Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24 |
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c01a6cc6 |
| 12-Apr-2023 |
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> |
arm64: dts: mediatek: mt6795: Add PMIC Wrapper node
Add the pwrap node: this is used to communicate with the PMIC(s).
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.
arm64: dts: mediatek: mt6795: Add PMIC Wrapper node
Add the pwrap node: this is used to communicate with the PMIC(s).
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230412112739.160376-22-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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06254e9f |
| 12-Apr-2023 |
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> |
arm64: dts: mediatek: mt6795: Add support for IOMMU and LARBs
Add nodes for the multimedia IOMMU and its LARBs: this includes all but the MJC LARB, which cannot currently be used and will be added l
arm64: dts: mediatek: mt6795: Add support for IOMMU and LARBs
Add nodes for the multimedia IOMMU and its LARBs: this includes all but the MJC LARB, which cannot currently be used and will be added later.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230412112739.160376-19-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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d9acc19b |
| 12-Apr-2023 |
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> |
arm64: dts: mediatek: mt6795: Add MMSYS node for multimedia clocks
Add the MultiMedia System node, providing clocks for the multimedia hardware blocks and their IOMMU/SMIs.
Signed-off-by: AngeloGio
arm64: dts: mediatek: mt6795: Add MMSYS node for multimedia clocks
Add the MultiMedia System node, providing clocks for the multimedia hardware blocks and their IOMMU/SMIs.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230412112739.160376-18-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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fee3d8ee |
| 12-Apr-2023 |
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> |
arm64: dts: mediatek: mt6795: Add support for the CMDQ/GCE mailbox
In preparation for adding multimedia blocks, add the CMDQ/GCE mailbox.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino
arm64: dts: mediatek: mt6795: Add support for the CMDQ/GCE mailbox
In preparation for adding multimedia blocks, add the CMDQ/GCE mailbox.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230412112739.160376-17-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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0dd58c07 |
| 12-Apr-2023 |
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> |
arm64: dts: mediatek: mt6795: Add tertiary PWM node
The PWM at 0x11006000 is the tertiary PWM; unlike PWM0, PWM1, this is not display specific and can be used as a generic PWM controller.
This node
arm64: dts: mediatek: mt6795: Add tertiary PWM node
The PWM at 0x11006000 is the tertiary PWM; unlike PWM0, PWM1, this is not display specific and can be used as a generic PWM controller.
This node is left disabled as usage is board-specific.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230412112739.160376-21-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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Revision tags: v6.1.23, v6.1.22 |
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7eb1f2c6 |
| 27-Mar-2023 |
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> |
arm64: dts: mediatek: mt6795: Add VDECSYS and VENCSYS clocks
In prepration for adding the IOMMUs and LARBs of this SoC, add the VDECSYS and VENCSYS clock controller nodes, providing clocks for the v
arm64: dts: mediatek: mt6795: Add VDECSYS and VENCSYS clocks
In prepration for adding the IOMMUs and LARBs of this SoC, add the VDECSYS and VENCSYS clock controller nodes, providing clocks for the vcodec stateful decoder and stateful decoder hardware.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230327083647.22017-11-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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80dd5ca5 |
| 27-Mar-2023 |
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> |
arm64: dts: mediatek: mt6795: Add SoC power domains
Add power domain tree for various hardware blocks on MT6795.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
arm64: dts: mediatek: mt6795: Add SoC power domains
Add power domain tree for various hardware blocks on MT6795.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230327083647.22017-7-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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80d9c073 |
| 27-Mar-2023 |
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> |
arm64: dts: mediatek: mt6795: Add nodes for I2C controllers
Add all four I2C controller nodes but keep them in disabled state as usage is board-dependant.
Signed-off-by: AngeloGioacchino Del Regno
arm64: dts: mediatek: mt6795: Add nodes for I2C controllers
Add all four I2C controller nodes but keep them in disabled state as usage is board-dependant.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230327083647.22017-6-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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befae66a |
| 27-Mar-2023 |
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> |
arm64: dts: mediatek: mt6795: Add apmixedsys syscon node
Add the APMIXEDSYS node, providing a syscon to the APMIXED iospace and also providing PLLs.
Signed-off-by: AngeloGioacchino Del Regno <angel
arm64: dts: mediatek: mt6795: Add apmixedsys syscon node
Add the APMIXEDSYS node, providing a syscon to the APMIXED iospace and also providing PLLs.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230327083647.22017-3-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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03a750a7 |
| 27-Mar-2023 |
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> |
arm64: dts: mediatek: mt6795: Add Frequency Hopping Controller node
Add FHCTL node but keep it disabled as the PLL clocks that should be handled through FHCTL and the Spread Spectrum Clocking parame
arm64: dts: mediatek: mt6795: Add Frequency Hopping Controller node
Add FHCTL node but keep it disabled as the PLL clocks that should be handled through FHCTL and the Spread Spectrum Clocking parameters are board specific.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230327083647.22017-2-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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Revision tags: v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12 |
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c5f30727 |
| 06-Dec-2022 |
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> |
arm64: dts: mt6795: Add complete CPU caches information
This SoC's AP subsystem has 8x Cortex-A53 CPUs, specifically, four CPUs per cluster, with two CPU clusters.
Each CPU has: - A 32KB I-cache,
arm64: dts: mt6795: Add complete CPU caches information
This SoC's AP subsystem has 8x Cortex-A53 CPUs, specifically, four CPUs per cluster, with two CPU clusters.
Each CPU has: - A 32KB I-cache, 2-way set associative; - A 32KB D-cache, 4-way set associative.
Each cluster has a unified 1MB L2 cache, 16-way set associative.
With that in mind, add the appropriate properties needed to specify the caches information for this SoC, which will now be correctly exported to sysfs.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221206112330.78431-6-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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Revision tags: v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79, v6.0.8, v5.15.78, v6.0.7, v5.15.77, v5.15.76, v6.0.6 |
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d83f8a42 |
| 27-Oct-2022 |
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> |
arm64: dts: mediatek: mt6795: Add support for eMMC/SD/SDIO controllers
Add the mmc nodes to support all of the four controllers, used for eMMC, SD/MicroSD and SDIO storage. All of these controller n
arm64: dts: mediatek: mt6795: Add support for eMMC/SD/SDIO controllers
Add the mmc nodes to support all of the four controllers, used for eMMC, SD/MicroSD and SDIO storage. All of these controller nodes are left disabled by default, as usage is board dependent.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221027095504.37432-5-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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09608ccc |
| 27-Oct-2022 |
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> |
arm64: dts: mediatek: mt6795: Add support for APDMA and wire up UART DMAs
This SoC has a DMA controller with tx/rx channels for all of the UART controller IPs: add the apdma node and wire up the DMA
arm64: dts: mediatek: mt6795: Add support for APDMA and wire up UART DMAs
This SoC has a DMA controller with tx/rx channels for all of the UART controller IPs: add the apdma node and wire up the DMAs on all controllers. When one of the UART controllers is used as a serial console, the DMA will be automatically ignored.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221027095504.37432-4-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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12a36f02 |
| 27-Oct-2022 |
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> |
arm64: dts: mediatek: mt6795: Replace UART dummy clocks with pericfg
The UART nodes had a dummy clock for early bringup, as it is expected that these are left on by the bootloader: now that the peri
arm64: dts: mediatek: mt6795: Replace UART dummy clocks with pericfg
The UART nodes had a dummy clock for early bringup, as it is expected that these are left on by the bootloader: now that the pericfg clock controller is supported, we can replace them with the real clocks.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221027095504.37432-3-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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f89afcfc |
| 27-Oct-2022 |
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> |
arm64: dts: mediatek: mt6795: Add topckgen, infra, peri clocks/resets
Add nodes for topckgen, infracfg and pericfg, providing various clocks and resets and needed to support basic IPs of this SoC.
arm64: dts: mediatek: mt6795: Add topckgen, infra, peri clocks/resets
Add nodes for topckgen, infracfg and pericfg, providing various clocks and resets and needed to support basic IPs of this SoC.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221027095504.37432-2-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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Revision tags: v6.0.5, v5.15.75, v6.0.4, v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71, v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64, v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58 |
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5ebb14aa |
| 29-Jul-2022 |
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> |
arm64: dts: mediatek: mt6795: Add CPUX system timer node
Add a node for mt6795-systimer: this is necessary to start the System Timer(s) for all cores, finally making CNTVCT_EL0 usable.
Signed-off-b
arm64: dts: mediatek: mt6795: Add CPUX system timer node
Add a node for mt6795-systimer: this is necessary to start the System Timer(s) for all cores, finally making CNTVCT_EL0 usable.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220729093536.27623-1-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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Revision tags: v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48, v5.15.47 |
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55fcff6c |
| 09-Jun-2022 |
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> |
arm64: dts: mediatek: mt6795: Specify interrupts for vGIC
Add the maintenance interrupt for GIC-400.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https:
arm64: dts: mediatek: mt6795: Specify interrupts for vGIC
Add the maintenance interrupt for GIC-400.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220609112303.117928-11-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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b888886a |
| 09-Jun-2022 |
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> |
arm64: dts: mediatek: mt6795: Add pinctrl controller node
Add a node for the pinctrl controller found on MT6795 but without configuration for any pin, as that's expected to be done in the machine-sp
arm64: dts: mediatek: mt6795: Add pinctrl controller node
Add a node for the pinctrl controller found on MT6795 but without configuration for any pin, as that's expected to be done in the machine-specific devicetrees.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220609112303.117928-10-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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01931ee6 |
| 09-Jun-2022 |
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> |
arm64: dts: mediatek: mt6795: Add ARM CCI-400 node and assign to CPUs
This SoC features an ARM CCI-400 IP: add the required node and assign the cci control ports to the CPU cores.
Signed-off-by: An
arm64: dts: mediatek: mt6795: Add ARM CCI-400 node and assign to CPUs
This SoC features an ARM CCI-400 IP: add the required node and assign the cci control ports to the CPU cores.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220609112303.117928-9-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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4c400f18 |
| 09-Jun-2022 |
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> |
arm64: dts: mediatek: mt6795: Add general purpose timer node
Add the timer node, enabling two GPTs, of which one will be used as sched_clock.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacc
arm64: dts: mediatek: mt6795: Add general purpose timer node
Add the timer node, enabling two GPTs, of which one will be used as sched_clock.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220609112303.117928-8-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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468deda8 |
| 09-Jun-2022 |
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> |
arm64: dts: mediatek: mt6795: Remove incorrect fixed-clocks
Remove the RTC and UART fixed clocks, as these were introduced to temporarily provide a dummy clock to devices: since the two 26M/32K fixe
arm64: dts: mediatek: mt6795: Remove incorrect fixed-clocks
Remove the RTC and UART fixed clocks, as these were introduced to temporarily provide a dummy clock to devices: since the two 26M/32K fixed oscillators clocks (which do really exist in the SoC) have been added, there's no reason to keep the aforementioned (and now redundant) dummies in this devicetree.
In order to remove the uart dummy clock, it was necessary to also reassign the clock of all UART nodes to clk26m.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220609112303.117928-7-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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d9fc72d5 |
| 09-Jun-2022 |
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> |
arm64: dts: mediatek: mt6795: Add fixed clocks for 32kHz and 26MHz XOs
Add the 32kHz and 26MHz oscillators as fixed clocks in devicetree to provide a good initial clock spec, since this SoC features
arm64: dts: mediatek: mt6795: Add fixed clocks for 32kHz and 26MHz XOs
Add the 32kHz and 26MHz oscillators as fixed clocks in devicetree to provide a good initial clock spec, since this SoC features two always on oscillators running at the aforementioned frequencies.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220609112303.117928-6-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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ac4cf9a2 |
| 09-Jun-2022 |
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> |
arm64: dts: mediatek: mt6795: Add watchdog node to avoid timeouts
At least on commercial devices like some smartphones, the bootloader will initialize the SoC watchdog and set it to reboot the board
arm64: dts: mediatek: mt6795: Add watchdog node to avoid timeouts
At least on commercial devices like some smartphones, the bootloader will initialize the SoC watchdog and set it to reboot the board when it times out. The last pet that this watchdog is getting is right before booting the kernel and left it enabled as a protection against boot failure: this means that Linux is expected to initialize this device and pet as soon as possible, or it will bark and reset the AP.
In order to prevent that, add the required watchdog node as default enabled: this will have no side effects on boards that are not performing the aforementioned watchdog setup before booting Linux.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220609112303.117928-5-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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5fce1e6c |
| 09-Jun-2022 |
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> |
arm64: dts: mediatek: mt6795: Add Cortex A53 PMU nodes
Add the required nodes to enable the PMU on this SoC.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link
arm64: dts: mediatek: mt6795: Add Cortex A53 PMU nodes
Add the required nodes to enable the PMU on this SoC.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220609112303.117928-4-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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f48d4867 |
| 09-Jun-2022 |
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> |
arm64: dts: mediatek: mt6795: Add cpu-map and L2 cache
This SoC is HMP and has two clusters with four Cortex-A53 cores each: declare a cpu map and, while at it, also add the next-level-cache propert
arm64: dts: mediatek: mt6795: Add cpu-map and L2 cache
This SoC is HMP and has two clusters with four Cortex-A53 cores each: declare a cpu map and, while at it, also add the next-level-cache properties.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220609112303.117928-3-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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