1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2015 MediaTek Inc. 4 * Author: Mars.C <mars.cheng@mediatek.com> 5 */ 6 7#include <dt-bindings/interrupt-controller/irq.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/mediatek,mt6795-clk.h> 10#include <dt-bindings/gce/mediatek,mt6795-gce.h> 11#include <dt-bindings/pinctrl/mt6795-pinfunc.h> 12#include <dt-bindings/power/mt6795-power.h> 13#include <dt-bindings/reset/mediatek,mt6795-resets.h> 14 15/ { 16 compatible = "mediatek,mt6795"; 17 interrupt-parent = <&sysirq>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 psci { 22 compatible = "arm,psci-0.2"; 23 method = "smc"; 24 }; 25 26 cpus { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 cpu0: cpu@0 { 31 device_type = "cpu"; 32 compatible = "arm,cortex-a53"; 33 enable-method = "psci"; 34 reg = <0x000>; 35 cci-control-port = <&cci_control2>; 36 next-level-cache = <&l2_0>; 37 }; 38 39 cpu1: cpu@1 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a53"; 42 enable-method = "psci"; 43 reg = <0x001>; 44 cci-control-port = <&cci_control2>; 45 i-cache-size = <32768>; 46 i-cache-line-size = <64>; 47 i-cache-sets = <256>; 48 d-cache-size = <32768>; 49 d-cache-line-size = <64>; 50 d-cache-sets = <128>; 51 next-level-cache = <&l2_0>; 52 }; 53 54 cpu2: cpu@2 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a53"; 57 enable-method = "psci"; 58 reg = <0x002>; 59 cci-control-port = <&cci_control2>; 60 i-cache-size = <32768>; 61 i-cache-line-size = <64>; 62 i-cache-sets = <256>; 63 d-cache-size = <32768>; 64 d-cache-line-size = <64>; 65 d-cache-sets = <128>; 66 next-level-cache = <&l2_0>; 67 }; 68 69 cpu3: cpu@3 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a53"; 72 enable-method = "psci"; 73 reg = <0x003>; 74 cci-control-port = <&cci_control2>; 75 i-cache-size = <32768>; 76 i-cache-line-size = <64>; 77 i-cache-sets = <256>; 78 d-cache-size = <32768>; 79 d-cache-line-size = <64>; 80 d-cache-sets = <128>; 81 next-level-cache = <&l2_0>; 82 }; 83 84 cpu4: cpu@100 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a53"; 87 enable-method = "psci"; 88 reg = <0x100>; 89 cci-control-port = <&cci_control1>; 90 i-cache-size = <32768>; 91 i-cache-line-size = <64>; 92 i-cache-sets = <256>; 93 d-cache-size = <32768>; 94 d-cache-line-size = <64>; 95 d-cache-sets = <128>; 96 next-level-cache = <&l2_1>; 97 }; 98 99 cpu5: cpu@101 { 100 device_type = "cpu"; 101 compatible = "arm,cortex-a53"; 102 enable-method = "psci"; 103 reg = <0x101>; 104 cci-control-port = <&cci_control1>; 105 i-cache-size = <32768>; 106 i-cache-line-size = <64>; 107 i-cache-sets = <256>; 108 d-cache-size = <32768>; 109 d-cache-line-size = <64>; 110 d-cache-sets = <128>; 111 next-level-cache = <&l2_1>; 112 }; 113 114 cpu6: cpu@102 { 115 device_type = "cpu"; 116 compatible = "arm,cortex-a53"; 117 enable-method = "psci"; 118 reg = <0x102>; 119 cci-control-port = <&cci_control1>; 120 i-cache-size = <32768>; 121 i-cache-line-size = <64>; 122 i-cache-sets = <256>; 123 d-cache-size = <32768>; 124 d-cache-line-size = <64>; 125 d-cache-sets = <128>; 126 next-level-cache = <&l2_1>; 127 }; 128 129 cpu7: cpu@103 { 130 device_type = "cpu"; 131 compatible = "arm,cortex-a53"; 132 enable-method = "psci"; 133 reg = <0x103>; 134 cci-control-port = <&cci_control1>; 135 i-cache-size = <32768>; 136 i-cache-line-size = <64>; 137 i-cache-sets = <256>; 138 d-cache-size = <32768>; 139 d-cache-line-size = <64>; 140 d-cache-sets = <128>; 141 next-level-cache = <&l2_1>; 142 }; 143 144 cpu-map { 145 cluster0 { 146 core0 { 147 cpu = <&cpu0>; 148 }; 149 150 core1 { 151 cpu = <&cpu1>; 152 }; 153 154 core2 { 155 cpu = <&cpu2>; 156 }; 157 158 core3 { 159 cpu = <&cpu3>; 160 }; 161 }; 162 163 cluster1 { 164 core0 { 165 cpu = <&cpu4>; 166 }; 167 168 core1 { 169 cpu = <&cpu5>; 170 }; 171 172 core2 { 173 cpu = <&cpu6>; 174 }; 175 176 core3 { 177 cpu = <&cpu7>; 178 }; 179 }; 180 }; 181 182 l2_0: l2-cache0 { 183 compatible = "cache"; 184 cache-level = <2>; 185 cache-size = <1048576>; 186 cache-line-size = <64>; 187 cache-sets = <1024>; 188 cache-unified; 189 }; 190 191 l2_1: l2-cache1 { 192 compatible = "cache"; 193 cache-level = <2>; 194 cache-size = <1048576>; 195 cache-line-size = <64>; 196 cache-sets = <1024>; 197 cache-unified; 198 }; 199 }; 200 201 clk26m: oscillator-26m { 202 compatible = "fixed-clock"; 203 #clock-cells = <0>; 204 clock-frequency = <26000000>; 205 clock-output-names = "clk26m"; 206 }; 207 208 clk32k: oscillator-32k { 209 compatible = "fixed-clock"; 210 #clock-cells = <0>; 211 clock-frequency = <32000>; 212 clock-output-names = "clk32k"; 213 }; 214 215 system_clk: dummy13m { 216 compatible = "fixed-clock"; 217 clock-frequency = <13000000>; 218 #clock-cells = <0>; 219 }; 220 221 pmu { 222 compatible = "arm,cortex-a53-pmu"; 223 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>, 224 <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>, 225 <GIC_SPI 10 IRQ_TYPE_LEVEL_LOW>, 226 <GIC_SPI 11 IRQ_TYPE_LEVEL_LOW>; 227 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 228 }; 229 230 timer { 231 compatible = "arm,armv8-timer"; 232 interrupt-parent = <&gic>; 233 interrupts = <GIC_PPI 13 234 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 235 <GIC_PPI 14 236 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 237 <GIC_PPI 11 238 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 239 <GIC_PPI 10 240 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 241 }; 242 243 soc { 244 #address-cells = <2>; 245 #size-cells = <2>; 246 compatible = "simple-bus"; 247 ranges; 248 249 topckgen: syscon@10000000 { 250 compatible = "mediatek,mt6795-topckgen", "syscon"; 251 reg = <0 0x10000000 0 0x1000>; 252 #clock-cells = <1>; 253 }; 254 255 infracfg: syscon@10001000 { 256 compatible = "mediatek,mt6795-infracfg", "syscon"; 257 reg = <0 0x10001000 0 0x1000>; 258 #clock-cells = <1>; 259 #reset-cells = <1>; 260 }; 261 262 pericfg: syscon@10003000 { 263 compatible = "mediatek,mt6795-pericfg", "syscon"; 264 reg = <0 0x10003000 0 0x1000>; 265 #clock-cells = <1>; 266 #reset-cells = <1>; 267 }; 268 269 scpsys: syscon@10006000 { 270 compatible = "syscon", "simple-mfd"; 271 reg = <0 0x10006000 0 0x1000>; 272 #power-domain-cells = <1>; 273 274 /* System Power Manager */ 275 spm: power-controller { 276 compatible = "mediatek,mt6795-power-controller"; 277 #address-cells = <1>; 278 #size-cells = <0>; 279 #power-domain-cells = <1>; 280 281 /* power domains of the SoC */ 282 power-domain@MT6795_POWER_DOMAIN_VDEC { 283 reg = <MT6795_POWER_DOMAIN_VDEC>; 284 clocks = <&topckgen CLK_TOP_MM_SEL>; 285 clock-names = "mm"; 286 #power-domain-cells = <0>; 287 }; 288 power-domain@MT6795_POWER_DOMAIN_VENC { 289 reg = <MT6795_POWER_DOMAIN_VENC>; 290 clocks = <&topckgen CLK_TOP_MM_SEL>, 291 <&topckgen CLK_TOP_VENC_SEL>; 292 clock-names = "mm", "venc"; 293 #power-domain-cells = <0>; 294 }; 295 power-domain@MT6795_POWER_DOMAIN_ISP { 296 reg = <MT6795_POWER_DOMAIN_ISP>; 297 clocks = <&topckgen CLK_TOP_MM_SEL>; 298 clock-names = "mm"; 299 #power-domain-cells = <0>; 300 }; 301 302 power-domain@MT6795_POWER_DOMAIN_MM { 303 reg = <MT6795_POWER_DOMAIN_MM>; 304 clocks = <&topckgen CLK_TOP_MM_SEL>; 305 clock-names = "mm"; 306 #power-domain-cells = <0>; 307 mediatek,infracfg = <&infracfg>; 308 }; 309 310 power-domain@MT6795_POWER_DOMAIN_MJC { 311 reg = <MT6795_POWER_DOMAIN_MJC>; 312 clocks = <&topckgen CLK_TOP_MM_SEL>, 313 <&topckgen CLK_TOP_MJC_SEL>; 314 clock-names = "mm", "mjc"; 315 #power-domain-cells = <0>; 316 }; 317 318 power-domain@MT6795_POWER_DOMAIN_AUDIO { 319 reg = <MT6795_POWER_DOMAIN_AUDIO>; 320 #power-domain-cells = <0>; 321 }; 322 323 mfg_async: power-domain@MT6795_POWER_DOMAIN_MFG_ASYNC { 324 reg = <MT6795_POWER_DOMAIN_MFG_ASYNC>; 325 clocks = <&clk26m>; 326 clock-names = "mfg"; 327 #address-cells = <1>; 328 #size-cells = <0>; 329 #power-domain-cells = <1>; 330 331 power-domain@MT6795_POWER_DOMAIN_MFG_2D { 332 reg = <MT6795_POWER_DOMAIN_MFG_2D>; 333 #address-cells = <1>; 334 #size-cells = <0>; 335 #power-domain-cells = <1>; 336 337 power-domain@MT6795_POWER_DOMAIN_MFG { 338 reg = <MT6795_POWER_DOMAIN_MFG>; 339 #power-domain-cells = <0>; 340 mediatek,infracfg = <&infracfg>; 341 }; 342 }; 343 }; 344 }; 345 }; 346 347 pio: pinctrl@10005000 { 348 compatible = "mediatek,mt6795-pinctrl"; 349 reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>; 350 reg-names = "base", "eint"; 351 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 352 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 353 gpio-controller; 354 #gpio-cells = <2>; 355 gpio-ranges = <&pio 0 0 196>; 356 interrupt-controller; 357 #interrupt-cells = <2>; 358 }; 359 360 watchdog: watchdog@10007000 { 361 compatible = "mediatek,mt6795-wdt"; 362 reg = <0 0x10007000 0 0x100>; 363 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>; 364 #reset-cells = <1>; 365 timeout-sec = <20>; 366 }; 367 368 timer: timer@10008000 { 369 compatible = "mediatek,mt6795-timer", 370 "mediatek,mt6577-timer"; 371 reg = <0 0x10008000 0 0x1000>; 372 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>; 373 clocks = <&system_clk>, <&clk32k>; 374 }; 375 376 sysirq: intpol-controller@10200620 { 377 compatible = "mediatek,mt6795-sysirq", 378 "mediatek,mt6577-sysirq"; 379 interrupt-controller; 380 #interrupt-cells = <3>; 381 interrupt-parent = <&gic>; 382 reg = <0 0x10200620 0 0x20>; 383 }; 384 385 systimer: timer@10200670 { 386 compatible = "mediatek,mt6795-systimer"; 387 reg = <0 0x10200670 0 0x10>; 388 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 389 clocks = <&system_clk>; 390 clock-names = "clk13m"; 391 }; 392 393 apmixedsys: syscon@10209000 { 394 compatible = "mediatek,mt6795-apmixedsys", "syscon"; 395 reg = <0 0x10209000 0 0x1000>; 396 #clock-cells = <1>; 397 }; 398 399 fhctl: clock-controller@10209f00 { 400 compatible = "mediatek,mt6795-fhctl"; 401 reg = <0 0x10209f00 0 0x100>; 402 status = "disabled"; 403 }; 404 405 gce: mailbox@10212000 { 406 compatible = "mediatek,mt6795-gce", "mediatek,mt8173-gce"; 407 reg = <0 0x10212000 0 0x1000>; 408 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>; 409 clocks = <&infracfg CLK_INFRA_GCE>; 410 clock-names = "gce"; 411 #mbox-cells = <2>; 412 }; 413 414 gic: interrupt-controller@10221000 { 415 compatible = "arm,gic-400"; 416 #interrupt-cells = <3>; 417 interrupt-parent = <&gic>; 418 interrupt-controller; 419 reg = <0 0x10221000 0 0x1000>, 420 <0 0x10222000 0 0x2000>, 421 <0 0x10224000 0 0x2000>, 422 <0 0x10226000 0 0x2000>; 423 interrupts = <GIC_PPI 9 424 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 425 }; 426 427 cci: cci@10390000 { 428 compatible = "arm,cci-400"; 429 #address-cells = <1>; 430 #size-cells = <1>; 431 reg = <0 0x10390000 0 0x1000>; 432 ranges = <0 0 0x10390000 0x10000>; 433 434 cci_control0: slave-if@1000 { 435 compatible = "arm,cci-400-ctrl-if"; 436 interface-type = "ace-lite"; 437 reg = <0x1000 0x1000>; 438 }; 439 440 cci_control1: slave-if@4000 { 441 compatible = "arm,cci-400-ctrl-if"; 442 interface-type = "ace"; 443 reg = <0x4000 0x1000>; 444 }; 445 446 cci_control2: slave-if@5000 { 447 compatible = "arm,cci-400-ctrl-if"; 448 interface-type = "ace"; 449 reg = <0x5000 0x1000>; 450 }; 451 452 pmu@9000 { 453 compatible = "arm,cci-400-pmu,r1"; 454 reg = <0x9000 0x5000>; 455 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 456 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 458 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 460 }; 461 }; 462 463 uart0: serial@11002000 { 464 compatible = "mediatek,mt6795-uart", 465 "mediatek,mt6577-uart"; 466 reg = <0 0x11002000 0 0x400>; 467 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 468 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 469 clock-names = "baud", "bus"; 470 dmas = <&apdma 0>, <&apdma 1>; 471 dma-names = "tx", "rx"; 472 status = "disabled"; 473 }; 474 475 uart1: serial@11003000 { 476 compatible = "mediatek,mt6795-uart", 477 "mediatek,mt6577-uart"; 478 reg = <0 0x11003000 0 0x400>; 479 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 480 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 481 clock-names = "baud", "bus"; 482 dmas = <&apdma 2>, <&apdma 3>; 483 dma-names = "tx", "rx"; 484 status = "disabled"; 485 }; 486 487 apdma: dma-controller@11000380 { 488 compatible = "mediatek,mt6795-uart-dma", 489 "mediatek,mt6577-uart-dma"; 490 reg = <0 0x11000380 0 0x60>, 491 <0 0x11000400 0 0x60>, 492 <0 0x11000480 0 0x60>, 493 <0 0x11000500 0 0x60>, 494 <0 0x11000580 0 0x60>, 495 <0 0x11000600 0 0x60>, 496 <0 0x11000680 0 0x60>, 497 <0 0x11000700 0 0x60>; 498 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>, 499 <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, 500 <GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>, 501 <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>, 502 <GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>, 503 <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>, 504 <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>, 505 <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 506 dma-requests = <8>; 507 clocks = <&pericfg CLK_PERI_AP_DMA>; 508 clock-names = "apdma"; 509 mediatek,dma-33bits; 510 #dma-cells = <1>; 511 }; 512 513 uart2: serial@11004000 { 514 compatible = "mediatek,mt6795-uart", 515 "mediatek,mt6577-uart"; 516 reg = <0 0x11004000 0 0x400>; 517 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 518 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 519 clock-names = "baud", "bus"; 520 dmas = <&apdma 4>, <&apdma 5>; 521 dma-names = "tx", "rx"; 522 status = "disabled"; 523 }; 524 525 uart3: serial@11005000 { 526 compatible = "mediatek,mt6795-uart", 527 "mediatek,mt6577-uart"; 528 reg = <0 0x11005000 0 0x400>; 529 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>; 530 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 531 clock-names = "baud", "bus"; 532 dmas = <&apdma 6>, <&apdma 7>; 533 dma-names = "tx", "rx"; 534 status = "disabled"; 535 }; 536 537 pwm2: pwm@11006000 { 538 compatible = "mediatek,mt6795-pwm"; 539 reg = <0 0x11006000 0 0x1000>; 540 #pwm-cells = <2>; 541 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 542 clocks = <&topckgen CLK_TOP_PWM_SEL>, 543 <&pericfg CLK_PERI_PWM>, 544 <&pericfg CLK_PERI_PWM1>, 545 <&pericfg CLK_PERI_PWM2>, 546 <&pericfg CLK_PERI_PWM3>, 547 <&pericfg CLK_PERI_PWM4>, 548 <&pericfg CLK_PERI_PWM5>, 549 <&pericfg CLK_PERI_PWM6>, 550 <&pericfg CLK_PERI_PWM7>; 551 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", 552 "pwm4", "pwm5", "pwm6", "pwm7"; 553 status = "disabled"; 554 }; 555 556 i2c0: i2c@11007000 { 557 compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c"; 558 reg = <0 0x11007000 0 0x70>, <0 0x11000100 0 0x80>; 559 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 560 clock-div = <16>; 561 clocks = <&pericfg CLK_PERI_I2C0>, <&pericfg CLK_PERI_AP_DMA>; 562 clock-names = "main", "dma"; 563 #address-cells = <1>; 564 #size-cells = <0>; 565 status = "disabled"; 566 }; 567 568 i2c1: i2c@11008000 { 569 compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c"; 570 reg = <0 0x11008000 0 0x70>, <0 0x11000180 0 0x80>; 571 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 572 clock-div = <16>; 573 clocks = <&pericfg CLK_PERI_I2C1>, <&pericfg CLK_PERI_AP_DMA>; 574 clock-names = "main", "dma"; 575 #address-cells = <1>; 576 #size-cells = <0>; 577 status = "disabled"; 578 }; 579 580 i2c2: i2c@11009000 { 581 compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c"; 582 reg = <0 0x11009000 0 0x70>, <0 0x11000200 0 0x80>; 583 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 584 clock-div = <16>; 585 clocks = <&pericfg CLK_PERI_I2C2>, <&pericfg CLK_PERI_AP_DMA>; 586 clock-names = "main", "dma"; 587 #address-cells = <1>; 588 #size-cells = <0>; 589 status = "disabled"; 590 }; 591 592 i2c3: i2c@11010000 { 593 compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c"; 594 reg = <0 0x11010000 0 0x70>, <0 0x11000280 0 0x80>; 595 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; 596 clock-div = <16>; 597 clocks = <&pericfg CLK_PERI_I2C3>, <&pericfg CLK_PERI_AP_DMA>; 598 clock-names = "main", "dma"; 599 #address-cells = <1>; 600 #size-cells = <0>; 601 status = "disabled"; 602 }; 603 604 i2c4: i2c@11011000 { 605 compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c"; 606 reg = <0 0x11011000 0 0x70>, <0 0x11000300 0 0x80>; 607 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>; 608 clock-div = <16>; 609 clocks = <&pericfg CLK_PERI_I2C4>, <&pericfg CLK_PERI_AP_DMA>; 610 clock-names = "main", "dma"; 611 #address-cells = <1>; 612 #size-cells = <0>; 613 status = "disabled"; 614 }; 615 616 mmc0: mmc@11230000 { 617 compatible = "mediatek,mt6795-mmc"; 618 reg = <0 0x11230000 0 0x1000>; 619 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 620 clocks = <&pericfg CLK_PERI_MSDC30_0>, 621 <&topckgen CLK_TOP_MSDC50_0_H_SEL>, 622 <&topckgen CLK_TOP_MSDC50_0_SEL>; 623 clock-names = "source", "hclk", "source_cg"; 624 status = "disabled"; 625 }; 626 627 mmc1: mmc@11240000 { 628 compatible = "mediatek,mt6795-mmc"; 629 reg = <0 0x11240000 0 0x1000>; 630 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 631 clocks = <&pericfg CLK_PERI_MSDC30_1>, 632 <&topckgen CLK_TOP_AXI_SEL>; 633 clock-names = "source", "hclk"; 634 status = "disabled"; 635 }; 636 637 mmc2: mmc@11250000 { 638 compatible = "mediatek,mt6795-mmc"; 639 reg = <0 0x11250000 0 0x1000>; 640 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 641 clocks = <&pericfg CLK_PERI_MSDC30_2>, 642 <&topckgen CLK_TOP_AXI_SEL>; 643 clock-names = "source", "hclk"; 644 status = "disabled"; 645 }; 646 647 mmc3: mmc@11260000 { 648 compatible = "mediatek,mt6795-mmc"; 649 reg = <0 0x11260000 0 0x1000>; 650 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 651 clocks = <&pericfg CLK_PERI_MSDC30_3>, 652 <&topckgen CLK_TOP_AXI_SEL>; 653 clock-names = "source", "hclk"; 654 status = "disabled"; 655 }; 656 657 mmsys: syscon@14000000 { 658 compatible = "mediatek,mt6795-mmsys", "syscon"; 659 reg = <0 0x14000000 0 0x1000>; 660 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 661 assigned-clocks = <&topckgen CLK_TOP_MM_SEL>; 662 assigned-clock-rates = <400000000>; 663 #clock-cells = <1>; 664 #reset-cells = <1>; 665 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, 666 <&gce 1 CMDQ_THR_PRIO_HIGHEST>; 667 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; 668 }; 669 670 vdecsys: clock-controller@16000000 { 671 compatible = "mediatek,mt6795-vdecsys"; 672 reg = <0 0x16000000 0 0x1000>; 673 #clock-cells = <1>; 674 }; 675 676 vencsys: clock-controller@18000000 { 677 compatible = "mediatek,mt6795-vencsys"; 678 reg = <0 0x18000000 0 0x1000>; 679 #clock-cells = <1>; 680 }; 681 }; 682}; 683