1/*
2 * Copyright (c) 2015 MediaTek Inc.
3 * Author: Mars.C <mars.cheng@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11 * GNU General Public License for more details.
12 */
13
14#include <dt-bindings/interrupt-controller/irq.h>
15#include <dt-bindings/interrupt-controller/arm-gic.h>
16
17/ {
18	compatible = "mediatek,mt6795";
19	interrupt-parent = <&sysirq>;
20	#address-cells = <2>;
21	#size-cells = <2>;
22
23	psci {
24		compatible = "arm,psci-0.2";
25		method = "smc";
26	};
27
28	cpus {
29		#address-cells = <1>;
30		#size-cells = <0>;
31
32		cpu0: cpu@0 {
33			device_type = "cpu";
34			compatible = "arm,cortex-a53";
35			enable-method = "psci";
36			reg = <0x000>;
37			next-level-cache = <&l2_0>;
38		};
39
40		cpu1: cpu@1 {
41			device_type = "cpu";
42			compatible = "arm,cortex-a53";
43			enable-method = "psci";
44			reg = <0x001>;
45			next-level-cache = <&l2_0>;
46		};
47
48		cpu2: cpu@2 {
49			device_type = "cpu";
50			compatible = "arm,cortex-a53";
51			enable-method = "psci";
52			reg = <0x002>;
53			next-level-cache = <&l2_0>;
54		};
55
56		cpu3: cpu@3 {
57			device_type = "cpu";
58			compatible = "arm,cortex-a53";
59			enable-method = "psci";
60			reg = <0x003>;
61			next-level-cache = <&l2_0>;
62		};
63
64		cpu4: cpu@100 {
65			device_type = "cpu";
66			compatible = "arm,cortex-a53";
67			enable-method = "psci";
68			reg = <0x100>;
69			next-level-cache = <&l2_1>;
70		};
71
72		cpu5: cpu@101 {
73			device_type = "cpu";
74			compatible = "arm,cortex-a53";
75			enable-method = "psci";
76			reg = <0x101>;
77			next-level-cache = <&l2_1>;
78		};
79
80		cpu6: cpu@102 {
81			device_type = "cpu";
82			compatible = "arm,cortex-a53";
83			enable-method = "psci";
84			reg = <0x102>;
85			next-level-cache = <&l2_1>;
86		};
87
88		cpu7: cpu@103 {
89			device_type = "cpu";
90			compatible = "arm,cortex-a53";
91			enable-method = "psci";
92			reg = <0x103>;
93			next-level-cache = <&l2_1>;
94		};
95
96		cpu-map {
97			cluster0 {
98				core0 {
99					cpu = <&cpu0>;
100				};
101
102				core1 {
103					cpu = <&cpu1>;
104				};
105
106				core2 {
107					cpu = <&cpu2>;
108				};
109
110				core3 {
111					cpu = <&cpu3>;
112				};
113			};
114
115			cluster1 {
116				core0 {
117					cpu = <&cpu4>;
118				};
119
120				core1 {
121					cpu = <&cpu5>;
122				};
123
124				core2 {
125					cpu = <&cpu6>;
126				};
127
128				core3 {
129					cpu = <&cpu7>;
130				};
131			};
132		};
133
134		l2_0: l2-cache0 {
135			compatible = "cache";
136			cache-level = <2>;
137		};
138
139		l2_1: l2-cache1 {
140			compatible = "cache";
141			cache-level = <2>;
142		};
143	};
144
145	system_clk: dummy13m {
146		compatible = "fixed-clock";
147		clock-frequency = <13000000>;
148		#clock-cells = <0>;
149	};
150
151	rtc_clk: dummy32k {
152		compatible = "fixed-clock";
153		clock-frequency = <32000>;
154		#clock-cells = <0>;
155	};
156
157	uart_clk: dummy26m {
158		compatible = "fixed-clock";
159		clock-frequency = <26000000>;
160		#clock-cells = <0>;
161	};
162
163	pmu {
164		compatible = "arm,cortex-a53-pmu";
165		interrupts = <GIC_SPI  8 IRQ_TYPE_LEVEL_LOW>,
166			     <GIC_SPI  9 IRQ_TYPE_LEVEL_LOW>,
167			     <GIC_SPI 10 IRQ_TYPE_LEVEL_LOW>,
168			     <GIC_SPI 11 IRQ_TYPE_LEVEL_LOW>;
169		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
170	};
171
172	timer {
173		compatible = "arm,armv8-timer";
174		interrupt-parent = <&gic>;
175		interrupts = <GIC_PPI 13
176			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
177			     <GIC_PPI 14
178			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
179			     <GIC_PPI 11
180			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
181			     <GIC_PPI 10
182			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
183	};
184
185	soc {
186		#address-cells = <2>;
187		#size-cells = <2>;
188		compatible = "simple-bus";
189		ranges;
190
191		watchdog: watchdog@10007000 {
192			compatible = "mediatek,mt6795-wdt";
193			reg = <0 0x10007000 0 0x100>;
194			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>;
195			#reset-cells = <1>;
196			timeout-sec = <20>;
197		};
198
199		sysirq: intpol-controller@10200620 {
200			compatible = "mediatek,mt6795-sysirq",
201				     "mediatek,mt6577-sysirq";
202			interrupt-controller;
203			#interrupt-cells = <3>;
204			interrupt-parent = <&gic>;
205			reg = <0 0x10200620 0 0x20>;
206		};
207
208		gic: interrupt-controller@10221000 {
209			compatible = "arm,gic-400";
210			#interrupt-cells = <3>;
211			interrupt-parent = <&gic>;
212			interrupt-controller;
213			reg = <0 0x10221000 0 0x1000>,
214			      <0 0x10222000 0 0x2000>,
215			      <0 0x10224000 0 0x2000>,
216			      <0 0x10226000 0 0x2000>;
217		};
218
219		uart0: serial@11002000 {
220			compatible = "mediatek,mt6795-uart",
221				     "mediatek,mt6577-uart";
222			reg = <0 0x11002000 0 0x400>;
223			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
224			clocks = <&uart_clk>;
225			status = "disabled";
226		};
227
228		uart1: serial@11003000 {
229			compatible = "mediatek,mt6795-uart",
230				     "mediatek,mt6577-uart";
231			reg = <0 0x11003000 0 0x400>;
232			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
233			clocks = <&uart_clk>;
234			status = "disabled";
235		};
236
237		uart2: serial@11004000 {
238			compatible = "mediatek,mt6795-uart",
239				     "mediatek,mt6577-uart";
240			reg = <0 0x11004000 0 0x400>;
241			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
242			clocks = <&uart_clk>;
243			status = "disabled";
244		};
245
246		uart3: serial@11005000 {
247			compatible = "mediatek,mt6795-uart",
248				     "mediatek,mt6577-uart";
249			reg = <0 0x11005000 0 0x400>;
250			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
251			clocks = <&uart_clk>;
252			status = "disabled";
253		};
254	};
255};
256