1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2015 MediaTek Inc. 4 * Author: Mars.C <mars.cheng@mediatek.com> 5 */ 6 7#include <dt-bindings/interrupt-controller/irq.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/mediatek,mt6795-clk.h> 10#include <dt-bindings/pinctrl/mt6795-pinfunc.h> 11#include <dt-bindings/reset/mediatek,mt6795-resets.h> 12 13/ { 14 compatible = "mediatek,mt6795"; 15 interrupt-parent = <&sysirq>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 psci { 20 compatible = "arm,psci-0.2"; 21 method = "smc"; 22 }; 23 24 cpus { 25 #address-cells = <1>; 26 #size-cells = <0>; 27 28 cpu0: cpu@0 { 29 device_type = "cpu"; 30 compatible = "arm,cortex-a53"; 31 enable-method = "psci"; 32 reg = <0x000>; 33 cci-control-port = <&cci_control2>; 34 next-level-cache = <&l2_0>; 35 }; 36 37 cpu1: cpu@1 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a53"; 40 enable-method = "psci"; 41 reg = <0x001>; 42 cci-control-port = <&cci_control2>; 43 i-cache-size = <32768>; 44 i-cache-line-size = <64>; 45 i-cache-sets = <256>; 46 d-cache-size = <32768>; 47 d-cache-line-size = <64>; 48 d-cache-sets = <128>; 49 next-level-cache = <&l2_0>; 50 }; 51 52 cpu2: cpu@2 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a53"; 55 enable-method = "psci"; 56 reg = <0x002>; 57 cci-control-port = <&cci_control2>; 58 i-cache-size = <32768>; 59 i-cache-line-size = <64>; 60 i-cache-sets = <256>; 61 d-cache-size = <32768>; 62 d-cache-line-size = <64>; 63 d-cache-sets = <128>; 64 next-level-cache = <&l2_0>; 65 }; 66 67 cpu3: cpu@3 { 68 device_type = "cpu"; 69 compatible = "arm,cortex-a53"; 70 enable-method = "psci"; 71 reg = <0x003>; 72 cci-control-port = <&cci_control2>; 73 i-cache-size = <32768>; 74 i-cache-line-size = <64>; 75 i-cache-sets = <256>; 76 d-cache-size = <32768>; 77 d-cache-line-size = <64>; 78 d-cache-sets = <128>; 79 next-level-cache = <&l2_0>; 80 }; 81 82 cpu4: cpu@100 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a53"; 85 enable-method = "psci"; 86 reg = <0x100>; 87 cci-control-port = <&cci_control1>; 88 i-cache-size = <32768>; 89 i-cache-line-size = <64>; 90 i-cache-sets = <256>; 91 d-cache-size = <32768>; 92 d-cache-line-size = <64>; 93 d-cache-sets = <128>; 94 next-level-cache = <&l2_1>; 95 }; 96 97 cpu5: cpu@101 { 98 device_type = "cpu"; 99 compatible = "arm,cortex-a53"; 100 enable-method = "psci"; 101 reg = <0x101>; 102 cci-control-port = <&cci_control1>; 103 i-cache-size = <32768>; 104 i-cache-line-size = <64>; 105 i-cache-sets = <256>; 106 d-cache-size = <32768>; 107 d-cache-line-size = <64>; 108 d-cache-sets = <128>; 109 next-level-cache = <&l2_1>; 110 }; 111 112 cpu6: cpu@102 { 113 device_type = "cpu"; 114 compatible = "arm,cortex-a53"; 115 enable-method = "psci"; 116 reg = <0x102>; 117 cci-control-port = <&cci_control1>; 118 i-cache-size = <32768>; 119 i-cache-line-size = <64>; 120 i-cache-sets = <256>; 121 d-cache-size = <32768>; 122 d-cache-line-size = <64>; 123 d-cache-sets = <128>; 124 next-level-cache = <&l2_1>; 125 }; 126 127 cpu7: cpu@103 { 128 device_type = "cpu"; 129 compatible = "arm,cortex-a53"; 130 enable-method = "psci"; 131 reg = <0x103>; 132 cci-control-port = <&cci_control1>; 133 i-cache-size = <32768>; 134 i-cache-line-size = <64>; 135 i-cache-sets = <256>; 136 d-cache-size = <32768>; 137 d-cache-line-size = <64>; 138 d-cache-sets = <128>; 139 next-level-cache = <&l2_1>; 140 }; 141 142 cpu-map { 143 cluster0 { 144 core0 { 145 cpu = <&cpu0>; 146 }; 147 148 core1 { 149 cpu = <&cpu1>; 150 }; 151 152 core2 { 153 cpu = <&cpu2>; 154 }; 155 156 core3 { 157 cpu = <&cpu3>; 158 }; 159 }; 160 161 cluster1 { 162 core0 { 163 cpu = <&cpu4>; 164 }; 165 166 core1 { 167 cpu = <&cpu5>; 168 }; 169 170 core2 { 171 cpu = <&cpu6>; 172 }; 173 174 core3 { 175 cpu = <&cpu7>; 176 }; 177 }; 178 }; 179 180 l2_0: l2-cache0 { 181 compatible = "cache"; 182 cache-level = <2>; 183 cache-size = <1048576>; 184 cache-line-size = <64>; 185 cache-sets = <1024>; 186 cache-unified; 187 }; 188 189 l2_1: l2-cache1 { 190 compatible = "cache"; 191 cache-level = <2>; 192 cache-size = <1048576>; 193 cache-line-size = <64>; 194 cache-sets = <1024>; 195 cache-unified; 196 }; 197 }; 198 199 clk26m: oscillator-26m { 200 compatible = "fixed-clock"; 201 #clock-cells = <0>; 202 clock-frequency = <26000000>; 203 clock-output-names = "clk26m"; 204 }; 205 206 clk32k: oscillator-32k { 207 compatible = "fixed-clock"; 208 #clock-cells = <0>; 209 clock-frequency = <32000>; 210 clock-output-names = "clk32k"; 211 }; 212 213 system_clk: dummy13m { 214 compatible = "fixed-clock"; 215 clock-frequency = <13000000>; 216 #clock-cells = <0>; 217 }; 218 219 pmu { 220 compatible = "arm,cortex-a53-pmu"; 221 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>, 222 <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>, 223 <GIC_SPI 10 IRQ_TYPE_LEVEL_LOW>, 224 <GIC_SPI 11 IRQ_TYPE_LEVEL_LOW>; 225 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 226 }; 227 228 timer { 229 compatible = "arm,armv8-timer"; 230 interrupt-parent = <&gic>; 231 interrupts = <GIC_PPI 13 232 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 233 <GIC_PPI 14 234 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 235 <GIC_PPI 11 236 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 237 <GIC_PPI 10 238 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 239 }; 240 241 soc { 242 #address-cells = <2>; 243 #size-cells = <2>; 244 compatible = "simple-bus"; 245 ranges; 246 247 topckgen: syscon@10000000 { 248 compatible = "mediatek,mt6795-topckgen", "syscon"; 249 reg = <0 0x10000000 0 0x1000>; 250 #clock-cells = <1>; 251 }; 252 253 infracfg: syscon@10001000 { 254 compatible = "mediatek,mt6795-infracfg", "syscon"; 255 reg = <0 0x10001000 0 0x1000>; 256 #clock-cells = <1>; 257 #reset-cells = <1>; 258 }; 259 260 pericfg: syscon@10003000 { 261 compatible = "mediatek,mt6795-pericfg", "syscon"; 262 reg = <0 0x10003000 0 0x1000>; 263 #clock-cells = <1>; 264 #reset-cells = <1>; 265 }; 266 267 pio: pinctrl@10005000 { 268 compatible = "mediatek,mt6795-pinctrl"; 269 reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>; 270 reg-names = "base", "eint"; 271 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 272 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 273 gpio-controller; 274 #gpio-cells = <2>; 275 gpio-ranges = <&pio 0 0 196>; 276 interrupt-controller; 277 #interrupt-cells = <2>; 278 }; 279 280 watchdog: watchdog@10007000 { 281 compatible = "mediatek,mt6795-wdt"; 282 reg = <0 0x10007000 0 0x100>; 283 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>; 284 #reset-cells = <1>; 285 timeout-sec = <20>; 286 }; 287 288 timer: timer@10008000 { 289 compatible = "mediatek,mt6795-timer", 290 "mediatek,mt6577-timer"; 291 reg = <0 0x10008000 0 0x1000>; 292 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>; 293 clocks = <&system_clk>, <&clk32k>; 294 }; 295 296 sysirq: intpol-controller@10200620 { 297 compatible = "mediatek,mt6795-sysirq", 298 "mediatek,mt6577-sysirq"; 299 interrupt-controller; 300 #interrupt-cells = <3>; 301 interrupt-parent = <&gic>; 302 reg = <0 0x10200620 0 0x20>; 303 }; 304 305 systimer: timer@10200670 { 306 compatible = "mediatek,mt6795-systimer"; 307 reg = <0 0x10200670 0 0x10>; 308 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 309 clocks = <&system_clk>; 310 clock-names = "clk13m"; 311 }; 312 313 apmixedsys: syscon@10209000 { 314 compatible = "mediatek,mt6795-apmixedsys", "syscon"; 315 reg = <0 0x10209000 0 0x1000>; 316 #clock-cells = <1>; 317 }; 318 319 fhctl: clock-controller@10209f00 { 320 compatible = "mediatek,mt6795-fhctl"; 321 reg = <0 0x10209f00 0 0x100>; 322 status = "disabled"; 323 }; 324 325 gic: interrupt-controller@10221000 { 326 compatible = "arm,gic-400"; 327 #interrupt-cells = <3>; 328 interrupt-parent = <&gic>; 329 interrupt-controller; 330 reg = <0 0x10221000 0 0x1000>, 331 <0 0x10222000 0 0x2000>, 332 <0 0x10224000 0 0x2000>, 333 <0 0x10226000 0 0x2000>; 334 interrupts = <GIC_PPI 9 335 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 336 }; 337 338 cci: cci@10390000 { 339 compatible = "arm,cci-400"; 340 #address-cells = <1>; 341 #size-cells = <1>; 342 reg = <0 0x10390000 0 0x1000>; 343 ranges = <0 0 0x10390000 0x10000>; 344 345 cci_control0: slave-if@1000 { 346 compatible = "arm,cci-400-ctrl-if"; 347 interface-type = "ace-lite"; 348 reg = <0x1000 0x1000>; 349 }; 350 351 cci_control1: slave-if@4000 { 352 compatible = "arm,cci-400-ctrl-if"; 353 interface-type = "ace"; 354 reg = <0x4000 0x1000>; 355 }; 356 357 cci_control2: slave-if@5000 { 358 compatible = "arm,cci-400-ctrl-if"; 359 interface-type = "ace"; 360 reg = <0x5000 0x1000>; 361 }; 362 363 pmu@9000 { 364 compatible = "arm,cci-400-pmu,r1"; 365 reg = <0x9000 0x5000>; 366 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 367 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 368 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 369 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 370 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 371 }; 372 }; 373 374 uart0: serial@11002000 { 375 compatible = "mediatek,mt6795-uart", 376 "mediatek,mt6577-uart"; 377 reg = <0 0x11002000 0 0x400>; 378 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 379 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 380 clock-names = "baud", "bus"; 381 dmas = <&apdma 0>, <&apdma 1>; 382 dma-names = "tx", "rx"; 383 status = "disabled"; 384 }; 385 386 uart1: serial@11003000 { 387 compatible = "mediatek,mt6795-uart", 388 "mediatek,mt6577-uart"; 389 reg = <0 0x11003000 0 0x400>; 390 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 391 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 392 clock-names = "baud", "bus"; 393 dmas = <&apdma 2>, <&apdma 3>; 394 dma-names = "tx", "rx"; 395 status = "disabled"; 396 }; 397 398 apdma: dma-controller@11000380 { 399 compatible = "mediatek,mt6795-uart-dma", 400 "mediatek,mt6577-uart-dma"; 401 reg = <0 0x11000380 0 0x60>, 402 <0 0x11000400 0 0x60>, 403 <0 0x11000480 0 0x60>, 404 <0 0x11000500 0 0x60>, 405 <0 0x11000580 0 0x60>, 406 <0 0x11000600 0 0x60>, 407 <0 0x11000680 0 0x60>, 408 <0 0x11000700 0 0x60>; 409 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>, 410 <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, 411 <GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>, 412 <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>, 413 <GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>, 414 <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>, 415 <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>, 416 <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 417 dma-requests = <8>; 418 clocks = <&pericfg CLK_PERI_AP_DMA>; 419 clock-names = "apdma"; 420 mediatek,dma-33bits; 421 #dma-cells = <1>; 422 }; 423 424 uart2: serial@11004000 { 425 compatible = "mediatek,mt6795-uart", 426 "mediatek,mt6577-uart"; 427 reg = <0 0x11004000 0 0x400>; 428 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 429 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 430 clock-names = "baud", "bus"; 431 dmas = <&apdma 4>, <&apdma 5>; 432 dma-names = "tx", "rx"; 433 status = "disabled"; 434 }; 435 436 uart3: serial@11005000 { 437 compatible = "mediatek,mt6795-uart", 438 "mediatek,mt6577-uart"; 439 reg = <0 0x11005000 0 0x400>; 440 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>; 441 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 442 clock-names = "baud", "bus"; 443 dmas = <&apdma 6>, <&apdma 7>; 444 dma-names = "tx", "rx"; 445 status = "disabled"; 446 }; 447 448 i2c0: i2c@11007000 { 449 compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c"; 450 reg = <0 0x11007000 0 0x70>, <0 0x11000100 0 0x80>; 451 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 452 clock-div = <16>; 453 clocks = <&pericfg CLK_PERI_I2C0>, <&pericfg CLK_PERI_AP_DMA>; 454 clock-names = "main", "dma"; 455 #address-cells = <1>; 456 #size-cells = <0>; 457 status = "disabled"; 458 }; 459 460 i2c1: i2c@11008000 { 461 compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c"; 462 reg = <0 0x11008000 0 0x70>, <0 0x11000180 0 0x80>; 463 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 464 clock-div = <16>; 465 clocks = <&pericfg CLK_PERI_I2C1>, <&pericfg CLK_PERI_AP_DMA>; 466 clock-names = "main", "dma"; 467 #address-cells = <1>; 468 #size-cells = <0>; 469 status = "disabled"; 470 }; 471 472 i2c2: i2c@11009000 { 473 compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c"; 474 reg = <0 0x11009000 0 0x70>, <0 0x11000200 0 0x80>; 475 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 476 clock-div = <16>; 477 clocks = <&pericfg CLK_PERI_I2C2>, <&pericfg CLK_PERI_AP_DMA>; 478 clock-names = "main", "dma"; 479 #address-cells = <1>; 480 #size-cells = <0>; 481 status = "disabled"; 482 }; 483 484 i2c3: i2c@11010000 { 485 compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c"; 486 reg = <0 0x11010000 0 0x70>, <0 0x11000280 0 0x80>; 487 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; 488 clock-div = <16>; 489 clocks = <&pericfg CLK_PERI_I2C3>, <&pericfg CLK_PERI_AP_DMA>; 490 clock-names = "main", "dma"; 491 #address-cells = <1>; 492 #size-cells = <0>; 493 status = "disabled"; 494 }; 495 496 i2c4: i2c@11011000 { 497 compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c"; 498 reg = <0 0x11011000 0 0x70>, <0 0x11000300 0 0x80>; 499 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>; 500 clock-div = <16>; 501 clocks = <&pericfg CLK_PERI_I2C4>, <&pericfg CLK_PERI_AP_DMA>; 502 clock-names = "main", "dma"; 503 #address-cells = <1>; 504 #size-cells = <0>; 505 status = "disabled"; 506 }; 507 508 mmc0: mmc@11230000 { 509 compatible = "mediatek,mt6795-mmc"; 510 reg = <0 0x11230000 0 0x1000>; 511 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 512 clocks = <&pericfg CLK_PERI_MSDC30_0>, 513 <&topckgen CLK_TOP_MSDC50_0_H_SEL>, 514 <&topckgen CLK_TOP_MSDC50_0_SEL>; 515 clock-names = "source", "hclk", "source_cg"; 516 status = "disabled"; 517 }; 518 519 mmc1: mmc@11240000 { 520 compatible = "mediatek,mt6795-mmc"; 521 reg = <0 0x11240000 0 0x1000>; 522 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 523 clocks = <&pericfg CLK_PERI_MSDC30_1>, 524 <&topckgen CLK_TOP_AXI_SEL>; 525 clock-names = "source", "hclk"; 526 status = "disabled"; 527 }; 528 529 mmc2: mmc@11250000 { 530 compatible = "mediatek,mt6795-mmc"; 531 reg = <0 0x11250000 0 0x1000>; 532 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 533 clocks = <&pericfg CLK_PERI_MSDC30_2>, 534 <&topckgen CLK_TOP_AXI_SEL>; 535 clock-names = "source", "hclk"; 536 status = "disabled"; 537 }; 538 539 mmc3: mmc@11260000 { 540 compatible = "mediatek,mt6795-mmc"; 541 reg = <0 0x11260000 0 0x1000>; 542 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 543 clocks = <&pericfg CLK_PERI_MSDC30_3>, 544 <&topckgen CLK_TOP_AXI_SEL>; 545 clock-names = "source", "hclk"; 546 status = "disabled"; 547 }; 548 }; 549}; 550