1/*
2 * Copyright (c) 2015 MediaTek Inc.
3 * Author: Mars.C <mars.cheng@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11 * GNU General Public License for more details.
12 */
13
14#include <dt-bindings/interrupt-controller/irq.h>
15#include <dt-bindings/interrupt-controller/arm-gic.h>
16#include <dt-bindings/pinctrl/mt6795-pinfunc.h>
17
18/ {
19	compatible = "mediatek,mt6795";
20	interrupt-parent = <&sysirq>;
21	#address-cells = <2>;
22	#size-cells = <2>;
23
24	psci {
25		compatible = "arm,psci-0.2";
26		method = "smc";
27	};
28
29	cpus {
30		#address-cells = <1>;
31		#size-cells = <0>;
32
33		cpu0: cpu@0 {
34			device_type = "cpu";
35			compatible = "arm,cortex-a53";
36			enable-method = "psci";
37			reg = <0x000>;
38			cci-control-port = <&cci_control2>;
39			next-level-cache = <&l2_0>;
40		};
41
42		cpu1: cpu@1 {
43			device_type = "cpu";
44			compatible = "arm,cortex-a53";
45			enable-method = "psci";
46			reg = <0x001>;
47			cci-control-port = <&cci_control2>;
48			next-level-cache = <&l2_0>;
49		};
50
51		cpu2: cpu@2 {
52			device_type = "cpu";
53			compatible = "arm,cortex-a53";
54			enable-method = "psci";
55			reg = <0x002>;
56			cci-control-port = <&cci_control2>;
57			next-level-cache = <&l2_0>;
58		};
59
60		cpu3: cpu@3 {
61			device_type = "cpu";
62			compatible = "arm,cortex-a53";
63			enable-method = "psci";
64			reg = <0x003>;
65			cci-control-port = <&cci_control2>;
66			next-level-cache = <&l2_0>;
67		};
68
69		cpu4: cpu@100 {
70			device_type = "cpu";
71			compatible = "arm,cortex-a53";
72			enable-method = "psci";
73			reg = <0x100>;
74			cci-control-port = <&cci_control1>;
75			next-level-cache = <&l2_1>;
76		};
77
78		cpu5: cpu@101 {
79			device_type = "cpu";
80			compatible = "arm,cortex-a53";
81			enable-method = "psci";
82			reg = <0x101>;
83			cci-control-port = <&cci_control1>;
84			next-level-cache = <&l2_1>;
85		};
86
87		cpu6: cpu@102 {
88			device_type = "cpu";
89			compatible = "arm,cortex-a53";
90			enable-method = "psci";
91			reg = <0x102>;
92			cci-control-port = <&cci_control1>;
93			next-level-cache = <&l2_1>;
94		};
95
96		cpu7: cpu@103 {
97			device_type = "cpu";
98			compatible = "arm,cortex-a53";
99			enable-method = "psci";
100			reg = <0x103>;
101			cci-control-port = <&cci_control1>;
102			next-level-cache = <&l2_1>;
103		};
104
105		cpu-map {
106			cluster0 {
107				core0 {
108					cpu = <&cpu0>;
109				};
110
111				core1 {
112					cpu = <&cpu1>;
113				};
114
115				core2 {
116					cpu = <&cpu2>;
117				};
118
119				core3 {
120					cpu = <&cpu3>;
121				};
122			};
123
124			cluster1 {
125				core0 {
126					cpu = <&cpu4>;
127				};
128
129				core1 {
130					cpu = <&cpu5>;
131				};
132
133				core2 {
134					cpu = <&cpu6>;
135				};
136
137				core3 {
138					cpu = <&cpu7>;
139				};
140			};
141		};
142
143		l2_0: l2-cache0 {
144			compatible = "cache";
145			cache-level = <2>;
146		};
147
148		l2_1: l2-cache1 {
149			compatible = "cache";
150			cache-level = <2>;
151		};
152	};
153
154	clk26m: oscillator-26m {
155		compatible = "fixed-clock";
156		#clock-cells = <0>;
157		clock-frequency = <26000000>;
158		clock-output-names = "clk26m";
159	};
160
161	clk32k: oscillator-32k {
162		compatible = "fixed-clock";
163		#clock-cells = <0>;
164		clock-frequency = <32000>;
165		clock-output-names = "clk32k";
166	};
167
168	system_clk: dummy13m {
169		compatible = "fixed-clock";
170		clock-frequency = <13000000>;
171		#clock-cells = <0>;
172	};
173
174	pmu {
175		compatible = "arm,cortex-a53-pmu";
176		interrupts = <GIC_SPI  8 IRQ_TYPE_LEVEL_LOW>,
177			     <GIC_SPI  9 IRQ_TYPE_LEVEL_LOW>,
178			     <GIC_SPI 10 IRQ_TYPE_LEVEL_LOW>,
179			     <GIC_SPI 11 IRQ_TYPE_LEVEL_LOW>;
180		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
181	};
182
183	timer {
184		compatible = "arm,armv8-timer";
185		interrupt-parent = <&gic>;
186		interrupts = <GIC_PPI 13
187			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
188			     <GIC_PPI 14
189			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
190			     <GIC_PPI 11
191			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
192			     <GIC_PPI 10
193			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
194	};
195
196	soc {
197		#address-cells = <2>;
198		#size-cells = <2>;
199		compatible = "simple-bus";
200		ranges;
201
202		pio: pinctrl@10005000 {
203			compatible = "mediatek,mt6795-pinctrl";
204			reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>;
205			reg-names = "base", "eint";
206			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
207				     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
208			gpio-controller;
209			#gpio-cells = <2>;
210			gpio-ranges = <&pio 0 0 196>;
211			interrupt-controller;
212			#interrupt-cells = <2>;
213		};
214
215		watchdog: watchdog@10007000 {
216			compatible = "mediatek,mt6795-wdt";
217			reg = <0 0x10007000 0 0x100>;
218			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>;
219			#reset-cells = <1>;
220			timeout-sec = <20>;
221		};
222
223		timer: timer@10008000 {
224			compatible = "mediatek,mt6795-timer",
225				     "mediatek,mt6577-timer";
226			reg = <0 0x10008000 0 0x1000>;
227			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
228			clocks = <&system_clk>, <&clk32k>;
229		};
230
231		sysirq: intpol-controller@10200620 {
232			compatible = "mediatek,mt6795-sysirq",
233				     "mediatek,mt6577-sysirq";
234			interrupt-controller;
235			#interrupt-cells = <3>;
236			interrupt-parent = <&gic>;
237			reg = <0 0x10200620 0 0x20>;
238		};
239
240		gic: interrupt-controller@10221000 {
241			compatible = "arm,gic-400";
242			#interrupt-cells = <3>;
243			interrupt-parent = <&gic>;
244			interrupt-controller;
245			reg = <0 0x10221000 0 0x1000>,
246			      <0 0x10222000 0 0x2000>,
247			      <0 0x10224000 0 0x2000>,
248			      <0 0x10226000 0 0x2000>;
249			interrupts = <GIC_PPI 9
250				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
251		};
252
253		cci: cci@10390000 {
254			compatible = "arm,cci-400";
255			#address-cells = <1>;
256			#size-cells = <1>;
257			reg = <0 0x10390000 0 0x1000>;
258			ranges = <0 0 0x10390000 0x10000>;
259
260			cci_control0: slave-if@1000 {
261				compatible = "arm,cci-400-ctrl-if";
262				interface-type = "ace-lite";
263				reg = <0x1000 0x1000>;
264			};
265
266			cci_control1: slave-if@4000 {
267				compatible = "arm,cci-400-ctrl-if";
268				interface-type = "ace";
269				reg = <0x4000 0x1000>;
270			};
271
272			cci_control2: slave-if@5000 {
273				compatible = "arm,cci-400-ctrl-if";
274				interface-type = "ace";
275				reg = <0x5000 0x1000>;
276			};
277
278			pmu@9000 {
279				compatible = "arm,cci-400-pmu,r1";
280				reg = <0x9000 0x5000>;
281				interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
282					     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
283					     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
284					     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
285					     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
286			};
287		};
288
289		uart0: serial@11002000 {
290			compatible = "mediatek,mt6795-uart",
291				     "mediatek,mt6577-uart";
292			reg = <0 0x11002000 0 0x400>;
293			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
294			clocks = <&clk26m>;
295			status = "disabled";
296		};
297
298		uart1: serial@11003000 {
299			compatible = "mediatek,mt6795-uart",
300				     "mediatek,mt6577-uart";
301			reg = <0 0x11003000 0 0x400>;
302			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
303			clocks = <&clk26m>;
304			status = "disabled";
305		};
306
307		uart2: serial@11004000 {
308			compatible = "mediatek,mt6795-uart",
309				     "mediatek,mt6577-uart";
310			reg = <0 0x11004000 0 0x400>;
311			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
312			clocks = <&clk26m>;
313			status = "disabled";
314		};
315
316		uart3: serial@11005000 {
317			compatible = "mediatek,mt6795-uart",
318				     "mediatek,mt6577-uart";
319			reg = <0 0x11005000 0 0x400>;
320			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
321			clocks = <&clk26m>;
322			status = "disabled";
323		};
324	};
325};
326