1/* 2 * Copyright (c) 2015 MediaTek Inc. 3 * Author: Mars.C <mars.cheng@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14#include <dt-bindings/interrupt-controller/irq.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16 17/ { 18 compatible = "mediatek,mt6795"; 19 interrupt-parent = <&sysirq>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 psci { 24 compatible = "arm,psci-0.2"; 25 method = "smc"; 26 }; 27 28 cpus { 29 #address-cells = <1>; 30 #size-cells = <0>; 31 32 cpu0: cpu@0 { 33 device_type = "cpu"; 34 compatible = "arm,cortex-a53"; 35 enable-method = "psci"; 36 reg = <0x000>; 37 cci-control-port = <&cci_control2>; 38 next-level-cache = <&l2_0>; 39 }; 40 41 cpu1: cpu@1 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a53"; 44 enable-method = "psci"; 45 reg = <0x001>; 46 cci-control-port = <&cci_control2>; 47 next-level-cache = <&l2_0>; 48 }; 49 50 cpu2: cpu@2 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a53"; 53 enable-method = "psci"; 54 reg = <0x002>; 55 cci-control-port = <&cci_control2>; 56 next-level-cache = <&l2_0>; 57 }; 58 59 cpu3: cpu@3 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a53"; 62 enable-method = "psci"; 63 reg = <0x003>; 64 cci-control-port = <&cci_control2>; 65 next-level-cache = <&l2_0>; 66 }; 67 68 cpu4: cpu@100 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a53"; 71 enable-method = "psci"; 72 reg = <0x100>; 73 cci-control-port = <&cci_control1>; 74 next-level-cache = <&l2_1>; 75 }; 76 77 cpu5: cpu@101 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a53"; 80 enable-method = "psci"; 81 reg = <0x101>; 82 cci-control-port = <&cci_control1>; 83 next-level-cache = <&l2_1>; 84 }; 85 86 cpu6: cpu@102 { 87 device_type = "cpu"; 88 compatible = "arm,cortex-a53"; 89 enable-method = "psci"; 90 reg = <0x102>; 91 cci-control-port = <&cci_control1>; 92 next-level-cache = <&l2_1>; 93 }; 94 95 cpu7: cpu@103 { 96 device_type = "cpu"; 97 compatible = "arm,cortex-a53"; 98 enable-method = "psci"; 99 reg = <0x103>; 100 cci-control-port = <&cci_control1>; 101 next-level-cache = <&l2_1>; 102 }; 103 104 cpu-map { 105 cluster0 { 106 core0 { 107 cpu = <&cpu0>; 108 }; 109 110 core1 { 111 cpu = <&cpu1>; 112 }; 113 114 core2 { 115 cpu = <&cpu2>; 116 }; 117 118 core3 { 119 cpu = <&cpu3>; 120 }; 121 }; 122 123 cluster1 { 124 core0 { 125 cpu = <&cpu4>; 126 }; 127 128 core1 { 129 cpu = <&cpu5>; 130 }; 131 132 core2 { 133 cpu = <&cpu6>; 134 }; 135 136 core3 { 137 cpu = <&cpu7>; 138 }; 139 }; 140 }; 141 142 l2_0: l2-cache0 { 143 compatible = "cache"; 144 cache-level = <2>; 145 }; 146 147 l2_1: l2-cache1 { 148 compatible = "cache"; 149 cache-level = <2>; 150 }; 151 }; 152 153 clk26m: oscillator-26m { 154 compatible = "fixed-clock"; 155 #clock-cells = <0>; 156 clock-frequency = <26000000>; 157 clock-output-names = "clk26m"; 158 }; 159 160 clk32k: oscillator-32k { 161 compatible = "fixed-clock"; 162 #clock-cells = <0>; 163 clock-frequency = <32000>; 164 clock-output-names = "clk32k"; 165 }; 166 167 system_clk: dummy13m { 168 compatible = "fixed-clock"; 169 clock-frequency = <13000000>; 170 #clock-cells = <0>; 171 }; 172 173 pmu { 174 compatible = "arm,cortex-a53-pmu"; 175 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>, 176 <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>, 177 <GIC_SPI 10 IRQ_TYPE_LEVEL_LOW>, 178 <GIC_SPI 11 IRQ_TYPE_LEVEL_LOW>; 179 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 180 }; 181 182 timer { 183 compatible = "arm,armv8-timer"; 184 interrupt-parent = <&gic>; 185 interrupts = <GIC_PPI 13 186 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 187 <GIC_PPI 14 188 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 189 <GIC_PPI 11 190 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 191 <GIC_PPI 10 192 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 193 }; 194 195 soc { 196 #address-cells = <2>; 197 #size-cells = <2>; 198 compatible = "simple-bus"; 199 ranges; 200 201 watchdog: watchdog@10007000 { 202 compatible = "mediatek,mt6795-wdt"; 203 reg = <0 0x10007000 0 0x100>; 204 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>; 205 #reset-cells = <1>; 206 timeout-sec = <20>; 207 }; 208 209 timer: timer@10008000 { 210 compatible = "mediatek,mt6795-timer", 211 "mediatek,mt6577-timer"; 212 reg = <0 0x10008000 0 0x1000>; 213 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>; 214 clocks = <&system_clk>, <&clk32k>; 215 }; 216 217 sysirq: intpol-controller@10200620 { 218 compatible = "mediatek,mt6795-sysirq", 219 "mediatek,mt6577-sysirq"; 220 interrupt-controller; 221 #interrupt-cells = <3>; 222 interrupt-parent = <&gic>; 223 reg = <0 0x10200620 0 0x20>; 224 }; 225 226 gic: interrupt-controller@10221000 { 227 compatible = "arm,gic-400"; 228 #interrupt-cells = <3>; 229 interrupt-parent = <&gic>; 230 interrupt-controller; 231 reg = <0 0x10221000 0 0x1000>, 232 <0 0x10222000 0 0x2000>, 233 <0 0x10224000 0 0x2000>, 234 <0 0x10226000 0 0x2000>; 235 }; 236 237 cci: cci@10390000 { 238 compatible = "arm,cci-400"; 239 #address-cells = <1>; 240 #size-cells = <1>; 241 reg = <0 0x10390000 0 0x1000>; 242 ranges = <0 0 0x10390000 0x10000>; 243 244 cci_control0: slave-if@1000 { 245 compatible = "arm,cci-400-ctrl-if"; 246 interface-type = "ace-lite"; 247 reg = <0x1000 0x1000>; 248 }; 249 250 cci_control1: slave-if@4000 { 251 compatible = "arm,cci-400-ctrl-if"; 252 interface-type = "ace"; 253 reg = <0x4000 0x1000>; 254 }; 255 256 cci_control2: slave-if@5000 { 257 compatible = "arm,cci-400-ctrl-if"; 258 interface-type = "ace"; 259 reg = <0x5000 0x1000>; 260 }; 261 262 pmu@9000 { 263 compatible = "arm,cci-400-pmu,r1"; 264 reg = <0x9000 0x5000>; 265 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 266 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 267 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 268 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 269 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 270 }; 271 }; 272 273 uart0: serial@11002000 { 274 compatible = "mediatek,mt6795-uart", 275 "mediatek,mt6577-uart"; 276 reg = <0 0x11002000 0 0x400>; 277 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 278 clocks = <&clk26m>; 279 status = "disabled"; 280 }; 281 282 uart1: serial@11003000 { 283 compatible = "mediatek,mt6795-uart", 284 "mediatek,mt6577-uart"; 285 reg = <0 0x11003000 0 0x400>; 286 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 287 clocks = <&clk26m>; 288 status = "disabled"; 289 }; 290 291 uart2: serial@11004000 { 292 compatible = "mediatek,mt6795-uart", 293 "mediatek,mt6577-uart"; 294 reg = <0 0x11004000 0 0x400>; 295 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 296 clocks = <&clk26m>; 297 status = "disabled"; 298 }; 299 300 uart3: serial@11005000 { 301 compatible = "mediatek,mt6795-uart", 302 "mediatek,mt6577-uart"; 303 reg = <0 0x11005000 0 0x400>; 304 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>; 305 clocks = <&clk26m>; 306 status = "disabled"; 307 }; 308 }; 309}; 310