1/* 2 * Copyright (c) 2015 MediaTek Inc. 3 * Author: Mars.C <mars.cheng@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14#include <dt-bindings/interrupt-controller/irq.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16 17/ { 18 compatible = "mediatek,mt6795"; 19 interrupt-parent = <&sysirq>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 psci { 24 compatible = "arm,psci-0.2"; 25 method = "smc"; 26 }; 27 28 cpus { 29 #address-cells = <1>; 30 #size-cells = <0>; 31 32 cpu0: cpu@0 { 33 device_type = "cpu"; 34 compatible = "arm,cortex-a53"; 35 enable-method = "psci"; 36 reg = <0x000>; 37 next-level-cache = <&l2_0>; 38 }; 39 40 cpu1: cpu@1 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a53"; 43 enable-method = "psci"; 44 reg = <0x001>; 45 next-level-cache = <&l2_0>; 46 }; 47 48 cpu2: cpu@2 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a53"; 51 enable-method = "psci"; 52 reg = <0x002>; 53 next-level-cache = <&l2_0>; 54 }; 55 56 cpu3: cpu@3 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a53"; 59 enable-method = "psci"; 60 reg = <0x003>; 61 next-level-cache = <&l2_0>; 62 }; 63 64 cpu4: cpu@100 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a53"; 67 enable-method = "psci"; 68 reg = <0x100>; 69 next-level-cache = <&l2_1>; 70 }; 71 72 cpu5: cpu@101 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a53"; 75 enable-method = "psci"; 76 reg = <0x101>; 77 next-level-cache = <&l2_1>; 78 }; 79 80 cpu6: cpu@102 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a53"; 83 enable-method = "psci"; 84 reg = <0x102>; 85 next-level-cache = <&l2_1>; 86 }; 87 88 cpu7: cpu@103 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a53"; 91 enable-method = "psci"; 92 reg = <0x103>; 93 next-level-cache = <&l2_1>; 94 }; 95 96 cpu-map { 97 cluster0 { 98 core0 { 99 cpu = <&cpu0>; 100 }; 101 102 core1 { 103 cpu = <&cpu1>; 104 }; 105 106 core2 { 107 cpu = <&cpu2>; 108 }; 109 110 core3 { 111 cpu = <&cpu3>; 112 }; 113 }; 114 115 cluster1 { 116 core0 { 117 cpu = <&cpu4>; 118 }; 119 120 core1 { 121 cpu = <&cpu5>; 122 }; 123 124 core2 { 125 cpu = <&cpu6>; 126 }; 127 128 core3 { 129 cpu = <&cpu7>; 130 }; 131 }; 132 }; 133 134 l2_0: l2-cache0 { 135 compatible = "cache"; 136 cache-level = <2>; 137 }; 138 139 l2_1: l2-cache1 { 140 compatible = "cache"; 141 cache-level = <2>; 142 }; 143 }; 144 145 system_clk: dummy13m { 146 compatible = "fixed-clock"; 147 clock-frequency = <13000000>; 148 #clock-cells = <0>; 149 }; 150 151 rtc_clk: dummy32k { 152 compatible = "fixed-clock"; 153 clock-frequency = <32000>; 154 #clock-cells = <0>; 155 }; 156 157 uart_clk: dummy26m { 158 compatible = "fixed-clock"; 159 clock-frequency = <26000000>; 160 #clock-cells = <0>; 161 }; 162 163 timer { 164 compatible = "arm,armv8-timer"; 165 interrupt-parent = <&gic>; 166 interrupts = <GIC_PPI 13 167 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 168 <GIC_PPI 14 169 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 170 <GIC_PPI 11 171 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 172 <GIC_PPI 10 173 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 174 }; 175 176 soc { 177 #address-cells = <2>; 178 #size-cells = <2>; 179 compatible = "simple-bus"; 180 ranges; 181 182 sysirq: intpol-controller@10200620 { 183 compatible = "mediatek,mt6795-sysirq", 184 "mediatek,mt6577-sysirq"; 185 interrupt-controller; 186 #interrupt-cells = <3>; 187 interrupt-parent = <&gic>; 188 reg = <0 0x10200620 0 0x20>; 189 }; 190 191 gic: interrupt-controller@10221000 { 192 compatible = "arm,gic-400"; 193 #interrupt-cells = <3>; 194 interrupt-parent = <&gic>; 195 interrupt-controller; 196 reg = <0 0x10221000 0 0x1000>, 197 <0 0x10222000 0 0x2000>, 198 <0 0x10224000 0 0x2000>, 199 <0 0x10226000 0 0x2000>; 200 }; 201 202 uart0: serial@11002000 { 203 compatible = "mediatek,mt6795-uart", 204 "mediatek,mt6577-uart"; 205 reg = <0 0x11002000 0 0x400>; 206 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 207 clocks = <&uart_clk>; 208 status = "disabled"; 209 }; 210 211 uart1: serial@11003000 { 212 compatible = "mediatek,mt6795-uart", 213 "mediatek,mt6577-uart"; 214 reg = <0 0x11003000 0 0x400>; 215 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 216 clocks = <&uart_clk>; 217 status = "disabled"; 218 }; 219 220 uart2: serial@11004000 { 221 compatible = "mediatek,mt6795-uart", 222 "mediatek,mt6577-uart"; 223 reg = <0 0x11004000 0 0x400>; 224 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 225 clocks = <&uart_clk>; 226 status = "disabled"; 227 }; 228 229 uart3: serial@11005000 { 230 compatible = "mediatek,mt6795-uart", 231 "mediatek,mt6577-uart"; 232 reg = <0 0x11005000 0 0x400>; 233 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>; 234 clocks = <&uart_clk>; 235 status = "disabled"; 236 }; 237 }; 238}; 239