1/*
2 * Copyright (c) 2015 MediaTek Inc.
3 * Author: Mars.C <mars.cheng@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11 * GNU General Public License for more details.
12 */
13
14#include <dt-bindings/interrupt-controller/irq.h>
15#include <dt-bindings/interrupt-controller/arm-gic.h>
16
17/ {
18	compatible = "mediatek,mt6795";
19	interrupt-parent = <&sysirq>;
20	#address-cells = <2>;
21	#size-cells = <2>;
22
23	psci {
24		compatible = "arm,psci-0.2";
25		method = "smc";
26	};
27
28	cpus {
29		#address-cells = <1>;
30		#size-cells = <0>;
31
32		cpu0: cpu@0 {
33			device_type = "cpu";
34			compatible = "arm,cortex-a53";
35			enable-method = "psci";
36			reg = <0x000>;
37			next-level-cache = <&l2_0>;
38		};
39
40		cpu1: cpu@1 {
41			device_type = "cpu";
42			compatible = "arm,cortex-a53";
43			enable-method = "psci";
44			reg = <0x001>;
45			next-level-cache = <&l2_0>;
46		};
47
48		cpu2: cpu@2 {
49			device_type = "cpu";
50			compatible = "arm,cortex-a53";
51			enable-method = "psci";
52			reg = <0x002>;
53			next-level-cache = <&l2_0>;
54		};
55
56		cpu3: cpu@3 {
57			device_type = "cpu";
58			compatible = "arm,cortex-a53";
59			enable-method = "psci";
60			reg = <0x003>;
61			next-level-cache = <&l2_0>;
62		};
63
64		cpu4: cpu@100 {
65			device_type = "cpu";
66			compatible = "arm,cortex-a53";
67			enable-method = "psci";
68			reg = <0x100>;
69			next-level-cache = <&l2_1>;
70		};
71
72		cpu5: cpu@101 {
73			device_type = "cpu";
74			compatible = "arm,cortex-a53";
75			enable-method = "psci";
76			reg = <0x101>;
77			next-level-cache = <&l2_1>;
78		};
79
80		cpu6: cpu@102 {
81			device_type = "cpu";
82			compatible = "arm,cortex-a53";
83			enable-method = "psci";
84			reg = <0x102>;
85			next-level-cache = <&l2_1>;
86		};
87
88		cpu7: cpu@103 {
89			device_type = "cpu";
90			compatible = "arm,cortex-a53";
91			enable-method = "psci";
92			reg = <0x103>;
93			next-level-cache = <&l2_1>;
94		};
95
96		cpu-map {
97			cluster0 {
98				core0 {
99					cpu = <&cpu0>;
100				};
101
102				core1 {
103					cpu = <&cpu1>;
104				};
105
106				core2 {
107					cpu = <&cpu2>;
108				};
109
110				core3 {
111					cpu = <&cpu3>;
112				};
113			};
114
115			cluster1 {
116				core0 {
117					cpu = <&cpu4>;
118				};
119
120				core1 {
121					cpu = <&cpu5>;
122				};
123
124				core2 {
125					cpu = <&cpu6>;
126				};
127
128				core3 {
129					cpu = <&cpu7>;
130				};
131			};
132		};
133
134		l2_0: l2-cache0 {
135			compatible = "cache";
136			cache-level = <2>;
137		};
138
139		l2_1: l2-cache1 {
140			compatible = "cache";
141			cache-level = <2>;
142		};
143	};
144
145	clk26m: oscillator-26m {
146		compatible = "fixed-clock";
147		#clock-cells = <0>;
148		clock-frequency = <26000000>;
149		clock-output-names = "clk26m";
150	};
151
152	clk32k: oscillator-32k {
153		compatible = "fixed-clock";
154		#clock-cells = <0>;
155		clock-frequency = <32000>;
156		clock-output-names = "clk32k";
157	};
158
159	system_clk: dummy13m {
160		compatible = "fixed-clock";
161		clock-frequency = <13000000>;
162		#clock-cells = <0>;
163	};
164
165	pmu {
166		compatible = "arm,cortex-a53-pmu";
167		interrupts = <GIC_SPI  8 IRQ_TYPE_LEVEL_LOW>,
168			     <GIC_SPI  9 IRQ_TYPE_LEVEL_LOW>,
169			     <GIC_SPI 10 IRQ_TYPE_LEVEL_LOW>,
170			     <GIC_SPI 11 IRQ_TYPE_LEVEL_LOW>;
171		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
172	};
173
174	timer {
175		compatible = "arm,armv8-timer";
176		interrupt-parent = <&gic>;
177		interrupts = <GIC_PPI 13
178			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
179			     <GIC_PPI 14
180			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
181			     <GIC_PPI 11
182			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
183			     <GIC_PPI 10
184			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
185	};
186
187	soc {
188		#address-cells = <2>;
189		#size-cells = <2>;
190		compatible = "simple-bus";
191		ranges;
192
193		watchdog: watchdog@10007000 {
194			compatible = "mediatek,mt6795-wdt";
195			reg = <0 0x10007000 0 0x100>;
196			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>;
197			#reset-cells = <1>;
198			timeout-sec = <20>;
199		};
200
201		sysirq: intpol-controller@10200620 {
202			compatible = "mediatek,mt6795-sysirq",
203				     "mediatek,mt6577-sysirq";
204			interrupt-controller;
205			#interrupt-cells = <3>;
206			interrupt-parent = <&gic>;
207			reg = <0 0x10200620 0 0x20>;
208		};
209
210		gic: interrupt-controller@10221000 {
211			compatible = "arm,gic-400";
212			#interrupt-cells = <3>;
213			interrupt-parent = <&gic>;
214			interrupt-controller;
215			reg = <0 0x10221000 0 0x1000>,
216			      <0 0x10222000 0 0x2000>,
217			      <0 0x10224000 0 0x2000>,
218			      <0 0x10226000 0 0x2000>;
219		};
220
221		uart0: serial@11002000 {
222			compatible = "mediatek,mt6795-uart",
223				     "mediatek,mt6577-uart";
224			reg = <0 0x11002000 0 0x400>;
225			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
226			clocks = <&clk26m>;
227			status = "disabled";
228		};
229
230		uart1: serial@11003000 {
231			compatible = "mediatek,mt6795-uart",
232				     "mediatek,mt6577-uart";
233			reg = <0 0x11003000 0 0x400>;
234			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
235			clocks = <&clk26m>;
236			status = "disabled";
237		};
238
239		uart2: serial@11004000 {
240			compatible = "mediatek,mt6795-uart",
241				     "mediatek,mt6577-uart";
242			reg = <0 0x11004000 0 0x400>;
243			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
244			clocks = <&clk26m>;
245			status = "disabled";
246		};
247
248		uart3: serial@11005000 {
249			compatible = "mediatek,mt6795-uart",
250				     "mediatek,mt6577-uart";
251			reg = <0 0x11005000 0 0x400>;
252			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
253			clocks = <&clk26m>;
254			status = "disabled";
255		};
256	};
257};
258