1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author: Mars.C <mars.cheng@mediatek.com>
5 */
6
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/clock/mediatek,mt6795-clk.h>
10#include <dt-bindings/pinctrl/mt6795-pinfunc.h>
11#include <dt-bindings/reset/mediatek,mt6795-resets.h>
12
13/ {
14	compatible = "mediatek,mt6795";
15	interrupt-parent = <&sysirq>;
16	#address-cells = <2>;
17	#size-cells = <2>;
18
19	psci {
20		compatible = "arm,psci-0.2";
21		method = "smc";
22	};
23
24	cpus {
25		#address-cells = <1>;
26		#size-cells = <0>;
27
28		cpu0: cpu@0 {
29			device_type = "cpu";
30			compatible = "arm,cortex-a53";
31			enable-method = "psci";
32			reg = <0x000>;
33			cci-control-port = <&cci_control2>;
34			next-level-cache = <&l2_0>;
35		};
36
37		cpu1: cpu@1 {
38			device_type = "cpu";
39			compatible = "arm,cortex-a53";
40			enable-method = "psci";
41			reg = <0x001>;
42			cci-control-port = <&cci_control2>;
43			next-level-cache = <&l2_0>;
44		};
45
46		cpu2: cpu@2 {
47			device_type = "cpu";
48			compatible = "arm,cortex-a53";
49			enable-method = "psci";
50			reg = <0x002>;
51			cci-control-port = <&cci_control2>;
52			next-level-cache = <&l2_0>;
53		};
54
55		cpu3: cpu@3 {
56			device_type = "cpu";
57			compatible = "arm,cortex-a53";
58			enable-method = "psci";
59			reg = <0x003>;
60			cci-control-port = <&cci_control2>;
61			next-level-cache = <&l2_0>;
62		};
63
64		cpu4: cpu@100 {
65			device_type = "cpu";
66			compatible = "arm,cortex-a53";
67			enable-method = "psci";
68			reg = <0x100>;
69			cci-control-port = <&cci_control1>;
70			next-level-cache = <&l2_1>;
71		};
72
73		cpu5: cpu@101 {
74			device_type = "cpu";
75			compatible = "arm,cortex-a53";
76			enable-method = "psci";
77			reg = <0x101>;
78			cci-control-port = <&cci_control1>;
79			next-level-cache = <&l2_1>;
80		};
81
82		cpu6: cpu@102 {
83			device_type = "cpu";
84			compatible = "arm,cortex-a53";
85			enable-method = "psci";
86			reg = <0x102>;
87			cci-control-port = <&cci_control1>;
88			next-level-cache = <&l2_1>;
89		};
90
91		cpu7: cpu@103 {
92			device_type = "cpu";
93			compatible = "arm,cortex-a53";
94			enable-method = "psci";
95			reg = <0x103>;
96			cci-control-port = <&cci_control1>;
97			next-level-cache = <&l2_1>;
98		};
99
100		cpu-map {
101			cluster0 {
102				core0 {
103					cpu = <&cpu0>;
104				};
105
106				core1 {
107					cpu = <&cpu1>;
108				};
109
110				core2 {
111					cpu = <&cpu2>;
112				};
113
114				core3 {
115					cpu = <&cpu3>;
116				};
117			};
118
119			cluster1 {
120				core0 {
121					cpu = <&cpu4>;
122				};
123
124				core1 {
125					cpu = <&cpu5>;
126				};
127
128				core2 {
129					cpu = <&cpu6>;
130				};
131
132				core3 {
133					cpu = <&cpu7>;
134				};
135			};
136		};
137
138		l2_0: l2-cache0 {
139			compatible = "cache";
140			cache-level = <2>;
141		};
142
143		l2_1: l2-cache1 {
144			compatible = "cache";
145			cache-level = <2>;
146		};
147	};
148
149	clk26m: oscillator-26m {
150		compatible = "fixed-clock";
151		#clock-cells = <0>;
152		clock-frequency = <26000000>;
153		clock-output-names = "clk26m";
154	};
155
156	clk32k: oscillator-32k {
157		compatible = "fixed-clock";
158		#clock-cells = <0>;
159		clock-frequency = <32000>;
160		clock-output-names = "clk32k";
161	};
162
163	system_clk: dummy13m {
164		compatible = "fixed-clock";
165		clock-frequency = <13000000>;
166		#clock-cells = <0>;
167	};
168
169	pmu {
170		compatible = "arm,cortex-a53-pmu";
171		interrupts = <GIC_SPI  8 IRQ_TYPE_LEVEL_LOW>,
172			     <GIC_SPI  9 IRQ_TYPE_LEVEL_LOW>,
173			     <GIC_SPI 10 IRQ_TYPE_LEVEL_LOW>,
174			     <GIC_SPI 11 IRQ_TYPE_LEVEL_LOW>;
175		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
176	};
177
178	timer {
179		compatible = "arm,armv8-timer";
180		interrupt-parent = <&gic>;
181		interrupts = <GIC_PPI 13
182			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
183			     <GIC_PPI 14
184			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
185			     <GIC_PPI 11
186			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
187			     <GIC_PPI 10
188			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
189	};
190
191	soc {
192		#address-cells = <2>;
193		#size-cells = <2>;
194		compatible = "simple-bus";
195		ranges;
196
197		topckgen: syscon@10000000 {
198			compatible = "mediatek,mt6795-topckgen", "syscon";
199			reg = <0 0x10000000 0 0x1000>;
200			#clock-cells = <1>;
201		};
202
203		infracfg: syscon@10001000 {
204			compatible = "mediatek,mt6795-infracfg", "syscon";
205			reg = <0 0x10001000 0 0x1000>;
206			#clock-cells = <1>;
207			#reset-cells = <1>;
208		};
209
210		pericfg: syscon@10003000 {
211			compatible = "mediatek,mt6795-pericfg", "syscon";
212			reg = <0 0x10003000 0 0x1000>;
213			#clock-cells = <1>;
214			#reset-cells = <1>;
215		};
216
217		pio: pinctrl@10005000 {
218			compatible = "mediatek,mt6795-pinctrl";
219			reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>;
220			reg-names = "base", "eint";
221			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
222				     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
223			gpio-controller;
224			#gpio-cells = <2>;
225			gpio-ranges = <&pio 0 0 196>;
226			interrupt-controller;
227			#interrupt-cells = <2>;
228		};
229
230		watchdog: watchdog@10007000 {
231			compatible = "mediatek,mt6795-wdt";
232			reg = <0 0x10007000 0 0x100>;
233			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>;
234			#reset-cells = <1>;
235			timeout-sec = <20>;
236		};
237
238		timer: timer@10008000 {
239			compatible = "mediatek,mt6795-timer",
240				     "mediatek,mt6577-timer";
241			reg = <0 0x10008000 0 0x1000>;
242			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
243			clocks = <&system_clk>, <&clk32k>;
244		};
245
246		sysirq: intpol-controller@10200620 {
247			compatible = "mediatek,mt6795-sysirq",
248				     "mediatek,mt6577-sysirq";
249			interrupt-controller;
250			#interrupt-cells = <3>;
251			interrupt-parent = <&gic>;
252			reg = <0 0x10200620 0 0x20>;
253		};
254
255		systimer: timer@10200670 {
256			compatible = "mediatek,mt6795-systimer";
257			reg = <0 0x10200670 0 0x10>;
258			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
259			clocks = <&system_clk>;
260			clock-names = "clk13m";
261		};
262
263		gic: interrupt-controller@10221000 {
264			compatible = "arm,gic-400";
265			#interrupt-cells = <3>;
266			interrupt-parent = <&gic>;
267			interrupt-controller;
268			reg = <0 0x10221000 0 0x1000>,
269			      <0 0x10222000 0 0x2000>,
270			      <0 0x10224000 0 0x2000>,
271			      <0 0x10226000 0 0x2000>;
272			interrupts = <GIC_PPI 9
273				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
274		};
275
276		cci: cci@10390000 {
277			compatible = "arm,cci-400";
278			#address-cells = <1>;
279			#size-cells = <1>;
280			reg = <0 0x10390000 0 0x1000>;
281			ranges = <0 0 0x10390000 0x10000>;
282
283			cci_control0: slave-if@1000 {
284				compatible = "arm,cci-400-ctrl-if";
285				interface-type = "ace-lite";
286				reg = <0x1000 0x1000>;
287			};
288
289			cci_control1: slave-if@4000 {
290				compatible = "arm,cci-400-ctrl-if";
291				interface-type = "ace";
292				reg = <0x4000 0x1000>;
293			};
294
295			cci_control2: slave-if@5000 {
296				compatible = "arm,cci-400-ctrl-if";
297				interface-type = "ace";
298				reg = <0x5000 0x1000>;
299			};
300
301			pmu@9000 {
302				compatible = "arm,cci-400-pmu,r1";
303				reg = <0x9000 0x5000>;
304				interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
305					     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
306					     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
307					     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
308					     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
309			};
310		};
311
312		uart0: serial@11002000 {
313			compatible = "mediatek,mt6795-uart",
314				     "mediatek,mt6577-uart";
315			reg = <0 0x11002000 0 0x400>;
316			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
317			clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
318			clock-names = "baud", "bus";
319			status = "disabled";
320		};
321
322		uart1: serial@11003000 {
323			compatible = "mediatek,mt6795-uart",
324				     "mediatek,mt6577-uart";
325			reg = <0 0x11003000 0 0x400>;
326			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
327			clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
328			clock-names = "baud", "bus";
329			status = "disabled";
330		};
331
332		uart2: serial@11004000 {
333			compatible = "mediatek,mt6795-uart",
334				     "mediatek,mt6577-uart";
335			reg = <0 0x11004000 0 0x400>;
336			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
337			clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
338			clock-names = "baud", "bus";
339			status = "disabled";
340		};
341
342		uart3: serial@11005000 {
343			compatible = "mediatek,mt6795-uart",
344				     "mediatek,mt6577-uart";
345			reg = <0 0x11005000 0 0x400>;
346			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
347			clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
348			clock-names = "baud", "bus";
349			status = "disabled";
350		};
351	};
352};
353