1/* 2 * Copyright (c) 2015 MediaTek Inc. 3 * Author: Mars.C <mars.cheng@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14#include <dt-bindings/interrupt-controller/irq.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16 17/ { 18 compatible = "mediatek,mt6795"; 19 interrupt-parent = <&sysirq>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 psci { 24 compatible = "arm,psci-0.2"; 25 method = "smc"; 26 }; 27 28 cpus { 29 #address-cells = <1>; 30 #size-cells = <0>; 31 32 cpu0: cpu@0 { 33 device_type = "cpu"; 34 compatible = "arm,cortex-a53"; 35 enable-method = "psci"; 36 reg = <0x000>; 37 next-level-cache = <&l2_0>; 38 }; 39 40 cpu1: cpu@1 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a53"; 43 enable-method = "psci"; 44 reg = <0x001>; 45 next-level-cache = <&l2_0>; 46 }; 47 48 cpu2: cpu@2 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a53"; 51 enable-method = "psci"; 52 reg = <0x002>; 53 next-level-cache = <&l2_0>; 54 }; 55 56 cpu3: cpu@3 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a53"; 59 enable-method = "psci"; 60 reg = <0x003>; 61 next-level-cache = <&l2_0>; 62 }; 63 64 cpu4: cpu@100 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a53"; 67 enable-method = "psci"; 68 reg = <0x100>; 69 next-level-cache = <&l2_1>; 70 }; 71 72 cpu5: cpu@101 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a53"; 75 enable-method = "psci"; 76 reg = <0x101>; 77 next-level-cache = <&l2_1>; 78 }; 79 80 cpu6: cpu@102 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a53"; 83 enable-method = "psci"; 84 reg = <0x102>; 85 next-level-cache = <&l2_1>; 86 }; 87 88 cpu7: cpu@103 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a53"; 91 enable-method = "psci"; 92 reg = <0x103>; 93 next-level-cache = <&l2_1>; 94 }; 95 96 cpu-map { 97 cluster0 { 98 core0 { 99 cpu = <&cpu0>; 100 }; 101 102 core1 { 103 cpu = <&cpu1>; 104 }; 105 106 core2 { 107 cpu = <&cpu2>; 108 }; 109 110 core3 { 111 cpu = <&cpu3>; 112 }; 113 }; 114 115 cluster1 { 116 core0 { 117 cpu = <&cpu4>; 118 }; 119 120 core1 { 121 cpu = <&cpu5>; 122 }; 123 124 core2 { 125 cpu = <&cpu6>; 126 }; 127 128 core3 { 129 cpu = <&cpu7>; 130 }; 131 }; 132 }; 133 134 l2_0: l2-cache0 { 135 compatible = "cache"; 136 cache-level = <2>; 137 }; 138 139 l2_1: l2-cache1 { 140 compatible = "cache"; 141 cache-level = <2>; 142 }; 143 }; 144 145 clk26m: oscillator-26m { 146 compatible = "fixed-clock"; 147 #clock-cells = <0>; 148 clock-frequency = <26000000>; 149 clock-output-names = "clk26m"; 150 }; 151 152 clk32k: oscillator-32k { 153 compatible = "fixed-clock"; 154 #clock-cells = <0>; 155 clock-frequency = <32000>; 156 clock-output-names = "clk32k"; 157 }; 158 159 system_clk: dummy13m { 160 compatible = "fixed-clock"; 161 clock-frequency = <13000000>; 162 #clock-cells = <0>; 163 }; 164 165 rtc_clk: dummy32k { 166 compatible = "fixed-clock"; 167 clock-frequency = <32000>; 168 #clock-cells = <0>; 169 }; 170 171 uart_clk: dummy26m { 172 compatible = "fixed-clock"; 173 clock-frequency = <26000000>; 174 #clock-cells = <0>; 175 }; 176 177 pmu { 178 compatible = "arm,cortex-a53-pmu"; 179 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>, 180 <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>, 181 <GIC_SPI 10 IRQ_TYPE_LEVEL_LOW>, 182 <GIC_SPI 11 IRQ_TYPE_LEVEL_LOW>; 183 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 184 }; 185 186 timer { 187 compatible = "arm,armv8-timer"; 188 interrupt-parent = <&gic>; 189 interrupts = <GIC_PPI 13 190 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 191 <GIC_PPI 14 192 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 193 <GIC_PPI 11 194 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 195 <GIC_PPI 10 196 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 197 }; 198 199 soc { 200 #address-cells = <2>; 201 #size-cells = <2>; 202 compatible = "simple-bus"; 203 ranges; 204 205 watchdog: watchdog@10007000 { 206 compatible = "mediatek,mt6795-wdt"; 207 reg = <0 0x10007000 0 0x100>; 208 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>; 209 #reset-cells = <1>; 210 timeout-sec = <20>; 211 }; 212 213 sysirq: intpol-controller@10200620 { 214 compatible = "mediatek,mt6795-sysirq", 215 "mediatek,mt6577-sysirq"; 216 interrupt-controller; 217 #interrupt-cells = <3>; 218 interrupt-parent = <&gic>; 219 reg = <0 0x10200620 0 0x20>; 220 }; 221 222 gic: interrupt-controller@10221000 { 223 compatible = "arm,gic-400"; 224 #interrupt-cells = <3>; 225 interrupt-parent = <&gic>; 226 interrupt-controller; 227 reg = <0 0x10221000 0 0x1000>, 228 <0 0x10222000 0 0x2000>, 229 <0 0x10224000 0 0x2000>, 230 <0 0x10226000 0 0x2000>; 231 }; 232 233 uart0: serial@11002000 { 234 compatible = "mediatek,mt6795-uart", 235 "mediatek,mt6577-uart"; 236 reg = <0 0x11002000 0 0x400>; 237 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 238 clocks = <&uart_clk>; 239 status = "disabled"; 240 }; 241 242 uart1: serial@11003000 { 243 compatible = "mediatek,mt6795-uart", 244 "mediatek,mt6577-uart"; 245 reg = <0 0x11003000 0 0x400>; 246 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 247 clocks = <&uart_clk>; 248 status = "disabled"; 249 }; 250 251 uart2: serial@11004000 { 252 compatible = "mediatek,mt6795-uart", 253 "mediatek,mt6577-uart"; 254 reg = <0 0x11004000 0 0x400>; 255 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 256 clocks = <&uart_clk>; 257 status = "disabled"; 258 }; 259 260 uart3: serial@11005000 { 261 compatible = "mediatek,mt6795-uart", 262 "mediatek,mt6577-uart"; 263 reg = <0 0x11005000 0 0x400>; 264 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>; 265 clocks = <&uart_clk>; 266 status = "disabled"; 267 }; 268 }; 269}; 270