1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2015 MediaTek Inc. 4 * Author: Mars.C <mars.cheng@mediatek.com> 5 */ 6 7#include <dt-bindings/interrupt-controller/irq.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/mediatek,mt6795-clk.h> 10#include <dt-bindings/gce/mediatek,mt6795-gce.h> 11#include <dt-bindings/memory/mt6795-larb-port.h> 12#include <dt-bindings/pinctrl/mt6795-pinfunc.h> 13#include <dt-bindings/power/mt6795-power.h> 14#include <dt-bindings/reset/mediatek,mt6795-resets.h> 15 16/ { 17 compatible = "mediatek,mt6795"; 18 interrupt-parent = <&sysirq>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 psci { 23 compatible = "arm,psci-0.2"; 24 method = "smc"; 25 }; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 cpu0: cpu@0 { 32 device_type = "cpu"; 33 compatible = "arm,cortex-a53"; 34 enable-method = "psci"; 35 reg = <0x000>; 36 cci-control-port = <&cci_control2>; 37 next-level-cache = <&l2_0>; 38 }; 39 40 cpu1: cpu@1 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a53"; 43 enable-method = "psci"; 44 reg = <0x001>; 45 cci-control-port = <&cci_control2>; 46 i-cache-size = <32768>; 47 i-cache-line-size = <64>; 48 i-cache-sets = <256>; 49 d-cache-size = <32768>; 50 d-cache-line-size = <64>; 51 d-cache-sets = <128>; 52 next-level-cache = <&l2_0>; 53 }; 54 55 cpu2: cpu@2 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a53"; 58 enable-method = "psci"; 59 reg = <0x002>; 60 cci-control-port = <&cci_control2>; 61 i-cache-size = <32768>; 62 i-cache-line-size = <64>; 63 i-cache-sets = <256>; 64 d-cache-size = <32768>; 65 d-cache-line-size = <64>; 66 d-cache-sets = <128>; 67 next-level-cache = <&l2_0>; 68 }; 69 70 cpu3: cpu@3 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a53"; 73 enable-method = "psci"; 74 reg = <0x003>; 75 cci-control-port = <&cci_control2>; 76 i-cache-size = <32768>; 77 i-cache-line-size = <64>; 78 i-cache-sets = <256>; 79 d-cache-size = <32768>; 80 d-cache-line-size = <64>; 81 d-cache-sets = <128>; 82 next-level-cache = <&l2_0>; 83 }; 84 85 cpu4: cpu@100 { 86 device_type = "cpu"; 87 compatible = "arm,cortex-a53"; 88 enable-method = "psci"; 89 reg = <0x100>; 90 cci-control-port = <&cci_control1>; 91 i-cache-size = <32768>; 92 i-cache-line-size = <64>; 93 i-cache-sets = <256>; 94 d-cache-size = <32768>; 95 d-cache-line-size = <64>; 96 d-cache-sets = <128>; 97 next-level-cache = <&l2_1>; 98 }; 99 100 cpu5: cpu@101 { 101 device_type = "cpu"; 102 compatible = "arm,cortex-a53"; 103 enable-method = "psci"; 104 reg = <0x101>; 105 cci-control-port = <&cci_control1>; 106 i-cache-size = <32768>; 107 i-cache-line-size = <64>; 108 i-cache-sets = <256>; 109 d-cache-size = <32768>; 110 d-cache-line-size = <64>; 111 d-cache-sets = <128>; 112 next-level-cache = <&l2_1>; 113 }; 114 115 cpu6: cpu@102 { 116 device_type = "cpu"; 117 compatible = "arm,cortex-a53"; 118 enable-method = "psci"; 119 reg = <0x102>; 120 cci-control-port = <&cci_control1>; 121 i-cache-size = <32768>; 122 i-cache-line-size = <64>; 123 i-cache-sets = <256>; 124 d-cache-size = <32768>; 125 d-cache-line-size = <64>; 126 d-cache-sets = <128>; 127 next-level-cache = <&l2_1>; 128 }; 129 130 cpu7: cpu@103 { 131 device_type = "cpu"; 132 compatible = "arm,cortex-a53"; 133 enable-method = "psci"; 134 reg = <0x103>; 135 cci-control-port = <&cci_control1>; 136 i-cache-size = <32768>; 137 i-cache-line-size = <64>; 138 i-cache-sets = <256>; 139 d-cache-size = <32768>; 140 d-cache-line-size = <64>; 141 d-cache-sets = <128>; 142 next-level-cache = <&l2_1>; 143 }; 144 145 cpu-map { 146 cluster0 { 147 core0 { 148 cpu = <&cpu0>; 149 }; 150 151 core1 { 152 cpu = <&cpu1>; 153 }; 154 155 core2 { 156 cpu = <&cpu2>; 157 }; 158 159 core3 { 160 cpu = <&cpu3>; 161 }; 162 }; 163 164 cluster1 { 165 core0 { 166 cpu = <&cpu4>; 167 }; 168 169 core1 { 170 cpu = <&cpu5>; 171 }; 172 173 core2 { 174 cpu = <&cpu6>; 175 }; 176 177 core3 { 178 cpu = <&cpu7>; 179 }; 180 }; 181 }; 182 183 l2_0: l2-cache0 { 184 compatible = "cache"; 185 cache-level = <2>; 186 cache-size = <1048576>; 187 cache-line-size = <64>; 188 cache-sets = <1024>; 189 cache-unified; 190 }; 191 192 l2_1: l2-cache1 { 193 compatible = "cache"; 194 cache-level = <2>; 195 cache-size = <1048576>; 196 cache-line-size = <64>; 197 cache-sets = <1024>; 198 cache-unified; 199 }; 200 }; 201 202 clk26m: oscillator-26m { 203 compatible = "fixed-clock"; 204 #clock-cells = <0>; 205 clock-frequency = <26000000>; 206 clock-output-names = "clk26m"; 207 }; 208 209 clk32k: oscillator-32k { 210 compatible = "fixed-clock"; 211 #clock-cells = <0>; 212 clock-frequency = <32000>; 213 clock-output-names = "clk32k"; 214 }; 215 216 system_clk: dummy13m { 217 compatible = "fixed-clock"; 218 clock-frequency = <13000000>; 219 #clock-cells = <0>; 220 }; 221 222 pmu { 223 compatible = "arm,cortex-a53-pmu"; 224 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>, 225 <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>, 226 <GIC_SPI 10 IRQ_TYPE_LEVEL_LOW>, 227 <GIC_SPI 11 IRQ_TYPE_LEVEL_LOW>; 228 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 229 }; 230 231 timer { 232 compatible = "arm,armv8-timer"; 233 interrupt-parent = <&gic>; 234 interrupts = <GIC_PPI 13 235 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 236 <GIC_PPI 14 237 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 238 <GIC_PPI 11 239 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 240 <GIC_PPI 10 241 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 242 }; 243 244 soc { 245 #address-cells = <2>; 246 #size-cells = <2>; 247 compatible = "simple-bus"; 248 ranges; 249 250 topckgen: syscon@10000000 { 251 compatible = "mediatek,mt6795-topckgen", "syscon"; 252 reg = <0 0x10000000 0 0x1000>; 253 #clock-cells = <1>; 254 }; 255 256 infracfg: syscon@10001000 { 257 compatible = "mediatek,mt6795-infracfg", "syscon"; 258 reg = <0 0x10001000 0 0x1000>; 259 #clock-cells = <1>; 260 #reset-cells = <1>; 261 }; 262 263 pericfg: syscon@10003000 { 264 compatible = "mediatek,mt6795-pericfg", "syscon"; 265 reg = <0 0x10003000 0 0x1000>; 266 #clock-cells = <1>; 267 #reset-cells = <1>; 268 }; 269 270 scpsys: syscon@10006000 { 271 compatible = "syscon", "simple-mfd"; 272 reg = <0 0x10006000 0 0x1000>; 273 #power-domain-cells = <1>; 274 275 /* System Power Manager */ 276 spm: power-controller { 277 compatible = "mediatek,mt6795-power-controller"; 278 #address-cells = <1>; 279 #size-cells = <0>; 280 #power-domain-cells = <1>; 281 282 /* power domains of the SoC */ 283 power-domain@MT6795_POWER_DOMAIN_VDEC { 284 reg = <MT6795_POWER_DOMAIN_VDEC>; 285 clocks = <&topckgen CLK_TOP_MM_SEL>; 286 clock-names = "mm"; 287 #power-domain-cells = <0>; 288 }; 289 power-domain@MT6795_POWER_DOMAIN_VENC { 290 reg = <MT6795_POWER_DOMAIN_VENC>; 291 clocks = <&topckgen CLK_TOP_MM_SEL>, 292 <&topckgen CLK_TOP_VENC_SEL>; 293 clock-names = "mm", "venc"; 294 #power-domain-cells = <0>; 295 }; 296 power-domain@MT6795_POWER_DOMAIN_ISP { 297 reg = <MT6795_POWER_DOMAIN_ISP>; 298 clocks = <&topckgen CLK_TOP_MM_SEL>; 299 clock-names = "mm"; 300 #power-domain-cells = <0>; 301 }; 302 303 power-domain@MT6795_POWER_DOMAIN_MM { 304 reg = <MT6795_POWER_DOMAIN_MM>; 305 clocks = <&topckgen CLK_TOP_MM_SEL>; 306 clock-names = "mm"; 307 #power-domain-cells = <0>; 308 mediatek,infracfg = <&infracfg>; 309 }; 310 311 power-domain@MT6795_POWER_DOMAIN_MJC { 312 reg = <MT6795_POWER_DOMAIN_MJC>; 313 clocks = <&topckgen CLK_TOP_MM_SEL>, 314 <&topckgen CLK_TOP_MJC_SEL>; 315 clock-names = "mm", "mjc"; 316 #power-domain-cells = <0>; 317 }; 318 319 power-domain@MT6795_POWER_DOMAIN_AUDIO { 320 reg = <MT6795_POWER_DOMAIN_AUDIO>; 321 #power-domain-cells = <0>; 322 }; 323 324 mfg_async: power-domain@MT6795_POWER_DOMAIN_MFG_ASYNC { 325 reg = <MT6795_POWER_DOMAIN_MFG_ASYNC>; 326 clocks = <&clk26m>; 327 clock-names = "mfg"; 328 #address-cells = <1>; 329 #size-cells = <0>; 330 #power-domain-cells = <1>; 331 332 power-domain@MT6795_POWER_DOMAIN_MFG_2D { 333 reg = <MT6795_POWER_DOMAIN_MFG_2D>; 334 #address-cells = <1>; 335 #size-cells = <0>; 336 #power-domain-cells = <1>; 337 338 power-domain@MT6795_POWER_DOMAIN_MFG { 339 reg = <MT6795_POWER_DOMAIN_MFG>; 340 #power-domain-cells = <0>; 341 mediatek,infracfg = <&infracfg>; 342 }; 343 }; 344 }; 345 }; 346 }; 347 348 pio: pinctrl@10005000 { 349 compatible = "mediatek,mt6795-pinctrl"; 350 reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>; 351 reg-names = "base", "eint"; 352 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 353 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 354 gpio-controller; 355 #gpio-cells = <2>; 356 gpio-ranges = <&pio 0 0 196>; 357 interrupt-controller; 358 #interrupt-cells = <2>; 359 }; 360 361 watchdog: watchdog@10007000 { 362 compatible = "mediatek,mt6795-wdt"; 363 reg = <0 0x10007000 0 0x100>; 364 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>; 365 #reset-cells = <1>; 366 timeout-sec = <20>; 367 }; 368 369 timer: timer@10008000 { 370 compatible = "mediatek,mt6795-timer", 371 "mediatek,mt6577-timer"; 372 reg = <0 0x10008000 0 0x1000>; 373 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>; 374 clocks = <&system_clk>, <&clk32k>; 375 }; 376 377 sysirq: intpol-controller@10200620 { 378 compatible = "mediatek,mt6795-sysirq", 379 "mediatek,mt6577-sysirq"; 380 interrupt-controller; 381 #interrupt-cells = <3>; 382 interrupt-parent = <&gic>; 383 reg = <0 0x10200620 0 0x20>; 384 }; 385 386 systimer: timer@10200670 { 387 compatible = "mediatek,mt6795-systimer"; 388 reg = <0 0x10200670 0 0x10>; 389 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 390 clocks = <&system_clk>; 391 clock-names = "clk13m"; 392 }; 393 394 iommu: iommu@10205000 { 395 compatible = "mediatek,mt6795-m4u"; 396 reg = <0 0x10205000 0 0x1000>; 397 clocks = <&infracfg CLK_INFRA_M4U>; 398 clock-names = "bclk"; 399 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_LOW>; 400 mediatek,larbs = <&larb0 &larb1 &larb2 &larb3>; 401 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 402 #iommu-cells = <1>; 403 }; 404 405 apmixedsys: syscon@10209000 { 406 compatible = "mediatek,mt6795-apmixedsys", "syscon"; 407 reg = <0 0x10209000 0 0x1000>; 408 #clock-cells = <1>; 409 }; 410 411 fhctl: clock-controller@10209f00 { 412 compatible = "mediatek,mt6795-fhctl"; 413 reg = <0 0x10209f00 0 0x100>; 414 status = "disabled"; 415 }; 416 417 gce: mailbox@10212000 { 418 compatible = "mediatek,mt6795-gce", "mediatek,mt8173-gce"; 419 reg = <0 0x10212000 0 0x1000>; 420 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>; 421 clocks = <&infracfg CLK_INFRA_GCE>; 422 clock-names = "gce"; 423 #mbox-cells = <2>; 424 }; 425 426 gic: interrupt-controller@10221000 { 427 compatible = "arm,gic-400"; 428 #interrupt-cells = <3>; 429 interrupt-parent = <&gic>; 430 interrupt-controller; 431 reg = <0 0x10221000 0 0x1000>, 432 <0 0x10222000 0 0x2000>, 433 <0 0x10224000 0 0x2000>, 434 <0 0x10226000 0 0x2000>; 435 interrupts = <GIC_PPI 9 436 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 437 }; 438 439 cci: cci@10390000 { 440 compatible = "arm,cci-400"; 441 #address-cells = <1>; 442 #size-cells = <1>; 443 reg = <0 0x10390000 0 0x1000>; 444 ranges = <0 0 0x10390000 0x10000>; 445 446 cci_control0: slave-if@1000 { 447 compatible = "arm,cci-400-ctrl-if"; 448 interface-type = "ace-lite"; 449 reg = <0x1000 0x1000>; 450 }; 451 452 cci_control1: slave-if@4000 { 453 compatible = "arm,cci-400-ctrl-if"; 454 interface-type = "ace"; 455 reg = <0x4000 0x1000>; 456 }; 457 458 cci_control2: slave-if@5000 { 459 compatible = "arm,cci-400-ctrl-if"; 460 interface-type = "ace"; 461 reg = <0x5000 0x1000>; 462 }; 463 464 pmu@9000 { 465 compatible = "arm,cci-400-pmu,r1"; 466 reg = <0x9000 0x5000>; 467 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 471 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 472 }; 473 }; 474 475 uart0: serial@11002000 { 476 compatible = "mediatek,mt6795-uart", 477 "mediatek,mt6577-uart"; 478 reg = <0 0x11002000 0 0x400>; 479 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 480 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 481 clock-names = "baud", "bus"; 482 dmas = <&apdma 0>, <&apdma 1>; 483 dma-names = "tx", "rx"; 484 status = "disabled"; 485 }; 486 487 uart1: serial@11003000 { 488 compatible = "mediatek,mt6795-uart", 489 "mediatek,mt6577-uart"; 490 reg = <0 0x11003000 0 0x400>; 491 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 492 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 493 clock-names = "baud", "bus"; 494 dmas = <&apdma 2>, <&apdma 3>; 495 dma-names = "tx", "rx"; 496 status = "disabled"; 497 }; 498 499 apdma: dma-controller@11000380 { 500 compatible = "mediatek,mt6795-uart-dma", 501 "mediatek,mt6577-uart-dma"; 502 reg = <0 0x11000380 0 0x60>, 503 <0 0x11000400 0 0x60>, 504 <0 0x11000480 0 0x60>, 505 <0 0x11000500 0 0x60>, 506 <0 0x11000580 0 0x60>, 507 <0 0x11000600 0 0x60>, 508 <0 0x11000680 0 0x60>, 509 <0 0x11000700 0 0x60>; 510 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>, 511 <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, 512 <GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>, 513 <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>, 514 <GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>, 515 <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>, 516 <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>, 517 <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 518 dma-requests = <8>; 519 clocks = <&pericfg CLK_PERI_AP_DMA>; 520 clock-names = "apdma"; 521 mediatek,dma-33bits; 522 #dma-cells = <1>; 523 }; 524 525 uart2: serial@11004000 { 526 compatible = "mediatek,mt6795-uart", 527 "mediatek,mt6577-uart"; 528 reg = <0 0x11004000 0 0x400>; 529 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 530 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 531 clock-names = "baud", "bus"; 532 dmas = <&apdma 4>, <&apdma 5>; 533 dma-names = "tx", "rx"; 534 status = "disabled"; 535 }; 536 537 uart3: serial@11005000 { 538 compatible = "mediatek,mt6795-uart", 539 "mediatek,mt6577-uart"; 540 reg = <0 0x11005000 0 0x400>; 541 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>; 542 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 543 clock-names = "baud", "bus"; 544 dmas = <&apdma 6>, <&apdma 7>; 545 dma-names = "tx", "rx"; 546 status = "disabled"; 547 }; 548 549 pwm2: pwm@11006000 { 550 compatible = "mediatek,mt6795-pwm"; 551 reg = <0 0x11006000 0 0x1000>; 552 #pwm-cells = <2>; 553 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 554 clocks = <&topckgen CLK_TOP_PWM_SEL>, 555 <&pericfg CLK_PERI_PWM>, 556 <&pericfg CLK_PERI_PWM1>, 557 <&pericfg CLK_PERI_PWM2>, 558 <&pericfg CLK_PERI_PWM3>, 559 <&pericfg CLK_PERI_PWM4>, 560 <&pericfg CLK_PERI_PWM5>, 561 <&pericfg CLK_PERI_PWM6>, 562 <&pericfg CLK_PERI_PWM7>; 563 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", 564 "pwm4", "pwm5", "pwm6", "pwm7"; 565 status = "disabled"; 566 }; 567 568 i2c0: i2c@11007000 { 569 compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c"; 570 reg = <0 0x11007000 0 0x70>, <0 0x11000100 0 0x80>; 571 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 572 clock-div = <16>; 573 clocks = <&pericfg CLK_PERI_I2C0>, <&pericfg CLK_PERI_AP_DMA>; 574 clock-names = "main", "dma"; 575 #address-cells = <1>; 576 #size-cells = <0>; 577 status = "disabled"; 578 }; 579 580 i2c1: i2c@11008000 { 581 compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c"; 582 reg = <0 0x11008000 0 0x70>, <0 0x11000180 0 0x80>; 583 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 584 clock-div = <16>; 585 clocks = <&pericfg CLK_PERI_I2C1>, <&pericfg CLK_PERI_AP_DMA>; 586 clock-names = "main", "dma"; 587 #address-cells = <1>; 588 #size-cells = <0>; 589 status = "disabled"; 590 }; 591 592 i2c2: i2c@11009000 { 593 compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c"; 594 reg = <0 0x11009000 0 0x70>, <0 0x11000200 0 0x80>; 595 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 596 clock-div = <16>; 597 clocks = <&pericfg CLK_PERI_I2C2>, <&pericfg CLK_PERI_AP_DMA>; 598 clock-names = "main", "dma"; 599 #address-cells = <1>; 600 #size-cells = <0>; 601 status = "disabled"; 602 }; 603 604 i2c3: i2c@11010000 { 605 compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c"; 606 reg = <0 0x11010000 0 0x70>, <0 0x11000280 0 0x80>; 607 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; 608 clock-div = <16>; 609 clocks = <&pericfg CLK_PERI_I2C3>, <&pericfg CLK_PERI_AP_DMA>; 610 clock-names = "main", "dma"; 611 #address-cells = <1>; 612 #size-cells = <0>; 613 status = "disabled"; 614 }; 615 616 i2c4: i2c@11011000 { 617 compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c"; 618 reg = <0 0x11011000 0 0x70>, <0 0x11000300 0 0x80>; 619 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>; 620 clock-div = <16>; 621 clocks = <&pericfg CLK_PERI_I2C4>, <&pericfg CLK_PERI_AP_DMA>; 622 clock-names = "main", "dma"; 623 #address-cells = <1>; 624 #size-cells = <0>; 625 status = "disabled"; 626 }; 627 628 mmc0: mmc@11230000 { 629 compatible = "mediatek,mt6795-mmc"; 630 reg = <0 0x11230000 0 0x1000>; 631 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 632 clocks = <&pericfg CLK_PERI_MSDC30_0>, 633 <&topckgen CLK_TOP_MSDC50_0_H_SEL>, 634 <&topckgen CLK_TOP_MSDC50_0_SEL>; 635 clock-names = "source", "hclk", "source_cg"; 636 status = "disabled"; 637 }; 638 639 mmc1: mmc@11240000 { 640 compatible = "mediatek,mt6795-mmc"; 641 reg = <0 0x11240000 0 0x1000>; 642 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 643 clocks = <&pericfg CLK_PERI_MSDC30_1>, 644 <&topckgen CLK_TOP_AXI_SEL>; 645 clock-names = "source", "hclk"; 646 status = "disabled"; 647 }; 648 649 mmc2: mmc@11250000 { 650 compatible = "mediatek,mt6795-mmc"; 651 reg = <0 0x11250000 0 0x1000>; 652 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 653 clocks = <&pericfg CLK_PERI_MSDC30_2>, 654 <&topckgen CLK_TOP_AXI_SEL>; 655 clock-names = "source", "hclk"; 656 status = "disabled"; 657 }; 658 659 mmc3: mmc@11260000 { 660 compatible = "mediatek,mt6795-mmc"; 661 reg = <0 0x11260000 0 0x1000>; 662 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 663 clocks = <&pericfg CLK_PERI_MSDC30_3>, 664 <&topckgen CLK_TOP_AXI_SEL>; 665 clock-names = "source", "hclk"; 666 status = "disabled"; 667 }; 668 669 mmsys: syscon@14000000 { 670 compatible = "mediatek,mt6795-mmsys", "syscon"; 671 reg = <0 0x14000000 0 0x1000>; 672 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 673 assigned-clocks = <&topckgen CLK_TOP_MM_SEL>; 674 assigned-clock-rates = <400000000>; 675 #clock-cells = <1>; 676 #reset-cells = <1>; 677 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, 678 <&gce 1 CMDQ_THR_PRIO_HIGHEST>; 679 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; 680 }; 681 682 larb0: larb@14021000 { 683 compatible = "mediatek,mt6795-smi-larb"; 684 reg = <0 0x14021000 0 0x1000>; 685 clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_LARB0>; 686 clock-names = "apb", "smi"; 687 mediatek,smi = <&smi_common>; 688 mediatek,larb-id = <0>; 689 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 690 }; 691 692 smi_common: smi@14022000 { 693 compatible = "mediatek,mt6795-smi-common"; 694 reg = <0 0x14022000 0 0x1000>; 695 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 696 clocks = <&infracfg CLK_INFRA_SMI>, <&mmsys CLK_MM_SMI_COMMON>; 697 clock-names = "apb", "smi"; 698 }; 699 700 larb2: larb@15001000 { 701 compatible = "mediatek,mt6795-smi-larb"; 702 reg = <0 0x15001000 0 0x1000>; 703 clocks = <&mmsys CLK_MM_SMI_COMMON>, <&infracfg CLK_INFRA_SMI>; 704 clock-names = "apb", "smi"; 705 mediatek,smi = <&smi_common>; 706 mediatek,larb-id = <2>; 707 power-domains = <&spm MT6795_POWER_DOMAIN_ISP>; 708 }; 709 710 vdecsys: clock-controller@16000000 { 711 compatible = "mediatek,mt6795-vdecsys"; 712 reg = <0 0x16000000 0 0x1000>; 713 #clock-cells = <1>; 714 }; 715 716 larb1: larb@16010000 { 717 compatible = "mediatek,mt6795-smi-larb"; 718 reg = <0 0x16010000 0 0x1000>; 719 mediatek,smi = <&smi_common>; 720 mediatek,larb-id = <1>; 721 clocks = <&vdecsys CLK_VDEC_CKEN>, <&vdecsys CLK_VDEC_LARB_CKEN>; 722 clock-names = "apb", "smi"; 723 power-domains = <&spm MT6795_POWER_DOMAIN_VDEC>; 724 }; 725 726 vencsys: clock-controller@18000000 { 727 compatible = "mediatek,mt6795-vencsys"; 728 reg = <0 0x18000000 0 0x1000>; 729 #clock-cells = <1>; 730 }; 731 732 larb3: larb@18001000 { 733 compatible = "mediatek,mt6795-smi-larb"; 734 reg = <0 0x18001000 0 0x1000>; 735 clocks = <&vencsys CLK_VENC_VENC>, <&vencsys CLK_VENC_LARB>; 736 clock-names = "apb", "smi"; 737 mediatek,smi = <&smi_common>; 738 mediatek,larb-id = <3>; 739 power-domains = <&spm MT6795_POWER_DOMAIN_VENC>; 740 }; 741 }; 742}; 743