| 67327f12 | 06-Dec-2022 |
Asahi Lina <lina@asahilina.net> |
arm64: dts: apple: t6002: Fix GPU power domains
On t6002 (M1 Ultra), each die contains a self-contained GPU block.
However, only the coprocessor and global management circuitry of the
first die are
arm64: dts: apple: t6002: Fix GPU power domains
On t6002 (M1 Ultra), each die contains a self-contained GPU block.
However, only the coprocessor and global management circuitry of the
first die are used. This is what is represented by the "gpu" PS (the
one in die1 is disabled). Nonetheless, this shared component drives the
processing blocks in both dies, and therefore depends on the AFR fabric
being powered up on both dies.
Add an explicit dependency from the GPU block on die0 to AFR on die1,
next to the existing die0 AFR dependency.
Fixes: fa86294eb355 ("arm64: dts: apple: Add initial t6000/t6001/t6002 DTs")
Signed-off-by: Asahi Lina <lina@asahilina.net>
Reviewed-by: Janne Grunau <j@jannau.net>
Signed-off-by: Hector Martin <marcan@marcan.st>
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| 2aa48e29 | 06-Dec-2022 |
Asahi Lina <lina@asahilina.net> |
arm64: dts: apple: t600x-pmgr: Fix search & replace typo
It looks like the search-and-replace that happened to add die IDs to
the t600x PMGR tree was a little bit too eager on a comment, and nobody
arm64: dts: apple: t600x-pmgr: Fix search & replace typo
It looks like the search-and-replace that happened to add die IDs to
the t600x PMGR tree was a little bit too eager on a comment, and nobody
noticed! Let's fix that.
Fixes: fa86294eb355 ("arm64: dts: apple: Add initial t6000/t6001/t6002 DTs")
Signed-off-by: Asahi Lina <lina@asahilina.net>
Reviewed-by: Janne Grunau <j@jannau.net>
Signed-off-by: Hector Martin <marcan@marcan.st>
show more ...
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| 9ecb7a4b | 06-Dec-2022 |
Janne Grunau <j@jannau.net> |
arm64: dts: apple: Add t8103 L1/L2 cache properties and nodes
The t8103 CPU nodes are missing the cache hierarchy information. The
cache hierarchy on Arm can not be detected and needs to be describe
arm64: dts: apple: Add t8103 L1/L2 cache properties and nodes
The t8103 CPU nodes are missing the cache hierarchy information. The
cache hierarchy on Arm can not be detected and needs to be described in
DT. The OS scheduler can make use of this information for scheduling
decisions.
The cache size information is based on various articles about the
processors. There's also an L3 system level cache (SLC). It's not
described here because SLCs typically have some MMIO interface which
would need to be described.
Based on Rob Herring's patch adding cache properties and nodes for
t600x.
Link: https://lore.kernel.org/asahi/20221122220619.659174-1-robh@kernel.org/
Signed-off-by: Janne Grunau <j@jannau.net>
Signed-off-by: Hector Martin <marcan@marcan.st>
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| 63bf0b66 | 05-Dec-2022 |
Hector Martin <marcan@marcan.st> |
arm64: dts: apple: Rename dart-sio* to sio-dart*
All the other DARTs are named foo-dart, so let's keep things consistent.
Fixes: 51979fbb7fb8 ("arm64: dts: apple: t600x: Add MCA and its support")
F
arm64: dts: apple: Rename dart-sio* to sio-dart*
All the other DARTs are named foo-dart, so let's keep things consistent.
Fixes: 51979fbb7fb8 ("arm64: dts: apple: t600x: Add MCA and its support")
Fixes: 8a3df85ad87d ("arm64: dts: apple: t8103: Add MCA and its support")
Reviewed-by: Sven Peter <sven@svenpeter.dev>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Signed-off-by: Hector Martin <marcan@marcan.st>
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| 97423509 | 06-Dec-2022 |
Janne Grunau <j@jannau.net> |
arch: arm64: apple: t600x: Use standard "iommu" node name
The PCIe iommu nodes use "dart" as node names. Replace it with the
the standard "iommu" node name as all other iommu nodes.
Fixes: 7b0b0191
arch: arm64: apple: t600x: Use standard "iommu" node name
The PCIe iommu nodes use "dart" as node names. Replace it with the
the standard "iommu" node name as all other iommu nodes.
Fixes: 7b0b0191a2c7 ("arm64: dts: apple: Add initial t6000/t6001/t6002 DTs")
Signed-off-by: Janne Grunau <j@jannau.net>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Signed-off-by: Hector Martin <marcan@marcan.st>
show more ...
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| 56d32c51 | 06-Dec-2022 |
Janne Grunau <j@jannau.net> |
arch: arm64: apple: t8103: Use standard "iommu" node name
The PCIe iommu nodes use "dart" as node names. Replace it with the
the standard "iommu" node name as all other iommu nodes.
Fixes: 3c866bb7
arch: arm64: apple: t8103: Use standard "iommu" node name
The PCIe iommu nodes use "dart" as node names. Replace it with the
the standard "iommu" node name as all other iommu nodes.
Fixes: 3c866bb79577 ("arm64: dts: apple: t8103: Add PCIe DARTs")
Signed-off-by: Janne Grunau <j@jannau.net>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Signed-off-by: Hector Martin <marcan@marcan.st>
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| d32c1530 | 15-Feb-2022 |
Hector Martin <marcan@marcan.st> |
arm64: dts: apple: Add CPU topology & cpufreq nodes for t600x
Add the missing CPU topology/capacity information and the cpufreq nodes,
so we can have CPU frequency scaling and the scheduler has the
arm64: dts: apple: Add CPU topology & cpufreq nodes for t600x
Add the missing CPU topology/capacity information and the cpufreq nodes,
so we can have CPU frequency scaling and the scheduler has the
information it needs to make the correct decisions.
As with t8103, boost states are commented out pending PSCI/etc support
for deep sleep states.
Reviewed-by: Sven Peter <sven@svenpeter.dev>
Signed-off-by: Hector Martin <marcan@marcan.st>
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| 3e895a64 | 02-May-2022 |
Hector Martin <marcan@marcan.st> |
arm64: dts: apple: Add CPU topology & cpufreq nodes for t8103
Add the missing CPU topology/capacity information and the cpufreq nodes,
so we can have CPU frequency scaling and the scheduler has the
arm64: dts: apple: Add CPU topology & cpufreq nodes for t8103
Add the missing CPU topology/capacity information and the cpufreq nodes,
so we can have CPU frequency scaling and the scheduler has the
information it needs to make the correct decisions.
Boost states are commented out, as they are not yet available (that
requires CPU deep sleep support, to be eventually done via PSCI).
The driver supports them fine; the hardware will just refuse to ever
go into them at this time, so don't expose them to users until that's
done.
Acked-by: Marc Zyngier <maz@kernel.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Hector Martin <marcan@marcan.st>
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| 83fb5b55 | 22-Nov-2022 |
Rob Herring <robh@kernel.org> |
arm64: dts: apple: Add t600x L1/L2 cache properties and nodes
The t600x CPU nodes are missing the cache hierarchy information. The
cache hierarchy on Arm can not be detected and needs to be describe
arm64: dts: apple: Add t600x L1/L2 cache properties and nodes
The t600x CPU nodes are missing the cache hierarchy information. The
cache hierarchy on Arm can not be detected and needs to be described in
DT. The OS scheduler can make use of this information for scheduling
decisions.
The cache size information is based on various articles about the
processors. There's also an L3 system level cache (SLC). It's not
described here because SLCs typically have some MMIO interface which
would need to be described.
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Hector Martin <marcan@marcan.st>
show more ...
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| 56fed763 | 18-Sep-2022 |
Martin Povišer <povik+lin@cutebit.org> |
arm64: dts: apple: Add ADMAC resets on t8103/t600x
There's a shared reset for the ADMAC and MCA peripherals. The MCA node
already describes it, and being a shared reset it is important we
describe i
arm64: dts: apple: Add ADMAC resets on t8103/t600x
There's a shared reset for the ADMAC and MCA peripherals. The MCA node
already describes it, and being a shared reset it is important we
describe it on the ADMAC node too.
Signed-off-by: Martin Povišer <povik+lin@cutebit.org>
Signed-off-by: Hector Martin <marcan@marcan.st>
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| 8a3df85a | 16-Sep-2022 |
Martin Povišer <povik+lin@cutebit.org> |
arm64: dts: apple: t8103: Add MCA and its support
Add the MCA I2S transceiver node and its supporting NCO, ADMAC nodes.
Signed-off-by: Martin Povišer <povik+lin@cutebit.org>
Signed-off-by: Janne Gr
arm64: dts: apple: t8103: Add MCA and its support
Add the MCA I2S transceiver node and its supporting NCO, ADMAC nodes.
Signed-off-by: Martin Povišer <povik+lin@cutebit.org>
Signed-off-by: Janne Grunau <j@jannau.net>
Acked-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Hector Martin <marcan@marcan.st>
show more ...
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| 50e320ad | 16-Sep-2022 |
Martin Povišer <povik+lin@cutebit.org> |
arm64: dts: apple: t8103: Add AUDIO_P parent to the SIO_ADMA power domain
The SIO_ADMA is a power domain of the Audio DMA Controller. In addition
to it, the AUDIO_P domain must be on for the control
arm64: dts: apple: t8103: Add AUDIO_P parent to the SIO_ADMA power domain
The SIO_ADMA is a power domain of the Audio DMA Controller. In addition
to it, the AUDIO_P domain must be on for the controller's MMIO registers
to be accessible.
On t600x and t8112, AUDIO_P is a parent of SIO_ADMA. On t8103, it isn't
so, at least as far as Apple's firmware goes. To make our life easier,
add the parent-child relationship on t8103 also.
Signed-off-by: Martin Povišer <povik+lin@cutebit.org>
Signed-off-by: Janne Grunau <j@jannau.net>
Acked-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Hector Martin <marcan@marcan.st>
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| 7b0b0191 | 16-Sep-2022 |
Hector Martin <marcan@marcan.st> |
arm64: dts: apple: Add initial t6000/t6001/t6002 DTs
These SoCs are found in Apple devices with M1 Pro (t6000), M1 Max
(t6001) and M1 Ultra (t6002).
t6000 is a cut-down version of t6001, so the for
arm64: dts: apple: Add initial t6000/t6001/t6002 DTs
These SoCs are found in Apple devices with M1 Pro (t6000), M1 Max
(t6001) and M1 Ultra (t6002).
t6000 is a cut-down version of t6001, so the former just includes the
latter and disables the missing bits (This is currently just one PMGR
node and all of its domains.
t6002 is two connected t6001 dies. The implementation seems to use
t6001 with blocks disabled (mostly on the second die). MMIO addresses on
the second die have a constant offset. The interrupt controller is
multi-die aware. This setup can be represented in the device tree with
two top level "soc" nodes. The MMIO offset is applied via "ranges" and
devices are included with preproceesor macros to make the node labels
unique and to specify the die number for the interrupt definition.
Device nodes are distributed over dtsi files based on whether they are
present on both dies or just on the first die. The only execption is the
NVMe controller which resides on the second die. Its nodes are in a
separate file.
Co-developed-by: Janne Grunau <j@jannau.net>
Signed-off-by: Janne Grunau <j@jannau.net>
Acked-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Hector Martin <marcan@marcan.st>
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