1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/ethtool.h> 19 #include <linux/phy.h> 20 #include <linux/if_vlan.h> 21 #include <linux/in.h> 22 #include <linux/io.h> 23 #include <linux/ip.h> 24 #include <linux/tcp.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/bitfield.h> 29 #include <linux/prefetch.h> 30 #include <linux/ipv6.h> 31 #include <asm/unaligned.h> 32 #include <net/ip6_checksum.h> 33 34 #include "r8169.h" 35 #include "r8169_firmware.h" 36 37 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 38 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 39 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 40 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 41 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 42 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 43 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 44 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 45 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 46 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 47 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 48 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 49 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 50 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 51 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 52 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 53 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" 54 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 55 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 56 #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw" 57 58 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 59 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ 60 #define MC_FILTER_LIMIT 32 61 62 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 63 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 64 65 #define R8169_REGS_SIZE 256 66 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 67 #define NUM_TX_DESC 256 /* Number of Tx descriptor registers */ 68 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ 69 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 70 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 71 72 #define OCP_STD_PHY_BASE 0xa400 73 74 #define RTL_CFG_NO_GBIT 1 75 76 /* write/read MMIO register */ 77 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 78 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 79 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 80 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 81 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 82 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 83 84 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 85 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 86 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 87 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 88 89 static const struct { 90 const char *name; 91 const char *fw_name; 92 } rtl_chip_infos[] = { 93 /* PCI devices. */ 94 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 95 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 96 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 97 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 98 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 99 /* PCI-E devices. */ 100 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 101 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 102 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 103 [RTL_GIGA_MAC_VER_10] = {"RTL8101e/RTL8100e" }, 104 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" }, 105 [RTL_GIGA_MAC_VER_14] = {"RTL8401" }, 106 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 107 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 108 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 109 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 110 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 111 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 112 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 113 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 114 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 115 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 116 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 117 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 118 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 119 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 120 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 121 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 122 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 123 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 124 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 125 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 126 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 127 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 128 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 129 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 130 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 131 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 132 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 133 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 134 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 135 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3}, 136 [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117", }, 137 [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3}, 138 /* reserve 62 for CFG_METHOD_4 in the vendor driver */ 139 [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2}, 140 }; 141 142 static const struct pci_device_id rtl8169_pci_tbl[] = { 143 { PCI_VDEVICE(REALTEK, 0x2502) }, 144 { PCI_VDEVICE(REALTEK, 0x2600) }, 145 { PCI_VDEVICE(REALTEK, 0x8129) }, 146 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 147 { PCI_VDEVICE(REALTEK, 0x8161) }, 148 { PCI_VDEVICE(REALTEK, 0x8162) }, 149 { PCI_VDEVICE(REALTEK, 0x8167) }, 150 { PCI_VDEVICE(REALTEK, 0x8168) }, 151 { PCI_VDEVICE(NCUBE, 0x8168) }, 152 { PCI_VDEVICE(REALTEK, 0x8169) }, 153 { PCI_VENDOR_ID_DLINK, 0x4300, 154 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 155 { PCI_VDEVICE(DLINK, 0x4300) }, 156 { PCI_VDEVICE(DLINK, 0x4302) }, 157 { PCI_VDEVICE(AT, 0xc107) }, 158 { PCI_VDEVICE(USR, 0x0116) }, 159 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 160 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 161 { PCI_VDEVICE(REALTEK, 0x8125) }, 162 { PCI_VDEVICE(REALTEK, 0x3000) }, 163 {} 164 }; 165 166 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 167 168 enum rtl_registers { 169 MAC0 = 0, /* Ethernet hardware address. */ 170 MAC4 = 4, 171 MAR0 = 8, /* Multicast filter. */ 172 CounterAddrLow = 0x10, 173 CounterAddrHigh = 0x14, 174 TxDescStartAddrLow = 0x20, 175 TxDescStartAddrHigh = 0x24, 176 TxHDescStartAddrLow = 0x28, 177 TxHDescStartAddrHigh = 0x2c, 178 FLASH = 0x30, 179 ERSR = 0x36, 180 ChipCmd = 0x37, 181 TxPoll = 0x38, 182 IntrMask = 0x3c, 183 IntrStatus = 0x3e, 184 185 TxConfig = 0x40, 186 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 187 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 188 189 RxConfig = 0x44, 190 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 191 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 192 #define RXCFG_FIFO_SHIFT 13 193 /* No threshold before first PCI xfer */ 194 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 195 #define RX_EARLY_OFF (1 << 11) 196 #define RXCFG_DMA_SHIFT 8 197 /* Unlimited maximum PCI burst. */ 198 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 199 200 Cfg9346 = 0x50, 201 Config0 = 0x51, 202 Config1 = 0x52, 203 Config2 = 0x53, 204 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 205 206 Config3 = 0x54, 207 Config4 = 0x55, 208 Config5 = 0x56, 209 PHYAR = 0x60, 210 PHYstatus = 0x6c, 211 RxMaxSize = 0xda, 212 CPlusCmd = 0xe0, 213 IntrMitigate = 0xe2, 214 215 #define RTL_COALESCE_TX_USECS GENMASK(15, 12) 216 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8) 217 #define RTL_COALESCE_RX_USECS GENMASK(7, 4) 218 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0) 219 220 #define RTL_COALESCE_T_MAX 0x0fU 221 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4) 222 223 RxDescAddrLow = 0xe4, 224 RxDescAddrHigh = 0xe8, 225 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 226 227 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 228 229 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 230 231 #define TxPacketMax (8064 >> 7) 232 #define EarlySize 0x27 233 234 FuncEvent = 0xf0, 235 FuncEventMask = 0xf4, 236 FuncPresetState = 0xf8, 237 IBCR0 = 0xf8, 238 IBCR2 = 0xf9, 239 IBIMR0 = 0xfa, 240 IBISR0 = 0xfb, 241 FuncForceEvent = 0xfc, 242 }; 243 244 enum rtl8168_8101_registers { 245 CSIDR = 0x64, 246 CSIAR = 0x68, 247 #define CSIAR_FLAG 0x80000000 248 #define CSIAR_WRITE_CMD 0x80000000 249 #define CSIAR_BYTE_ENABLE 0x0000f000 250 #define CSIAR_ADDR_MASK 0x00000fff 251 PMCH = 0x6f, 252 #define D3COLD_NO_PLL_DOWN BIT(7) 253 #define D3HOT_NO_PLL_DOWN BIT(6) 254 #define D3_NO_PLL_DOWN (BIT(7) | BIT(6)) 255 EPHYAR = 0x80, 256 #define EPHYAR_FLAG 0x80000000 257 #define EPHYAR_WRITE_CMD 0x80000000 258 #define EPHYAR_REG_MASK 0x1f 259 #define EPHYAR_REG_SHIFT 16 260 #define EPHYAR_DATA_MASK 0xffff 261 DLLPR = 0xd0, 262 #define PFM_EN (1 << 6) 263 #define TX_10M_PS_EN (1 << 7) 264 DBG_REG = 0xd1, 265 #define FIX_NAK_1 (1 << 4) 266 #define FIX_NAK_2 (1 << 3) 267 TWSI = 0xd2, 268 MCU = 0xd3, 269 #define NOW_IS_OOB (1 << 7) 270 #define TX_EMPTY (1 << 5) 271 #define RX_EMPTY (1 << 4) 272 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 273 #define EN_NDP (1 << 3) 274 #define EN_OOB_RESET (1 << 2) 275 #define LINK_LIST_RDY (1 << 1) 276 EFUSEAR = 0xdc, 277 #define EFUSEAR_FLAG 0x80000000 278 #define EFUSEAR_WRITE_CMD 0x80000000 279 #define EFUSEAR_READ_CMD 0x00000000 280 #define EFUSEAR_REG_MASK 0x03ff 281 #define EFUSEAR_REG_SHIFT 8 282 #define EFUSEAR_DATA_MASK 0xff 283 MISC_1 = 0xf2, 284 #define PFM_D3COLD_EN (1 << 6) 285 }; 286 287 enum rtl8168_registers { 288 LED_FREQ = 0x1a, 289 EEE_LED = 0x1b, 290 ERIDR = 0x70, 291 ERIAR = 0x74, 292 #define ERIAR_FLAG 0x80000000 293 #define ERIAR_WRITE_CMD 0x80000000 294 #define ERIAR_READ_CMD 0x00000000 295 #define ERIAR_ADDR_BYTE_ALIGN 4 296 #define ERIAR_TYPE_SHIFT 16 297 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 298 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 299 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 300 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 301 #define ERIAR_MASK_SHIFT 12 302 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 303 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 304 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 305 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 306 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 307 EPHY_RXER_NUM = 0x7c, 308 OCPDR = 0xb0, /* OCP GPHY access */ 309 #define OCPDR_WRITE_CMD 0x80000000 310 #define OCPDR_READ_CMD 0x00000000 311 #define OCPDR_REG_MASK 0x7f 312 #define OCPDR_GPHY_REG_SHIFT 16 313 #define OCPDR_DATA_MASK 0xffff 314 OCPAR = 0xb4, 315 #define OCPAR_FLAG 0x80000000 316 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 317 #define OCPAR_GPHY_READ_CMD 0x0000f060 318 GPHY_OCP = 0xb8, 319 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 320 MISC = 0xf0, /* 8168e only. */ 321 #define TXPLA_RST (1 << 29) 322 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 323 #define PWM_EN (1 << 22) 324 #define RXDV_GATED_EN (1 << 19) 325 #define EARLY_TALLY_EN (1 << 16) 326 }; 327 328 enum rtl8125_registers { 329 IntrMask_8125 = 0x38, 330 IntrStatus_8125 = 0x3c, 331 TxPoll_8125 = 0x90, 332 MAC0_BKP = 0x19e0, 333 EEE_TXIDLE_TIMER_8125 = 0x6048, 334 }; 335 336 #define RX_VLAN_INNER_8125 BIT(22) 337 #define RX_VLAN_OUTER_8125 BIT(23) 338 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 339 340 #define RX_FETCH_DFLT_8125 (8 << 27) 341 342 enum rtl_register_content { 343 /* InterruptStatusBits */ 344 SYSErr = 0x8000, 345 PCSTimeout = 0x4000, 346 SWInt = 0x0100, 347 TxDescUnavail = 0x0080, 348 RxFIFOOver = 0x0040, 349 LinkChg = 0x0020, 350 RxOverflow = 0x0010, 351 TxErr = 0x0008, 352 TxOK = 0x0004, 353 RxErr = 0x0002, 354 RxOK = 0x0001, 355 356 /* RxStatusDesc */ 357 RxRWT = (1 << 22), 358 RxRES = (1 << 21), 359 RxRUNT = (1 << 20), 360 RxCRC = (1 << 19), 361 362 /* ChipCmdBits */ 363 StopReq = 0x80, 364 CmdReset = 0x10, 365 CmdRxEnb = 0x08, 366 CmdTxEnb = 0x04, 367 RxBufEmpty = 0x01, 368 369 /* TXPoll register p.5 */ 370 HPQ = 0x80, /* Poll cmd on the high prio queue */ 371 NPQ = 0x40, /* Poll cmd on the low prio queue */ 372 FSWInt = 0x01, /* Forced software interrupt */ 373 374 /* Cfg9346Bits */ 375 Cfg9346_Lock = 0x00, 376 Cfg9346_Unlock = 0xc0, 377 378 /* rx_mode_bits */ 379 AcceptErr = 0x20, 380 AcceptRunt = 0x10, 381 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30 382 AcceptBroadcast = 0x08, 383 AcceptMulticast = 0x04, 384 AcceptMyPhys = 0x02, 385 AcceptAllPhys = 0x01, 386 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f 387 #define RX_CONFIG_ACCEPT_MASK 0x3f 388 389 /* TxConfigBits */ 390 TxInterFrameGapShift = 24, 391 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 392 393 /* Config1 register p.24 */ 394 LEDS1 = (1 << 7), 395 LEDS0 = (1 << 6), 396 Speed_down = (1 << 4), 397 MEMMAP = (1 << 3), 398 IOMAP = (1 << 2), 399 VPD = (1 << 1), 400 PMEnable = (1 << 0), /* Power Management Enable */ 401 402 /* Config2 register p. 25 */ 403 ClkReqEn = (1 << 7), /* Clock Request Enable */ 404 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 405 PCI_Clock_66MHz = 0x01, 406 PCI_Clock_33MHz = 0x00, 407 408 /* Config3 register p.25 */ 409 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 410 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 411 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 412 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 413 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 414 415 /* Config4 register */ 416 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 417 418 /* Config5 register p.27 */ 419 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 420 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 421 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 422 Spi_en = (1 << 3), 423 LanWake = (1 << 1), /* LanWake enable/disable */ 424 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 425 ASPM_en = (1 << 0), /* ASPM enable */ 426 427 /* CPlusCmd p.31 */ 428 EnableBist = (1 << 15), // 8168 8101 429 Mac_dbgo_oe = (1 << 14), // 8168 8101 430 EnAnaPLL = (1 << 14), // 8169 431 Normal_mode = (1 << 13), // unused 432 Force_half_dup = (1 << 12), // 8168 8101 433 Force_rxflow_en = (1 << 11), // 8168 8101 434 Force_txflow_en = (1 << 10), // 8168 8101 435 Cxpl_dbg_sel = (1 << 9), // 8168 8101 436 ASF = (1 << 8), // 8168 8101 437 PktCntrDisable = (1 << 7), // 8168 8101 438 Mac_dbgo_sel = 0x001c, // 8168 439 RxVlan = (1 << 6), 440 RxChkSum = (1 << 5), 441 PCIDAC = (1 << 4), 442 PCIMulRW = (1 << 3), 443 #define INTT_MASK GENMASK(1, 0) 444 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 445 446 /* rtl8169_PHYstatus */ 447 TBI_Enable = 0x80, 448 TxFlowCtrl = 0x40, 449 RxFlowCtrl = 0x20, 450 _1000bpsF = 0x10, 451 _100bps = 0x08, 452 _10bps = 0x04, 453 LinkStatus = 0x02, 454 FullDup = 0x01, 455 456 /* ResetCounterCommand */ 457 CounterReset = 0x1, 458 459 /* DumpCounterCommand */ 460 CounterDump = 0x8, 461 462 /* magic enable v2 */ 463 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 464 }; 465 466 enum rtl_desc_bit { 467 /* First doubleword. */ 468 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 469 RingEnd = (1 << 30), /* End of descriptor ring */ 470 FirstFrag = (1 << 29), /* First segment of a packet */ 471 LastFrag = (1 << 28), /* Final segment of a packet */ 472 }; 473 474 /* Generic case. */ 475 enum rtl_tx_desc_bit { 476 /* First doubleword. */ 477 TD_LSO = (1 << 27), /* Large Send Offload */ 478 #define TD_MSS_MAX 0x07ffu /* MSS value */ 479 480 /* Second doubleword. */ 481 TxVlanTag = (1 << 17), /* Add VLAN tag */ 482 }; 483 484 /* 8169, 8168b and 810x except 8102e. */ 485 enum rtl_tx_desc_bit_0 { 486 /* First doubleword. */ 487 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 488 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 489 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 490 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 491 }; 492 493 /* 8102e, 8168c and beyond. */ 494 enum rtl_tx_desc_bit_1 { 495 /* First doubleword. */ 496 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 497 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 498 #define GTTCPHO_SHIFT 18 499 #define GTTCPHO_MAX 0x7f 500 501 /* Second doubleword. */ 502 #define TCPHO_SHIFT 18 503 #define TCPHO_MAX 0x3ff 504 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 505 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 506 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 507 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 508 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 509 }; 510 511 enum rtl_rx_desc_bit { 512 /* Rx private */ 513 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 514 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 515 516 #define RxProtoUDP (PID1) 517 #define RxProtoTCP (PID0) 518 #define RxProtoIP (PID1 | PID0) 519 #define RxProtoMask RxProtoIP 520 521 IPFail = (1 << 16), /* IP checksum failed */ 522 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 523 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 524 525 #define RxCSFailMask (IPFail | UDPFail | TCPFail) 526 527 RxVlanTag = (1 << 16), /* VLAN tag available */ 528 }; 529 530 #define RTL_GSO_MAX_SIZE_V1 32000 531 #define RTL_GSO_MAX_SEGS_V1 24 532 #define RTL_GSO_MAX_SIZE_V2 64000 533 #define RTL_GSO_MAX_SEGS_V2 64 534 535 struct TxDesc { 536 __le32 opts1; 537 __le32 opts2; 538 __le64 addr; 539 }; 540 541 struct RxDesc { 542 __le32 opts1; 543 __le32 opts2; 544 __le64 addr; 545 }; 546 547 struct ring_info { 548 struct sk_buff *skb; 549 u32 len; 550 }; 551 552 struct rtl8169_counters { 553 __le64 tx_packets; 554 __le64 rx_packets; 555 __le64 tx_errors; 556 __le32 rx_errors; 557 __le16 rx_missed; 558 __le16 align_errors; 559 __le32 tx_one_collision; 560 __le32 tx_multi_collision; 561 __le64 rx_unicast; 562 __le64 rx_broadcast; 563 __le32 rx_multicast; 564 __le16 tx_aborted; 565 __le16 tx_underun; 566 }; 567 568 struct rtl8169_tc_offsets { 569 bool inited; 570 __le64 tx_errors; 571 __le32 tx_multi_collision; 572 __le16 tx_aborted; 573 __le16 rx_missed; 574 }; 575 576 enum rtl_flag { 577 RTL_FLAG_TASK_ENABLED = 0, 578 RTL_FLAG_TASK_RESET_PENDING, 579 RTL_FLAG_TASK_TX_TIMEOUT, 580 RTL_FLAG_MAX 581 }; 582 583 enum rtl_dash_type { 584 RTL_DASH_NONE, 585 RTL_DASH_DP, 586 RTL_DASH_EP, 587 }; 588 589 struct rtl8169_private { 590 void __iomem *mmio_addr; /* memory map physical address */ 591 struct pci_dev *pci_dev; 592 struct net_device *dev; 593 struct phy_device *phydev; 594 struct napi_struct napi; 595 enum mac_version mac_version; 596 enum rtl_dash_type dash_type; 597 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 598 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 599 u32 dirty_tx; 600 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 601 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 602 dma_addr_t TxPhyAddr; 603 dma_addr_t RxPhyAddr; 604 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 605 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 606 u16 cp_cmd; 607 u32 irq_mask; 608 int irq; 609 struct clk *clk; 610 611 struct { 612 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 613 struct work_struct work; 614 } wk; 615 616 unsigned supports_gmii:1; 617 unsigned aspm_manageable:1; 618 dma_addr_t counters_phys_addr; 619 struct rtl8169_counters *counters; 620 struct rtl8169_tc_offsets tc_offset; 621 u32 saved_wolopts; 622 int eee_adv; 623 624 const char *fw_name; 625 struct rtl_fw *rtl_fw; 626 627 u32 ocp_base; 628 }; 629 630 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 631 632 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 633 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 634 MODULE_SOFTDEP("pre: realtek"); 635 MODULE_LICENSE("GPL"); 636 MODULE_FIRMWARE(FIRMWARE_8168D_1); 637 MODULE_FIRMWARE(FIRMWARE_8168D_2); 638 MODULE_FIRMWARE(FIRMWARE_8168E_1); 639 MODULE_FIRMWARE(FIRMWARE_8168E_2); 640 MODULE_FIRMWARE(FIRMWARE_8168E_3); 641 MODULE_FIRMWARE(FIRMWARE_8105E_1); 642 MODULE_FIRMWARE(FIRMWARE_8168F_1); 643 MODULE_FIRMWARE(FIRMWARE_8168F_2); 644 MODULE_FIRMWARE(FIRMWARE_8402_1); 645 MODULE_FIRMWARE(FIRMWARE_8411_1); 646 MODULE_FIRMWARE(FIRMWARE_8411_2); 647 MODULE_FIRMWARE(FIRMWARE_8106E_1); 648 MODULE_FIRMWARE(FIRMWARE_8106E_2); 649 MODULE_FIRMWARE(FIRMWARE_8168G_2); 650 MODULE_FIRMWARE(FIRMWARE_8168G_3); 651 MODULE_FIRMWARE(FIRMWARE_8168H_2); 652 MODULE_FIRMWARE(FIRMWARE_8168FP_3); 653 MODULE_FIRMWARE(FIRMWARE_8107E_2); 654 MODULE_FIRMWARE(FIRMWARE_8125A_3); 655 MODULE_FIRMWARE(FIRMWARE_8125B_2); 656 657 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 658 { 659 return &tp->pci_dev->dev; 660 } 661 662 static void rtl_lock_config_regs(struct rtl8169_private *tp) 663 { 664 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 665 } 666 667 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 668 { 669 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 670 } 671 672 static void rtl_pci_commit(struct rtl8169_private *tp) 673 { 674 /* Read an arbitrary register to commit a preceding PCI write */ 675 RTL_R8(tp, ChipCmd); 676 } 677 678 static bool rtl_is_8125(struct rtl8169_private *tp) 679 { 680 return tp->mac_version >= RTL_GIGA_MAC_VER_61; 681 } 682 683 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 684 { 685 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 686 tp->mac_version != RTL_GIGA_MAC_VER_39 && 687 tp->mac_version <= RTL_GIGA_MAC_VER_53; 688 } 689 690 static bool rtl_supports_eee(struct rtl8169_private *tp) 691 { 692 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 693 tp->mac_version != RTL_GIGA_MAC_VER_37 && 694 tp->mac_version != RTL_GIGA_MAC_VER_39; 695 } 696 697 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 698 { 699 int i; 700 701 for (i = 0; i < ETH_ALEN; i++) 702 mac[i] = RTL_R8(tp, reg + i); 703 } 704 705 struct rtl_cond { 706 bool (*check)(struct rtl8169_private *); 707 const char *msg; 708 }; 709 710 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 711 unsigned long usecs, int n, bool high) 712 { 713 int i; 714 715 for (i = 0; i < n; i++) { 716 if (c->check(tp) == high) 717 return true; 718 fsleep(usecs); 719 } 720 721 if (net_ratelimit()) 722 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n", 723 c->msg, !high, n, usecs); 724 return false; 725 } 726 727 static bool rtl_loop_wait_high(struct rtl8169_private *tp, 728 const struct rtl_cond *c, 729 unsigned long d, int n) 730 { 731 return rtl_loop_wait(tp, c, d, n, true); 732 } 733 734 static bool rtl_loop_wait_low(struct rtl8169_private *tp, 735 const struct rtl_cond *c, 736 unsigned long d, int n) 737 { 738 return rtl_loop_wait(tp, c, d, n, false); 739 } 740 741 #define DECLARE_RTL_COND(name) \ 742 static bool name ## _check(struct rtl8169_private *); \ 743 \ 744 static const struct rtl_cond name = { \ 745 .check = name ## _check, \ 746 .msg = #name \ 747 }; \ 748 \ 749 static bool name ## _check(struct rtl8169_private *tp) 750 751 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type) 752 { 753 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */ 754 if (type == ERIAR_OOB && 755 (tp->mac_version == RTL_GIGA_MAC_VER_52 || 756 tp->mac_version == RTL_GIGA_MAC_VER_53)) 757 *cmd |= 0xf70 << 18; 758 } 759 760 DECLARE_RTL_COND(rtl_eriar_cond) 761 { 762 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 763 } 764 765 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 766 u32 val, int type) 767 { 768 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr; 769 770 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask)) 771 return; 772 773 RTL_W32(tp, ERIDR, val); 774 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 775 RTL_W32(tp, ERIAR, cmd); 776 777 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 778 } 779 780 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 781 u32 val) 782 { 783 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 784 } 785 786 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 787 { 788 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr; 789 790 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 791 RTL_W32(tp, ERIAR, cmd); 792 793 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 794 RTL_R32(tp, ERIDR) : ~0; 795 } 796 797 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 798 { 799 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 800 } 801 802 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m) 803 { 804 u32 val = rtl_eri_read(tp, addr); 805 806 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p); 807 } 808 809 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p) 810 { 811 rtl_w0w1_eri(tp, addr, p, 0); 812 } 813 814 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m) 815 { 816 rtl_w0w1_eri(tp, addr, 0, m); 817 } 818 819 static bool rtl_ocp_reg_failure(u32 reg) 820 { 821 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg); 822 } 823 824 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 825 { 826 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 827 } 828 829 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 830 { 831 if (rtl_ocp_reg_failure(reg)) 832 return; 833 834 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 835 836 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 837 } 838 839 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 840 { 841 if (rtl_ocp_reg_failure(reg)) 842 return 0; 843 844 RTL_W32(tp, GPHY_OCP, reg << 15); 845 846 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 847 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 848 } 849 850 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 851 { 852 if (rtl_ocp_reg_failure(reg)) 853 return; 854 855 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 856 } 857 858 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 859 { 860 if (rtl_ocp_reg_failure(reg)) 861 return 0; 862 863 RTL_W32(tp, OCPDR, reg << 15); 864 865 return RTL_R32(tp, OCPDR); 866 } 867 868 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 869 u16 set) 870 { 871 u16 data = r8168_mac_ocp_read(tp, reg); 872 873 r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 874 } 875 876 /* Work around a hw issue with RTL8168g PHY, the quirk disables 877 * PHY MCU interrupts before PHY power-down. 878 */ 879 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value) 880 { 881 switch (tp->mac_version) { 882 case RTL_GIGA_MAC_VER_40: 883 if (value & BMCR_RESET || !(value & BMCR_PDOWN)) 884 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); 885 else 886 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); 887 break; 888 default: 889 break; 890 } 891 }; 892 893 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 894 { 895 if (reg == 0x1f) { 896 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 897 return; 898 } 899 900 if (tp->ocp_base != OCP_STD_PHY_BASE) 901 reg -= 0x10; 902 903 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR) 904 rtl8168g_phy_suspend_quirk(tp, value); 905 906 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 907 } 908 909 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 910 { 911 if (reg == 0x1f) 912 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; 913 914 if (tp->ocp_base != OCP_STD_PHY_BASE) 915 reg -= 0x10; 916 917 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 918 } 919 920 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 921 { 922 if (reg == 0x1f) { 923 tp->ocp_base = value << 4; 924 return; 925 } 926 927 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 928 } 929 930 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 931 { 932 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 933 } 934 935 DECLARE_RTL_COND(rtl_phyar_cond) 936 { 937 return RTL_R32(tp, PHYAR) & 0x80000000; 938 } 939 940 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 941 { 942 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 943 944 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 945 /* 946 * According to hardware specs a 20us delay is required after write 947 * complete indication, but before sending next command. 948 */ 949 udelay(20); 950 } 951 952 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 953 { 954 int value; 955 956 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 957 958 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 959 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 960 961 /* 962 * According to hardware specs a 20us delay is required after read 963 * complete indication, but before sending next command. 964 */ 965 udelay(20); 966 967 return value; 968 } 969 970 DECLARE_RTL_COND(rtl_ocpar_cond) 971 { 972 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 973 } 974 975 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 976 977 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 978 { 979 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 980 } 981 982 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 983 { 984 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 985 } 986 987 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 988 { 989 r8168dp_2_mdio_start(tp); 990 991 r8169_mdio_write(tp, reg, value); 992 993 r8168dp_2_mdio_stop(tp); 994 } 995 996 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 997 { 998 int value; 999 1000 /* Work around issue with chip reporting wrong PHY ID */ 1001 if (reg == MII_PHYSID2) 1002 return 0xc912; 1003 1004 r8168dp_2_mdio_start(tp); 1005 1006 value = r8169_mdio_read(tp, reg); 1007 1008 r8168dp_2_mdio_stop(tp); 1009 1010 return value; 1011 } 1012 1013 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 1014 { 1015 switch (tp->mac_version) { 1016 case RTL_GIGA_MAC_VER_28: 1017 case RTL_GIGA_MAC_VER_31: 1018 r8168dp_2_mdio_write(tp, location, val); 1019 break; 1020 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 1021 r8168g_mdio_write(tp, location, val); 1022 break; 1023 default: 1024 r8169_mdio_write(tp, location, val); 1025 break; 1026 } 1027 } 1028 1029 static int rtl_readphy(struct rtl8169_private *tp, int location) 1030 { 1031 switch (tp->mac_version) { 1032 case RTL_GIGA_MAC_VER_28: 1033 case RTL_GIGA_MAC_VER_31: 1034 return r8168dp_2_mdio_read(tp, location); 1035 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 1036 return r8168g_mdio_read(tp, location); 1037 default: 1038 return r8169_mdio_read(tp, location); 1039 } 1040 } 1041 1042 DECLARE_RTL_COND(rtl_ephyar_cond) 1043 { 1044 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1045 } 1046 1047 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1048 { 1049 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1050 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1051 1052 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1053 1054 udelay(10); 1055 } 1056 1057 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1058 { 1059 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1060 1061 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1062 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1063 } 1064 1065 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg) 1066 { 1067 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); 1068 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1069 RTL_R32(tp, OCPDR) : ~0; 1070 } 1071 1072 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg) 1073 { 1074 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1075 } 1076 1077 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1078 u32 data) 1079 { 1080 RTL_W32(tp, OCPDR, data); 1081 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1082 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1083 } 1084 1085 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1086 u32 data) 1087 { 1088 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1089 data, ERIAR_OOB); 1090 } 1091 1092 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1093 { 1094 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1095 1096 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1097 } 1098 1099 #define OOB_CMD_RESET 0x00 1100 #define OOB_CMD_DRIVER_START 0x05 1101 #define OOB_CMD_DRIVER_STOP 0x06 1102 1103 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1104 { 1105 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1106 } 1107 1108 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1109 { 1110 u16 reg; 1111 1112 reg = rtl8168_get_ocp_reg(tp); 1113 1114 return r8168dp_ocp_read(tp, reg) & 0x00000800; 1115 } 1116 1117 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1118 { 1119 return r8168ep_ocp_read(tp, 0x124) & 0x00000001; 1120 } 1121 1122 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1123 { 1124 return RTL_R8(tp, IBISR0) & 0x20; 1125 } 1126 1127 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1128 { 1129 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1130 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000); 1131 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1132 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1133 } 1134 1135 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1136 { 1137 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1138 rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1139 } 1140 1141 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1142 { 1143 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1144 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1145 rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1146 } 1147 1148 static void rtl8168_driver_start(struct rtl8169_private *tp) 1149 { 1150 if (tp->dash_type == RTL_DASH_DP) 1151 rtl8168dp_driver_start(tp); 1152 else 1153 rtl8168ep_driver_start(tp); 1154 } 1155 1156 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1157 { 1158 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1159 rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1160 } 1161 1162 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1163 { 1164 rtl8168ep_stop_cmac(tp); 1165 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1166 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1167 rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1168 } 1169 1170 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1171 { 1172 if (tp->dash_type == RTL_DASH_DP) 1173 rtl8168dp_driver_stop(tp); 1174 else 1175 rtl8168ep_driver_stop(tp); 1176 } 1177 1178 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1179 { 1180 u16 reg = rtl8168_get_ocp_reg(tp); 1181 1182 return r8168dp_ocp_read(tp, reg) & BIT(15); 1183 } 1184 1185 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1186 { 1187 return r8168ep_ocp_read(tp, 0x128) & BIT(0); 1188 } 1189 1190 static enum rtl_dash_type rtl_check_dash(struct rtl8169_private *tp) 1191 { 1192 switch (tp->mac_version) { 1193 case RTL_GIGA_MAC_VER_28: 1194 case RTL_GIGA_MAC_VER_31: 1195 return r8168dp_check_dash(tp) ? RTL_DASH_DP : RTL_DASH_NONE; 1196 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 1197 return r8168ep_check_dash(tp) ? RTL_DASH_EP : RTL_DASH_NONE; 1198 default: 1199 return RTL_DASH_NONE; 1200 } 1201 } 1202 1203 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable) 1204 { 1205 switch (tp->mac_version) { 1206 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26: 1207 case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30: 1208 case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37: 1209 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63: 1210 if (enable) 1211 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN); 1212 else 1213 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN); 1214 break; 1215 default: 1216 break; 1217 } 1218 } 1219 1220 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1221 { 1222 rtl_eri_clear_bits(tp, 0xdc, BIT(0)); 1223 rtl_eri_set_bits(tp, 0xdc, BIT(0)); 1224 } 1225 1226 DECLARE_RTL_COND(rtl_efusear_cond) 1227 { 1228 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1229 } 1230 1231 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1232 { 1233 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1234 1235 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1236 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1237 } 1238 1239 static u32 rtl_get_events(struct rtl8169_private *tp) 1240 { 1241 if (rtl_is_8125(tp)) 1242 return RTL_R32(tp, IntrStatus_8125); 1243 else 1244 return RTL_R16(tp, IntrStatus); 1245 } 1246 1247 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1248 { 1249 if (rtl_is_8125(tp)) 1250 RTL_W32(tp, IntrStatus_8125, bits); 1251 else 1252 RTL_W16(tp, IntrStatus, bits); 1253 } 1254 1255 static void rtl_irq_disable(struct rtl8169_private *tp) 1256 { 1257 if (rtl_is_8125(tp)) 1258 RTL_W32(tp, IntrMask_8125, 0); 1259 else 1260 RTL_W16(tp, IntrMask, 0); 1261 } 1262 1263 static void rtl_irq_enable(struct rtl8169_private *tp) 1264 { 1265 if (rtl_is_8125(tp)) 1266 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1267 else 1268 RTL_W16(tp, IntrMask, tp->irq_mask); 1269 } 1270 1271 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1272 { 1273 rtl_irq_disable(tp); 1274 rtl_ack_events(tp, 0xffffffff); 1275 rtl_pci_commit(tp); 1276 } 1277 1278 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1279 { 1280 struct phy_device *phydev = tp->phydev; 1281 1282 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1283 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1284 if (phydev->speed == SPEED_1000) { 1285 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1286 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1287 } else if (phydev->speed == SPEED_100) { 1288 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1289 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1290 } else { 1291 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1292 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1293 } 1294 rtl_reset_packet_filter(tp); 1295 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1296 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1297 if (phydev->speed == SPEED_1000) { 1298 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1299 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1300 } else { 1301 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1302 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1303 } 1304 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1305 if (phydev->speed == SPEED_10) { 1306 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1307 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1308 } else { 1309 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1310 } 1311 } 1312 } 1313 1314 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1315 1316 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1317 { 1318 struct rtl8169_private *tp = netdev_priv(dev); 1319 1320 wol->supported = WAKE_ANY; 1321 wol->wolopts = tp->saved_wolopts; 1322 } 1323 1324 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1325 { 1326 static const struct { 1327 u32 opt; 1328 u16 reg; 1329 u8 mask; 1330 } cfg[] = { 1331 { WAKE_PHY, Config3, LinkUp }, 1332 { WAKE_UCAST, Config5, UWF }, 1333 { WAKE_BCAST, Config5, BWF }, 1334 { WAKE_MCAST, Config5, MWF }, 1335 { WAKE_ANY, Config5, LanWake }, 1336 { WAKE_MAGIC, Config3, MagicPacket } 1337 }; 1338 unsigned int i, tmp = ARRAY_SIZE(cfg); 1339 u8 options; 1340 1341 rtl_unlock_config_regs(tp); 1342 1343 if (rtl_is_8168evl_up(tp)) { 1344 tmp--; 1345 if (wolopts & WAKE_MAGIC) 1346 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2); 1347 else 1348 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2); 1349 } else if (rtl_is_8125(tp)) { 1350 tmp--; 1351 if (wolopts & WAKE_MAGIC) 1352 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1353 else 1354 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1355 } 1356 1357 for (i = 0; i < tmp; i++) { 1358 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; 1359 if (wolopts & cfg[i].opt) 1360 options |= cfg[i].mask; 1361 RTL_W8(tp, cfg[i].reg, options); 1362 } 1363 1364 switch (tp->mac_version) { 1365 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1366 options = RTL_R8(tp, Config1) & ~PMEnable; 1367 if (wolopts) 1368 options |= PMEnable; 1369 RTL_W8(tp, Config1, options); 1370 break; 1371 case RTL_GIGA_MAC_VER_34: 1372 case RTL_GIGA_MAC_VER_37: 1373 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63: 1374 options = RTL_R8(tp, Config2) & ~PME_SIGNAL; 1375 if (wolopts) 1376 options |= PME_SIGNAL; 1377 RTL_W8(tp, Config2, options); 1378 break; 1379 default: 1380 break; 1381 } 1382 1383 rtl_lock_config_regs(tp); 1384 1385 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1386 1387 if (tp->dash_type == RTL_DASH_NONE) { 1388 rtl_set_d3_pll_down(tp, !wolopts); 1389 tp->dev->wol_enabled = wolopts ? 1 : 0; 1390 } 1391 } 1392 1393 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1394 { 1395 struct rtl8169_private *tp = netdev_priv(dev); 1396 1397 if (wol->wolopts & ~WAKE_ANY) 1398 return -EINVAL; 1399 1400 tp->saved_wolopts = wol->wolopts; 1401 __rtl8169_set_wol(tp, tp->saved_wolopts); 1402 1403 return 0; 1404 } 1405 1406 static void rtl8169_get_drvinfo(struct net_device *dev, 1407 struct ethtool_drvinfo *info) 1408 { 1409 struct rtl8169_private *tp = netdev_priv(dev); 1410 struct rtl_fw *rtl_fw = tp->rtl_fw; 1411 1412 strscpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); 1413 strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1414 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1415 if (rtl_fw) 1416 strscpy(info->fw_version, rtl_fw->version, 1417 sizeof(info->fw_version)); 1418 } 1419 1420 static int rtl8169_get_regs_len(struct net_device *dev) 1421 { 1422 return R8169_REGS_SIZE; 1423 } 1424 1425 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1426 netdev_features_t features) 1427 { 1428 struct rtl8169_private *tp = netdev_priv(dev); 1429 1430 if (dev->mtu > TD_MSS_MAX) 1431 features &= ~NETIF_F_ALL_TSO; 1432 1433 if (dev->mtu > ETH_DATA_LEN && 1434 tp->mac_version > RTL_GIGA_MAC_VER_06) 1435 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1436 1437 return features; 1438 } 1439 1440 static void rtl_set_rx_config_features(struct rtl8169_private *tp, 1441 netdev_features_t features) 1442 { 1443 u32 rx_config = RTL_R32(tp, RxConfig); 1444 1445 if (features & NETIF_F_RXALL) 1446 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK; 1447 else 1448 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK; 1449 1450 if (rtl_is_8125(tp)) { 1451 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1452 rx_config |= RX_VLAN_8125; 1453 else 1454 rx_config &= ~RX_VLAN_8125; 1455 } 1456 1457 RTL_W32(tp, RxConfig, rx_config); 1458 } 1459 1460 static int rtl8169_set_features(struct net_device *dev, 1461 netdev_features_t features) 1462 { 1463 struct rtl8169_private *tp = netdev_priv(dev); 1464 1465 rtl_set_rx_config_features(tp, features); 1466 1467 if (features & NETIF_F_RXCSUM) 1468 tp->cp_cmd |= RxChkSum; 1469 else 1470 tp->cp_cmd &= ~RxChkSum; 1471 1472 if (!rtl_is_8125(tp)) { 1473 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1474 tp->cp_cmd |= RxVlan; 1475 else 1476 tp->cp_cmd &= ~RxVlan; 1477 } 1478 1479 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1480 rtl_pci_commit(tp); 1481 1482 return 0; 1483 } 1484 1485 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1486 { 1487 return (skb_vlan_tag_present(skb)) ? 1488 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1489 } 1490 1491 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1492 { 1493 u32 opts2 = le32_to_cpu(desc->opts2); 1494 1495 if (opts2 & RxVlanTag) 1496 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1497 } 1498 1499 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1500 void *p) 1501 { 1502 struct rtl8169_private *tp = netdev_priv(dev); 1503 u32 __iomem *data = tp->mmio_addr; 1504 u32 *dw = p; 1505 int i; 1506 1507 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1508 memcpy_fromio(dw++, data++, 4); 1509 } 1510 1511 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1512 "tx_packets", 1513 "rx_packets", 1514 "tx_errors", 1515 "rx_errors", 1516 "rx_missed", 1517 "align_errors", 1518 "tx_single_collisions", 1519 "tx_multi_collisions", 1520 "unicast", 1521 "broadcast", 1522 "multicast", 1523 "tx_aborted", 1524 "tx_underrun", 1525 }; 1526 1527 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1528 { 1529 switch (sset) { 1530 case ETH_SS_STATS: 1531 return ARRAY_SIZE(rtl8169_gstrings); 1532 default: 1533 return -EOPNOTSUPP; 1534 } 1535 } 1536 1537 DECLARE_RTL_COND(rtl_counters_cond) 1538 { 1539 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1540 } 1541 1542 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1543 { 1544 u32 cmd = lower_32_bits(tp->counters_phys_addr); 1545 1546 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr)); 1547 rtl_pci_commit(tp); 1548 RTL_W32(tp, CounterAddrLow, cmd); 1549 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1550 1551 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1552 } 1553 1554 static void rtl8169_update_counters(struct rtl8169_private *tp) 1555 { 1556 u8 val = RTL_R8(tp, ChipCmd); 1557 1558 /* 1559 * Some chips are unable to dump tally counters when the receiver 1560 * is disabled. If 0xff chip may be in a PCI power-save state. 1561 */ 1562 if (val & CmdRxEnb && val != 0xff) 1563 rtl8169_do_counters(tp, CounterDump); 1564 } 1565 1566 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1567 { 1568 struct rtl8169_counters *counters = tp->counters; 1569 1570 /* 1571 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1572 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1573 * reset by a power cycle, while the counter values collected by the 1574 * driver are reset at every driver unload/load cycle. 1575 * 1576 * To make sure the HW values returned by @get_stats64 match the SW 1577 * values, we collect the initial values at first open(*) and use them 1578 * as offsets to normalize the values returned by @get_stats64. 1579 * 1580 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1581 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1582 * set at open time by rtl_hw_start. 1583 */ 1584 1585 if (tp->tc_offset.inited) 1586 return; 1587 1588 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) { 1589 rtl8169_do_counters(tp, CounterReset); 1590 } else { 1591 rtl8169_update_counters(tp); 1592 tp->tc_offset.tx_errors = counters->tx_errors; 1593 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1594 tp->tc_offset.tx_aborted = counters->tx_aborted; 1595 tp->tc_offset.rx_missed = counters->rx_missed; 1596 } 1597 1598 tp->tc_offset.inited = true; 1599 } 1600 1601 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1602 struct ethtool_stats *stats, u64 *data) 1603 { 1604 struct rtl8169_private *tp = netdev_priv(dev); 1605 struct rtl8169_counters *counters; 1606 1607 counters = tp->counters; 1608 rtl8169_update_counters(tp); 1609 1610 data[0] = le64_to_cpu(counters->tx_packets); 1611 data[1] = le64_to_cpu(counters->rx_packets); 1612 data[2] = le64_to_cpu(counters->tx_errors); 1613 data[3] = le32_to_cpu(counters->rx_errors); 1614 data[4] = le16_to_cpu(counters->rx_missed); 1615 data[5] = le16_to_cpu(counters->align_errors); 1616 data[6] = le32_to_cpu(counters->tx_one_collision); 1617 data[7] = le32_to_cpu(counters->tx_multi_collision); 1618 data[8] = le64_to_cpu(counters->rx_unicast); 1619 data[9] = le64_to_cpu(counters->rx_broadcast); 1620 data[10] = le32_to_cpu(counters->rx_multicast); 1621 data[11] = le16_to_cpu(counters->tx_aborted); 1622 data[12] = le16_to_cpu(counters->tx_underun); 1623 } 1624 1625 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1626 { 1627 switch(stringset) { 1628 case ETH_SS_STATS: 1629 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1630 break; 1631 } 1632 } 1633 1634 /* 1635 * Interrupt coalescing 1636 * 1637 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1638 * > 8169, 8168 and 810x line of chipsets 1639 * 1640 * 8169, 8168, and 8136(810x) serial chipsets support it. 1641 * 1642 * > 2 - the Tx timer unit at gigabit speed 1643 * 1644 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1645 * (0xe0) bit 1 and bit 0. 1646 * 1647 * For 8169 1648 * bit[1:0] \ speed 1000M 100M 10M 1649 * 0 0 320ns 2.56us 40.96us 1650 * 0 1 2.56us 20.48us 327.7us 1651 * 1 0 5.12us 40.96us 655.4us 1652 * 1 1 10.24us 81.92us 1.31ms 1653 * 1654 * For the other 1655 * bit[1:0] \ speed 1000M 100M 10M 1656 * 0 0 5us 2.56us 40.96us 1657 * 0 1 40us 20.48us 327.7us 1658 * 1 0 80us 40.96us 655.4us 1659 * 1 1 160us 81.92us 1.31ms 1660 */ 1661 1662 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1663 struct rtl_coalesce_info { 1664 u32 speed; 1665 u32 scale_nsecs[4]; 1666 }; 1667 1668 /* produce array with base delay *1, *8, *8*2, *8*2*2 */ 1669 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) } 1670 1671 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1672 { SPEED_1000, COALESCE_DELAY(320) }, 1673 { SPEED_100, COALESCE_DELAY(2560) }, 1674 { SPEED_10, COALESCE_DELAY(40960) }, 1675 { 0 }, 1676 }; 1677 1678 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1679 { SPEED_1000, COALESCE_DELAY(5000) }, 1680 { SPEED_100, COALESCE_DELAY(2560) }, 1681 { SPEED_10, COALESCE_DELAY(40960) }, 1682 { 0 }, 1683 }; 1684 #undef COALESCE_DELAY 1685 1686 /* get rx/tx scale vector corresponding to current speed */ 1687 static const struct rtl_coalesce_info * 1688 rtl_coalesce_info(struct rtl8169_private *tp) 1689 { 1690 const struct rtl_coalesce_info *ci; 1691 1692 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1693 ci = rtl_coalesce_info_8169; 1694 else 1695 ci = rtl_coalesce_info_8168_8136; 1696 1697 /* if speed is unknown assume highest one */ 1698 if (tp->phydev->speed == SPEED_UNKNOWN) 1699 return ci; 1700 1701 for (; ci->speed; ci++) { 1702 if (tp->phydev->speed == ci->speed) 1703 return ci; 1704 } 1705 1706 return ERR_PTR(-ELNRNG); 1707 } 1708 1709 static int rtl_get_coalesce(struct net_device *dev, 1710 struct ethtool_coalesce *ec, 1711 struct kernel_ethtool_coalesce *kernel_coal, 1712 struct netlink_ext_ack *extack) 1713 { 1714 struct rtl8169_private *tp = netdev_priv(dev); 1715 const struct rtl_coalesce_info *ci; 1716 u32 scale, c_us, c_fr; 1717 u16 intrmit; 1718 1719 if (rtl_is_8125(tp)) 1720 return -EOPNOTSUPP; 1721 1722 memset(ec, 0, sizeof(*ec)); 1723 1724 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1725 ci = rtl_coalesce_info(tp); 1726 if (IS_ERR(ci)) 1727 return PTR_ERR(ci); 1728 1729 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK]; 1730 1731 intrmit = RTL_R16(tp, IntrMitigate); 1732 1733 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit); 1734 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1735 1736 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit); 1737 /* ethtool_coalesce states usecs and max_frames must not both be 0 */ 1738 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1739 1740 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit); 1741 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1742 1743 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit); 1744 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1745 1746 return 0; 1747 } 1748 1749 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */ 1750 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec, 1751 u16 *cp01) 1752 { 1753 const struct rtl_coalesce_info *ci; 1754 u16 i; 1755 1756 ci = rtl_coalesce_info(tp); 1757 if (IS_ERR(ci)) 1758 return PTR_ERR(ci); 1759 1760 for (i = 0; i < 4; i++) { 1761 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) { 1762 *cp01 = i; 1763 return ci->scale_nsecs[i]; 1764 } 1765 } 1766 1767 return -ERANGE; 1768 } 1769 1770 static int rtl_set_coalesce(struct net_device *dev, 1771 struct ethtool_coalesce *ec, 1772 struct kernel_ethtool_coalesce *kernel_coal, 1773 struct netlink_ext_ack *extack) 1774 { 1775 struct rtl8169_private *tp = netdev_priv(dev); 1776 u32 tx_fr = ec->tx_max_coalesced_frames; 1777 u32 rx_fr = ec->rx_max_coalesced_frames; 1778 u32 coal_usec_max, units; 1779 u16 w = 0, cp01 = 0; 1780 int scale; 1781 1782 if (rtl_is_8125(tp)) 1783 return -EOPNOTSUPP; 1784 1785 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX) 1786 return -ERANGE; 1787 1788 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs); 1789 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01); 1790 if (scale < 0) 1791 return scale; 1792 1793 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it 1794 * not only when usecs=0 because of e.g. the following scenario: 1795 * 1796 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 1797 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 1798 * - then user does `ethtool -C eth0 rx-usecs 100` 1799 * 1800 * Since ethtool sends to kernel whole ethtool_coalesce settings, 1801 * if we want to ignore rx_frames then it has to be set to 0. 1802 */ 1803 if (rx_fr == 1) 1804 rx_fr = 0; 1805 if (tx_fr == 1) 1806 tx_fr = 0; 1807 1808 /* HW requires time limit to be set if frame limit is set */ 1809 if ((tx_fr && !ec->tx_coalesce_usecs) || 1810 (rx_fr && !ec->rx_coalesce_usecs)) 1811 return -EINVAL; 1812 1813 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4)); 1814 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4)); 1815 1816 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale); 1817 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units); 1818 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale); 1819 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units); 1820 1821 RTL_W16(tp, IntrMitigate, w); 1822 1823 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */ 1824 if (rtl_is_8168evl_up(tp)) { 1825 if (!rx_fr && !tx_fr) 1826 /* disable packet counter */ 1827 tp->cp_cmd |= PktCntrDisable; 1828 else 1829 tp->cp_cmd &= ~PktCntrDisable; 1830 } 1831 1832 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 1833 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1834 rtl_pci_commit(tp); 1835 1836 return 0; 1837 } 1838 1839 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data) 1840 { 1841 struct rtl8169_private *tp = netdev_priv(dev); 1842 1843 if (!rtl_supports_eee(tp)) 1844 return -EOPNOTSUPP; 1845 1846 return phy_ethtool_get_eee(tp->phydev, data); 1847 } 1848 1849 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data) 1850 { 1851 struct rtl8169_private *tp = netdev_priv(dev); 1852 int ret; 1853 1854 if (!rtl_supports_eee(tp)) 1855 return -EOPNOTSUPP; 1856 1857 ret = phy_ethtool_set_eee(tp->phydev, data); 1858 1859 if (!ret) 1860 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN, 1861 MDIO_AN_EEE_ADV); 1862 return ret; 1863 } 1864 1865 static void rtl8169_get_ringparam(struct net_device *dev, 1866 struct ethtool_ringparam *data, 1867 struct kernel_ethtool_ringparam *kernel_data, 1868 struct netlink_ext_ack *extack) 1869 { 1870 data->rx_max_pending = NUM_RX_DESC; 1871 data->rx_pending = NUM_RX_DESC; 1872 data->tx_max_pending = NUM_TX_DESC; 1873 data->tx_pending = NUM_TX_DESC; 1874 } 1875 1876 static void rtl8169_get_pauseparam(struct net_device *dev, 1877 struct ethtool_pauseparam *data) 1878 { 1879 struct rtl8169_private *tp = netdev_priv(dev); 1880 bool tx_pause, rx_pause; 1881 1882 phy_get_pause(tp->phydev, &tx_pause, &rx_pause); 1883 1884 data->autoneg = tp->phydev->autoneg; 1885 data->tx_pause = tx_pause ? 1 : 0; 1886 data->rx_pause = rx_pause ? 1 : 0; 1887 } 1888 1889 static int rtl8169_set_pauseparam(struct net_device *dev, 1890 struct ethtool_pauseparam *data) 1891 { 1892 struct rtl8169_private *tp = netdev_priv(dev); 1893 1894 if (dev->mtu > ETH_DATA_LEN) 1895 return -EOPNOTSUPP; 1896 1897 phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause); 1898 1899 return 0; 1900 } 1901 1902 static const struct ethtool_ops rtl8169_ethtool_ops = { 1903 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 1904 ETHTOOL_COALESCE_MAX_FRAMES, 1905 .get_drvinfo = rtl8169_get_drvinfo, 1906 .get_regs_len = rtl8169_get_regs_len, 1907 .get_link = ethtool_op_get_link, 1908 .get_coalesce = rtl_get_coalesce, 1909 .set_coalesce = rtl_set_coalesce, 1910 .get_regs = rtl8169_get_regs, 1911 .get_wol = rtl8169_get_wol, 1912 .set_wol = rtl8169_set_wol, 1913 .get_strings = rtl8169_get_strings, 1914 .get_sset_count = rtl8169_get_sset_count, 1915 .get_ethtool_stats = rtl8169_get_ethtool_stats, 1916 .get_ts_info = ethtool_op_get_ts_info, 1917 .nway_reset = phy_ethtool_nway_reset, 1918 .get_eee = rtl8169_get_eee, 1919 .set_eee = rtl8169_set_eee, 1920 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1921 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1922 .get_ringparam = rtl8169_get_ringparam, 1923 .get_pauseparam = rtl8169_get_pauseparam, 1924 .set_pauseparam = rtl8169_set_pauseparam, 1925 }; 1926 1927 static void rtl_enable_eee(struct rtl8169_private *tp) 1928 { 1929 struct phy_device *phydev = tp->phydev; 1930 int adv; 1931 1932 /* respect EEE advertisement the user may have set */ 1933 if (tp->eee_adv >= 0) 1934 adv = tp->eee_adv; 1935 else 1936 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 1937 1938 if (adv >= 0) 1939 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv); 1940 } 1941 1942 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii) 1943 { 1944 /* 1945 * The driver currently handles the 8168Bf and the 8168Be identically 1946 * but they can be identified more specifically through the test below 1947 * if needed: 1948 * 1949 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 1950 * 1951 * Same thing for the 8101Eb and the 8101Ec: 1952 * 1953 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 1954 */ 1955 static const struct rtl_mac_info { 1956 u16 mask; 1957 u16 val; 1958 enum mac_version ver; 1959 } mac_info[] = { 1960 /* 8125B family. */ 1961 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 }, 1962 1963 /* 8125A family. */ 1964 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61 }, 1965 /* It seems only XID 609 made it to the mass market. 1966 * { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, 1967 * { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, 1968 */ 1969 1970 /* RTL8117 */ 1971 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 }, 1972 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, 1973 1974 /* 8168EP family. */ 1975 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 1976 /* It seems this chip version never made it to 1977 * the wild. Let's disable detection. 1978 * { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 1979 * { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 1980 */ 1981 1982 /* 8168H family. */ 1983 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 1984 /* It seems this chip version never made it to 1985 * the wild. Let's disable detection. 1986 * { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 1987 */ 1988 1989 /* 8168G family. */ 1990 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 1991 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 1992 /* It seems this chip version never made it to 1993 * the wild. Let's disable detection. 1994 * { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 1995 */ 1996 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 1997 1998 /* 8168F family. */ 1999 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 2000 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 2001 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 2002 2003 /* 8168E family. */ 2004 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 2005 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 2006 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 2007 2008 /* 8168D family. */ 2009 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 2010 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 2011 2012 /* 8168DP family. */ 2013 /* It seems this early RTL8168dp version never made it to 2014 * the wild. Support has been removed. 2015 * { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 2016 */ 2017 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 2018 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 2019 2020 /* 8168C family. */ 2021 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 2022 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 2023 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 2024 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 2025 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 2026 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 2027 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 2028 2029 /* 8168B family. */ 2030 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 2031 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 2032 2033 /* 8101 family. */ 2034 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2035 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2036 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2037 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2038 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2039 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2040 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2041 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2042 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 }, 2043 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2044 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2045 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10 }, 2046 2047 /* 8110 family. */ 2048 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2049 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2050 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2051 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2052 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2053 2054 /* Catch-all */ 2055 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2056 }; 2057 const struct rtl_mac_info *p = mac_info; 2058 enum mac_version ver; 2059 2060 while ((xid & p->mask) != p->val) 2061 p++; 2062 ver = p->ver; 2063 2064 if (ver != RTL_GIGA_MAC_NONE && !gmii) { 2065 if (ver == RTL_GIGA_MAC_VER_42) 2066 ver = RTL_GIGA_MAC_VER_43; 2067 else if (ver == RTL_GIGA_MAC_VER_46) 2068 ver = RTL_GIGA_MAC_VER_48; 2069 } 2070 2071 return ver; 2072 } 2073 2074 static void rtl_release_firmware(struct rtl8169_private *tp) 2075 { 2076 if (tp->rtl_fw) { 2077 rtl_fw_release_firmware(tp->rtl_fw); 2078 kfree(tp->rtl_fw); 2079 tp->rtl_fw = NULL; 2080 } 2081 } 2082 2083 void r8169_apply_firmware(struct rtl8169_private *tp) 2084 { 2085 int val; 2086 2087 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2088 if (tp->rtl_fw) { 2089 rtl_fw_write_firmware(tp, tp->rtl_fw); 2090 /* At least one firmware doesn't reset tp->ocp_base. */ 2091 tp->ocp_base = OCP_STD_PHY_BASE; 2092 2093 /* PHY soft reset may still be in progress */ 2094 phy_read_poll_timeout(tp->phydev, MII_BMCR, val, 2095 !(val & BMCR_RESET), 2096 50000, 600000, true); 2097 } 2098 } 2099 2100 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2101 { 2102 /* Adjust EEE LED frequency */ 2103 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2104 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2105 2106 rtl_eri_set_bits(tp, 0x1b0, 0x0003); 2107 } 2108 2109 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp) 2110 { 2111 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2112 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2113 } 2114 2115 static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp) 2116 { 2117 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20); 2118 } 2119 2120 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp) 2121 { 2122 rtl8125_set_eee_txidle_timer(tp); 2123 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2124 } 2125 2126 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr) 2127 { 2128 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr)); 2129 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4)); 2130 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16); 2131 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2)); 2132 } 2133 2134 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) 2135 { 2136 u16 data1, data2, ioffset; 2137 2138 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 2139 data1 = r8168_mac_ocp_read(tp, 0xdd02); 2140 data2 = r8168_mac_ocp_read(tp, 0xdd00); 2141 2142 ioffset = (data2 >> 1) & 0x7ff8; 2143 ioffset |= data2 & 0x0007; 2144 if (data1 & BIT(7)) 2145 ioffset |= BIT(15); 2146 2147 return ioffset; 2148 } 2149 2150 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 2151 { 2152 set_bit(flag, tp->wk.flags); 2153 schedule_work(&tp->wk.work); 2154 } 2155 2156 static void rtl8169_init_phy(struct rtl8169_private *tp) 2157 { 2158 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); 2159 2160 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 2161 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 2162 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 2163 /* set undocumented MAC Reg C+CR Offset 0x82h */ 2164 RTL_W8(tp, 0x82, 0x01); 2165 } 2166 2167 if (tp->mac_version == RTL_GIGA_MAC_VER_05 && 2168 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE && 2169 tp->pci_dev->subsystem_device == 0xe000) 2170 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); 2171 2172 /* We may have called phy_speed_down before */ 2173 phy_speed_up(tp->phydev); 2174 2175 if (rtl_supports_eee(tp)) 2176 rtl_enable_eee(tp); 2177 2178 genphy_soft_reset(tp->phydev); 2179 } 2180 2181 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr) 2182 { 2183 rtl_unlock_config_regs(tp); 2184 2185 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4)); 2186 rtl_pci_commit(tp); 2187 2188 RTL_W32(tp, MAC0, get_unaligned_le32(addr)); 2189 rtl_pci_commit(tp); 2190 2191 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 2192 rtl_rar_exgmac_set(tp, addr); 2193 2194 rtl_lock_config_regs(tp); 2195 } 2196 2197 static int rtl_set_mac_address(struct net_device *dev, void *p) 2198 { 2199 struct rtl8169_private *tp = netdev_priv(dev); 2200 int ret; 2201 2202 ret = eth_mac_addr(dev, p); 2203 if (ret) 2204 return ret; 2205 2206 rtl_rar_set(tp, dev->dev_addr); 2207 2208 return 0; 2209 } 2210 2211 static void rtl_init_rxcfg(struct rtl8169_private *tp) 2212 { 2213 switch (tp->mac_version) { 2214 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 2215 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 2216 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 2217 break; 2218 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 2219 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2220 case RTL_GIGA_MAC_VER_38: 2221 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 2222 break; 2223 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2224 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 2225 break; 2226 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 2227 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); 2228 break; 2229 default: 2230 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 2231 break; 2232 } 2233 } 2234 2235 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 2236 { 2237 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 2238 } 2239 2240 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) 2241 { 2242 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2243 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); 2244 } 2245 2246 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) 2247 { 2248 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2249 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); 2250 } 2251 2252 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) 2253 { 2254 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2255 } 2256 2257 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) 2258 { 2259 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2260 } 2261 2262 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) 2263 { 2264 RTL_W8(tp, MaxTxPacketSize, 0x24); 2265 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2266 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); 2267 } 2268 2269 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) 2270 { 2271 RTL_W8(tp, MaxTxPacketSize, 0x3f); 2272 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2273 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); 2274 } 2275 2276 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) 2277 { 2278 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); 2279 } 2280 2281 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) 2282 { 2283 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); 2284 } 2285 2286 static void rtl_jumbo_config(struct rtl8169_private *tp) 2287 { 2288 bool jumbo = tp->dev->mtu > ETH_DATA_LEN; 2289 int readrq = 4096; 2290 2291 rtl_unlock_config_regs(tp); 2292 switch (tp->mac_version) { 2293 case RTL_GIGA_MAC_VER_17: 2294 if (jumbo) { 2295 readrq = 512; 2296 r8168b_1_hw_jumbo_enable(tp); 2297 } else { 2298 r8168b_1_hw_jumbo_disable(tp); 2299 } 2300 break; 2301 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 2302 if (jumbo) { 2303 readrq = 512; 2304 r8168c_hw_jumbo_enable(tp); 2305 } else { 2306 r8168c_hw_jumbo_disable(tp); 2307 } 2308 break; 2309 case RTL_GIGA_MAC_VER_28: 2310 if (jumbo) 2311 r8168dp_hw_jumbo_enable(tp); 2312 else 2313 r8168dp_hw_jumbo_disable(tp); 2314 break; 2315 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 2316 if (jumbo) 2317 r8168e_hw_jumbo_enable(tp); 2318 else 2319 r8168e_hw_jumbo_disable(tp); 2320 break; 2321 default: 2322 break; 2323 } 2324 rtl_lock_config_regs(tp); 2325 2326 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii) 2327 pcie_set_readrq(tp->pci_dev, readrq); 2328 2329 /* Chip doesn't support pause in jumbo mode */ 2330 if (jumbo) { 2331 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2332 tp->phydev->advertising); 2333 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2334 tp->phydev->advertising); 2335 phy_start_aneg(tp->phydev); 2336 } 2337 } 2338 2339 DECLARE_RTL_COND(rtl_chipcmd_cond) 2340 { 2341 return RTL_R8(tp, ChipCmd) & CmdReset; 2342 } 2343 2344 static void rtl_hw_reset(struct rtl8169_private *tp) 2345 { 2346 RTL_W8(tp, ChipCmd, CmdReset); 2347 2348 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 2349 } 2350 2351 static void rtl_request_firmware(struct rtl8169_private *tp) 2352 { 2353 struct rtl_fw *rtl_fw; 2354 2355 /* firmware loaded already or no firmware available */ 2356 if (tp->rtl_fw || !tp->fw_name) 2357 return; 2358 2359 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 2360 if (!rtl_fw) 2361 return; 2362 2363 rtl_fw->phy_write = rtl_writephy; 2364 rtl_fw->phy_read = rtl_readphy; 2365 rtl_fw->mac_mcu_write = mac_mcu_write; 2366 rtl_fw->mac_mcu_read = mac_mcu_read; 2367 rtl_fw->fw_name = tp->fw_name; 2368 rtl_fw->dev = tp_to_dev(tp); 2369 2370 if (rtl_fw_request_firmware(rtl_fw)) 2371 kfree(rtl_fw); 2372 else 2373 tp->rtl_fw = rtl_fw; 2374 } 2375 2376 static void rtl_rx_close(struct rtl8169_private *tp) 2377 { 2378 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 2379 } 2380 2381 DECLARE_RTL_COND(rtl_npq_cond) 2382 { 2383 return RTL_R8(tp, TxPoll) & NPQ; 2384 } 2385 2386 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 2387 { 2388 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 2389 } 2390 2391 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 2392 { 2393 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 2394 } 2395 2396 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2) 2397 { 2398 /* IntrMitigate has new functionality on RTL8125 */ 2399 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103; 2400 } 2401 2402 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp) 2403 { 2404 switch (tp->mac_version) { 2405 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2406 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42); 2407 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2408 break; 2409 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61: 2410 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2411 break; 2412 case RTL_GIGA_MAC_VER_63: 2413 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2414 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2415 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42); 2416 break; 2417 default: 2418 break; 2419 } 2420 } 2421 2422 static void rtl_disable_rxdvgate(struct rtl8169_private *tp) 2423 { 2424 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 2425 } 2426 2427 static void rtl_enable_rxdvgate(struct rtl8169_private *tp) 2428 { 2429 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 2430 fsleep(2000); 2431 rtl_wait_txrx_fifo_empty(tp); 2432 } 2433 2434 static void rtl_wol_enable_rx(struct rtl8169_private *tp) 2435 { 2436 if (tp->mac_version >= RTL_GIGA_MAC_VER_25) 2437 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 2438 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 2439 2440 if (tp->mac_version >= RTL_GIGA_MAC_VER_40) 2441 rtl_disable_rxdvgate(tp); 2442 } 2443 2444 static void rtl_prepare_power_down(struct rtl8169_private *tp) 2445 { 2446 if (tp->dash_type != RTL_DASH_NONE) 2447 return; 2448 2449 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 2450 tp->mac_version == RTL_GIGA_MAC_VER_33) 2451 rtl_ephy_write(tp, 0x19, 0xff64); 2452 2453 if (device_may_wakeup(tp_to_dev(tp))) { 2454 phy_speed_down(tp->phydev, false); 2455 rtl_wol_enable_rx(tp); 2456 } 2457 } 2458 2459 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 2460 { 2461 u32 val = TX_DMA_BURST << TxDMAShift | 2462 InterFrameGap << TxInterFrameGapShift; 2463 2464 if (rtl_is_8168evl_up(tp)) 2465 val |= TXCFG_AUTO_FIFO; 2466 2467 RTL_W32(tp, TxConfig, val); 2468 } 2469 2470 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 2471 { 2472 /* Low hurts. Let's disable the filtering. */ 2473 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 2474 } 2475 2476 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 2477 { 2478 /* 2479 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 2480 * register to be written before TxDescAddrLow to work. 2481 * Switching from MMIO to I/O access fixes the issue as well. 2482 */ 2483 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 2484 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 2485 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 2486 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 2487 } 2488 2489 static void rtl8169_set_magic_reg(struct rtl8169_private *tp) 2490 { 2491 u32 val; 2492 2493 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 2494 val = 0x000fff00; 2495 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 2496 val = 0x00ffff00; 2497 else 2498 return; 2499 2500 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 2501 val |= 0xff; 2502 2503 RTL_W32(tp, 0x7c, val); 2504 } 2505 2506 static void rtl_set_rx_mode(struct net_device *dev) 2507 { 2508 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 2509 /* Multicast hash filter */ 2510 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 2511 struct rtl8169_private *tp = netdev_priv(dev); 2512 u32 tmp; 2513 2514 if (dev->flags & IFF_PROMISC) { 2515 rx_mode |= AcceptAllPhys; 2516 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT || 2517 dev->flags & IFF_ALLMULTI || 2518 tp->mac_version == RTL_GIGA_MAC_VER_35) { 2519 /* accept all multicasts */ 2520 } else if (netdev_mc_empty(dev)) { 2521 rx_mode &= ~AcceptMulticast; 2522 } else { 2523 struct netdev_hw_addr *ha; 2524 2525 mc_filter[1] = mc_filter[0] = 0; 2526 netdev_for_each_mc_addr(ha, dev) { 2527 u32 bit_nr = eth_hw_addr_crc(ha) >> 26; 2528 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 2529 } 2530 2531 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 2532 tmp = mc_filter[0]; 2533 mc_filter[0] = swab32(mc_filter[1]); 2534 mc_filter[1] = swab32(tmp); 2535 } 2536 } 2537 2538 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 2539 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 2540 2541 tmp = RTL_R32(tp, RxConfig); 2542 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); 2543 } 2544 2545 DECLARE_RTL_COND(rtl_csiar_cond) 2546 { 2547 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 2548 } 2549 2550 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 2551 { 2552 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2553 2554 RTL_W32(tp, CSIDR, value); 2555 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 2556 CSIAR_BYTE_ENABLE | func << 16); 2557 2558 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 2559 } 2560 2561 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 2562 { 2563 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2564 2565 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 2566 CSIAR_BYTE_ENABLE); 2567 2568 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 2569 RTL_R32(tp, CSIDR) : ~0; 2570 } 2571 2572 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val) 2573 { 2574 struct pci_dev *pdev = tp->pci_dev; 2575 u32 csi; 2576 2577 /* According to Realtek the value at config space address 0x070f 2578 * controls the L0s/L1 entrance latency. We try standard ECAM access 2579 * first and if it fails fall back to CSI. 2580 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo) 2581 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us 2582 */ 2583 if (pdev->cfg_size > 0x070f && 2584 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 2585 return; 2586 2587 netdev_notice_once(tp->dev, 2588 "No native access to PCI extended config space, falling back to CSI\n"); 2589 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 2590 rtl_csi_write(tp, 0x070c, csi | val << 24); 2591 } 2592 2593 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 2594 { 2595 /* L0 7us, L1 16us */ 2596 rtl_set_aspm_entry_latency(tp, 0x27); 2597 } 2598 2599 struct ephy_info { 2600 unsigned int offset; 2601 u16 mask; 2602 u16 bits; 2603 }; 2604 2605 static void __rtl_ephy_init(struct rtl8169_private *tp, 2606 const struct ephy_info *e, int len) 2607 { 2608 u16 w; 2609 2610 while (len-- > 0) { 2611 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 2612 rtl_ephy_write(tp, e->offset, w); 2613 e++; 2614 } 2615 } 2616 2617 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 2618 2619 static void rtl_disable_clock_request(struct rtl8169_private *tp) 2620 { 2621 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 2622 PCI_EXP_LNKCTL_CLKREQ_EN); 2623 } 2624 2625 static void rtl_enable_clock_request(struct rtl8169_private *tp) 2626 { 2627 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 2628 PCI_EXP_LNKCTL_CLKREQ_EN); 2629 } 2630 2631 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 2632 { 2633 /* work around an issue when PCI reset occurs during L2/L3 state */ 2634 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 2635 } 2636 2637 static void rtl_enable_exit_l1(struct rtl8169_private *tp) 2638 { 2639 /* Bits control which events trigger ASPM L1 exit: 2640 * Bit 12: rxdv 2641 * Bit 11: ltr_msg 2642 * Bit 10: txdma_poll 2643 * Bit 9: xadm 2644 * Bit 8: pktavi 2645 * Bit 7: txpla 2646 */ 2647 switch (tp->mac_version) { 2648 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2649 rtl_eri_set_bits(tp, 0xd4, 0x1f00); 2650 break; 2651 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38: 2652 rtl_eri_set_bits(tp, 0xd4, 0x0c00); 2653 break; 2654 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 2655 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80); 2656 break; 2657 default: 2658 break; 2659 } 2660 } 2661 2662 static void rtl_disable_exit_l1(struct rtl8169_private *tp) 2663 { 2664 switch (tp->mac_version) { 2665 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 2666 rtl_eri_clear_bits(tp, 0xd4, 0x1f00); 2667 break; 2668 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 2669 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0); 2670 break; 2671 default: 2672 break; 2673 } 2674 } 2675 2676 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 2677 { 2678 /* Don't enable ASPM in the chip if OS can't control ASPM */ 2679 if (enable && tp->aspm_manageable) { 2680 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en); 2681 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn); 2682 2683 switch (tp->mac_version) { 2684 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2685 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 2686 /* reset ephy tx/rx disable timer */ 2687 r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0); 2688 /* chip can trigger L1.2 */ 2689 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2)); 2690 break; 2691 default: 2692 break; 2693 } 2694 } else { 2695 switch (tp->mac_version) { 2696 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2697 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 2698 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0); 2699 break; 2700 default: 2701 break; 2702 } 2703 2704 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn); 2705 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en); 2706 } 2707 2708 udelay(10); 2709 } 2710 2711 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 2712 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 2713 { 2714 /* Usage of dynamic vs. static FIFO is controlled by bit 2715 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 2716 */ 2717 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 2718 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 2719 } 2720 2721 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 2722 u8 low, u8 high) 2723 { 2724 /* FIFO thresholds for pause flow control */ 2725 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 2726 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 2727 } 2728 2729 static void rtl_hw_start_8168b(struct rtl8169_private *tp) 2730 { 2731 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2732 } 2733 2734 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 2735 { 2736 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 2737 2738 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2739 2740 rtl_disable_clock_request(tp); 2741 } 2742 2743 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 2744 { 2745 static const struct ephy_info e_info_8168cp[] = { 2746 { 0x01, 0, 0x0001 }, 2747 { 0x02, 0x0800, 0x1000 }, 2748 { 0x03, 0, 0x0042 }, 2749 { 0x06, 0x0080, 0x0000 }, 2750 { 0x07, 0, 0x2000 } 2751 }; 2752 2753 rtl_set_def_aspm_entry_latency(tp); 2754 2755 rtl_ephy_init(tp, e_info_8168cp); 2756 2757 __rtl_hw_start_8168cp(tp); 2758 } 2759 2760 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 2761 { 2762 rtl_set_def_aspm_entry_latency(tp); 2763 2764 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2765 } 2766 2767 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 2768 { 2769 rtl_set_def_aspm_entry_latency(tp); 2770 2771 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2772 2773 /* Magic. */ 2774 RTL_W8(tp, DBG_REG, 0x20); 2775 } 2776 2777 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 2778 { 2779 static const struct ephy_info e_info_8168c_1[] = { 2780 { 0x02, 0x0800, 0x1000 }, 2781 { 0x03, 0, 0x0002 }, 2782 { 0x06, 0x0080, 0x0000 } 2783 }; 2784 2785 rtl_set_def_aspm_entry_latency(tp); 2786 2787 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 2788 2789 rtl_ephy_init(tp, e_info_8168c_1); 2790 2791 __rtl_hw_start_8168cp(tp); 2792 } 2793 2794 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 2795 { 2796 static const struct ephy_info e_info_8168c_2[] = { 2797 { 0x01, 0, 0x0001 }, 2798 { 0x03, 0x0400, 0x0020 } 2799 }; 2800 2801 rtl_set_def_aspm_entry_latency(tp); 2802 2803 rtl_ephy_init(tp, e_info_8168c_2); 2804 2805 __rtl_hw_start_8168cp(tp); 2806 } 2807 2808 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 2809 { 2810 rtl_set_def_aspm_entry_latency(tp); 2811 2812 __rtl_hw_start_8168cp(tp); 2813 } 2814 2815 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 2816 { 2817 rtl_set_def_aspm_entry_latency(tp); 2818 2819 rtl_disable_clock_request(tp); 2820 } 2821 2822 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 2823 { 2824 static const struct ephy_info e_info_8168d_4[] = { 2825 { 0x0b, 0x0000, 0x0048 }, 2826 { 0x19, 0x0020, 0x0050 }, 2827 { 0x0c, 0x0100, 0x0020 }, 2828 { 0x10, 0x0004, 0x0000 }, 2829 }; 2830 2831 rtl_set_def_aspm_entry_latency(tp); 2832 2833 rtl_ephy_init(tp, e_info_8168d_4); 2834 2835 rtl_enable_clock_request(tp); 2836 } 2837 2838 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 2839 { 2840 static const struct ephy_info e_info_8168e_1[] = { 2841 { 0x00, 0x0200, 0x0100 }, 2842 { 0x00, 0x0000, 0x0004 }, 2843 { 0x06, 0x0002, 0x0001 }, 2844 { 0x06, 0x0000, 0x0030 }, 2845 { 0x07, 0x0000, 0x2000 }, 2846 { 0x00, 0x0000, 0x0020 }, 2847 { 0x03, 0x5800, 0x2000 }, 2848 { 0x03, 0x0000, 0x0001 }, 2849 { 0x01, 0x0800, 0x1000 }, 2850 { 0x07, 0x0000, 0x4000 }, 2851 { 0x1e, 0x0000, 0x2000 }, 2852 { 0x19, 0xffff, 0xfe6c }, 2853 { 0x0a, 0x0000, 0x0040 } 2854 }; 2855 2856 rtl_set_def_aspm_entry_latency(tp); 2857 2858 rtl_ephy_init(tp, e_info_8168e_1); 2859 2860 rtl_disable_clock_request(tp); 2861 2862 /* Reset tx FIFO pointer */ 2863 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 2864 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 2865 2866 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2867 } 2868 2869 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 2870 { 2871 static const struct ephy_info e_info_8168e_2[] = { 2872 { 0x09, 0x0000, 0x0080 }, 2873 { 0x19, 0x0000, 0x0224 }, 2874 { 0x00, 0x0000, 0x0004 }, 2875 { 0x0c, 0x3df0, 0x0200 }, 2876 }; 2877 2878 rtl_set_def_aspm_entry_latency(tp); 2879 2880 rtl_ephy_init(tp, e_info_8168e_2); 2881 2882 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2883 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 2884 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 2885 rtl_eri_set_bits(tp, 0x1d0, BIT(1)); 2886 rtl_reset_packet_filter(tp); 2887 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 2888 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 2889 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 2890 2891 rtl_disable_clock_request(tp); 2892 2893 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 2894 2895 rtl8168_config_eee_mac(tp); 2896 2897 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 2898 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 2899 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2900 2901 rtl_hw_aspm_clkreq_enable(tp, true); 2902 } 2903 2904 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 2905 { 2906 rtl_set_def_aspm_entry_latency(tp); 2907 2908 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2909 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 2910 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 2911 rtl_reset_packet_filter(tp); 2912 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 2913 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1)); 2914 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 2915 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 2916 2917 rtl_disable_clock_request(tp); 2918 2919 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 2920 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 2921 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 2922 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2923 2924 rtl8168_config_eee_mac(tp); 2925 } 2926 2927 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 2928 { 2929 static const struct ephy_info e_info_8168f_1[] = { 2930 { 0x06, 0x00c0, 0x0020 }, 2931 { 0x08, 0x0001, 0x0002 }, 2932 { 0x09, 0x0000, 0x0080 }, 2933 { 0x19, 0x0000, 0x0224 }, 2934 { 0x00, 0x0000, 0x0008 }, 2935 { 0x0c, 0x3df0, 0x0200 }, 2936 }; 2937 2938 rtl_hw_start_8168f(tp); 2939 2940 rtl_ephy_init(tp, e_info_8168f_1); 2941 } 2942 2943 static void rtl_hw_start_8411(struct rtl8169_private *tp) 2944 { 2945 static const struct ephy_info e_info_8168f_1[] = { 2946 { 0x06, 0x00c0, 0x0020 }, 2947 { 0x0f, 0xffff, 0x5200 }, 2948 { 0x19, 0x0000, 0x0224 }, 2949 { 0x00, 0x0000, 0x0008 }, 2950 { 0x0c, 0x3df0, 0x0200 }, 2951 }; 2952 2953 rtl_hw_start_8168f(tp); 2954 rtl_pcie_state_l2l3_disable(tp); 2955 2956 rtl_ephy_init(tp, e_info_8168f_1); 2957 } 2958 2959 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 2960 { 2961 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 2962 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 2963 2964 rtl_set_def_aspm_entry_latency(tp); 2965 2966 rtl_reset_packet_filter(tp); 2967 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 2968 2969 rtl_disable_rxdvgate(tp); 2970 2971 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2972 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 2973 2974 rtl8168_config_eee_mac(tp); 2975 2976 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 2977 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 2978 2979 rtl_pcie_state_l2l3_disable(tp); 2980 } 2981 2982 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 2983 { 2984 static const struct ephy_info e_info_8168g_1[] = { 2985 { 0x00, 0x0008, 0x0000 }, 2986 { 0x0c, 0x3ff0, 0x0820 }, 2987 { 0x1e, 0x0000, 0x0001 }, 2988 { 0x19, 0x8000, 0x0000 } 2989 }; 2990 2991 rtl_hw_start_8168g(tp); 2992 2993 /* disable aspm and clock request before access ephy */ 2994 rtl_hw_aspm_clkreq_enable(tp, false); 2995 rtl_ephy_init(tp, e_info_8168g_1); 2996 rtl_hw_aspm_clkreq_enable(tp, true); 2997 } 2998 2999 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 3000 { 3001 static const struct ephy_info e_info_8168g_2[] = { 3002 { 0x00, 0x0008, 0x0000 }, 3003 { 0x0c, 0x3ff0, 0x0820 }, 3004 { 0x19, 0xffff, 0x7c00 }, 3005 { 0x1e, 0xffff, 0x20eb }, 3006 { 0x0d, 0xffff, 0x1666 }, 3007 { 0x00, 0xffff, 0x10a3 }, 3008 { 0x06, 0xffff, 0xf050 }, 3009 { 0x04, 0x0000, 0x0010 }, 3010 { 0x1d, 0x4000, 0x0000 }, 3011 }; 3012 3013 rtl_hw_start_8168g(tp); 3014 3015 /* disable aspm and clock request before access ephy */ 3016 rtl_hw_aspm_clkreq_enable(tp, false); 3017 rtl_ephy_init(tp, e_info_8168g_2); 3018 } 3019 3020 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 3021 { 3022 static const struct ephy_info e_info_8411_2[] = { 3023 { 0x00, 0x0008, 0x0000 }, 3024 { 0x0c, 0x37d0, 0x0820 }, 3025 { 0x1e, 0x0000, 0x0001 }, 3026 { 0x19, 0x8021, 0x0000 }, 3027 { 0x1e, 0x0000, 0x2000 }, 3028 { 0x0d, 0x0100, 0x0200 }, 3029 { 0x00, 0x0000, 0x0080 }, 3030 { 0x06, 0x0000, 0x0010 }, 3031 { 0x04, 0x0000, 0x0010 }, 3032 { 0x1d, 0x0000, 0x4000 }, 3033 }; 3034 3035 rtl_hw_start_8168g(tp); 3036 3037 /* disable aspm and clock request before access ephy */ 3038 rtl_hw_aspm_clkreq_enable(tp, false); 3039 rtl_ephy_init(tp, e_info_8411_2); 3040 3041 /* The following Realtek-provided magic fixes an issue with the RX unit 3042 * getting confused after the PHY having been powered-down. 3043 */ 3044 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 3045 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 3046 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 3047 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 3048 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 3049 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 3050 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 3051 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 3052 mdelay(3); 3053 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 3054 3055 r8168_mac_ocp_write(tp, 0xF800, 0xE008); 3056 r8168_mac_ocp_write(tp, 0xF802, 0xE00A); 3057 r8168_mac_ocp_write(tp, 0xF804, 0xE00C); 3058 r8168_mac_ocp_write(tp, 0xF806, 0xE00E); 3059 r8168_mac_ocp_write(tp, 0xF808, 0xE027); 3060 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F); 3061 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E); 3062 r8168_mac_ocp_write(tp, 0xF80E, 0xE065); 3063 r8168_mac_ocp_write(tp, 0xF810, 0xC602); 3064 r8168_mac_ocp_write(tp, 0xF812, 0xBE00); 3065 r8168_mac_ocp_write(tp, 0xF814, 0x0000); 3066 r8168_mac_ocp_write(tp, 0xF816, 0xC502); 3067 r8168_mac_ocp_write(tp, 0xF818, 0xBD00); 3068 r8168_mac_ocp_write(tp, 0xF81A, 0x074C); 3069 r8168_mac_ocp_write(tp, 0xF81C, 0xC302); 3070 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00); 3071 r8168_mac_ocp_write(tp, 0xF820, 0x080A); 3072 r8168_mac_ocp_write(tp, 0xF822, 0x6420); 3073 r8168_mac_ocp_write(tp, 0xF824, 0x48C2); 3074 r8168_mac_ocp_write(tp, 0xF826, 0x8C20); 3075 r8168_mac_ocp_write(tp, 0xF828, 0xC516); 3076 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4); 3077 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0); 3078 r8168_mac_ocp_write(tp, 0xF82E, 0xF009); 3079 r8168_mac_ocp_write(tp, 0xF830, 0x74A2); 3080 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5); 3081 r8168_mac_ocp_write(tp, 0xF834, 0x74A0); 3082 r8168_mac_ocp_write(tp, 0xF836, 0xC50E); 3083 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2); 3084 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11); 3085 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0); 3086 r8168_mac_ocp_write(tp, 0xF83E, 0xE006); 3087 r8168_mac_ocp_write(tp, 0xF840, 0x74F8); 3088 r8168_mac_ocp_write(tp, 0xF842, 0x48C4); 3089 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8); 3090 r8168_mac_ocp_write(tp, 0xF846, 0xC404); 3091 r8168_mac_ocp_write(tp, 0xF848, 0xBC00); 3092 r8168_mac_ocp_write(tp, 0xF84A, 0xC403); 3093 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00); 3094 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2); 3095 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A); 3096 r8168_mac_ocp_write(tp, 0xF852, 0xE434); 3097 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0); 3098 r8168_mac_ocp_write(tp, 0xF856, 0x49D9); 3099 r8168_mac_ocp_write(tp, 0xF858, 0xF01F); 3100 r8168_mac_ocp_write(tp, 0xF85A, 0xC526); 3101 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5); 3102 r8168_mac_ocp_write(tp, 0xF85E, 0x1400); 3103 r8168_mac_ocp_write(tp, 0xF860, 0xF007); 3104 r8168_mac_ocp_write(tp, 0xF862, 0x0C01); 3105 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5); 3106 r8168_mac_ocp_write(tp, 0xF866, 0x1C15); 3107 r8168_mac_ocp_write(tp, 0xF868, 0xC51B); 3108 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0); 3109 r8168_mac_ocp_write(tp, 0xF86C, 0xE013); 3110 r8168_mac_ocp_write(tp, 0xF86E, 0xC519); 3111 r8168_mac_ocp_write(tp, 0xF870, 0x74A0); 3112 r8168_mac_ocp_write(tp, 0xF872, 0x48C4); 3113 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0); 3114 r8168_mac_ocp_write(tp, 0xF876, 0xC516); 3115 r8168_mac_ocp_write(tp, 0xF878, 0x74A4); 3116 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8); 3117 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA); 3118 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4); 3119 r8168_mac_ocp_write(tp, 0xF880, 0xC512); 3120 r8168_mac_ocp_write(tp, 0xF882, 0x1B00); 3121 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0); 3122 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C); 3123 r8168_mac_ocp_write(tp, 0xF888, 0x483F); 3124 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2); 3125 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04); 3126 r8168_mac_ocp_write(tp, 0xF88E, 0xC508); 3127 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0); 3128 r8168_mac_ocp_write(tp, 0xF892, 0xC505); 3129 r8168_mac_ocp_write(tp, 0xF894, 0xBD00); 3130 r8168_mac_ocp_write(tp, 0xF896, 0xC502); 3131 r8168_mac_ocp_write(tp, 0xF898, 0xBD00); 3132 r8168_mac_ocp_write(tp, 0xF89A, 0x0300); 3133 r8168_mac_ocp_write(tp, 0xF89C, 0x051E); 3134 r8168_mac_ocp_write(tp, 0xF89E, 0xE434); 3135 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018); 3136 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092); 3137 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20); 3138 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0); 3139 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F); 3140 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4); 3141 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3); 3142 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007); 3143 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0); 3144 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103); 3145 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607); 3146 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00); 3147 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606); 3148 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00); 3149 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602); 3150 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00); 3151 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C); 3152 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28); 3153 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C); 3154 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00); 3155 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707); 3156 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00); 3157 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2); 3158 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1); 3159 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502); 3160 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00); 3161 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA); 3162 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0); 3163 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502); 3164 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00); 3165 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132); 3166 3167 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 3168 3169 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 3170 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 3171 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 3172 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 3173 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 3174 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 3175 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 3176 3177 rtl_hw_aspm_clkreq_enable(tp, true); 3178 } 3179 3180 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 3181 { 3182 static const struct ephy_info e_info_8168h_1[] = { 3183 { 0x1e, 0x0800, 0x0001 }, 3184 { 0x1d, 0x0000, 0x0800 }, 3185 { 0x05, 0xffff, 0x2089 }, 3186 { 0x06, 0xffff, 0x5881 }, 3187 { 0x04, 0xffff, 0x854a }, 3188 { 0x01, 0xffff, 0x068b } 3189 }; 3190 int rg_saw_cnt; 3191 3192 /* disable aspm and clock request before access ephy */ 3193 rtl_hw_aspm_clkreq_enable(tp, false); 3194 rtl_ephy_init(tp, e_info_8168h_1); 3195 3196 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3197 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3198 3199 rtl_set_def_aspm_entry_latency(tp); 3200 3201 rtl_reset_packet_filter(tp); 3202 3203 rtl_eri_set_bits(tp, 0xdc, 0x001c); 3204 3205 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3206 3207 rtl_disable_rxdvgate(tp); 3208 3209 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3210 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3211 3212 rtl8168_config_eee_mac(tp); 3213 3214 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3215 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3216 3217 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3218 3219 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3220 3221 rtl_pcie_state_l2l3_disable(tp); 3222 3223 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3224 if (rg_saw_cnt > 0) { 3225 u16 sw_cnt_1ms_ini; 3226 3227 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 3228 sw_cnt_1ms_ini &= 0x0fff; 3229 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3230 } 3231 3232 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3233 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 3234 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 3235 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3236 3237 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3238 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3239 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3240 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3241 3242 rtl_hw_aspm_clkreq_enable(tp, true); 3243 } 3244 3245 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 3246 { 3247 rtl8168ep_stop_cmac(tp); 3248 3249 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3250 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3251 3252 rtl_set_def_aspm_entry_latency(tp); 3253 3254 rtl_reset_packet_filter(tp); 3255 3256 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3257 3258 rtl_disable_rxdvgate(tp); 3259 3260 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3261 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3262 3263 rtl8168_config_eee_mac(tp); 3264 3265 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3266 3267 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3268 3269 rtl_pcie_state_l2l3_disable(tp); 3270 } 3271 3272 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 3273 { 3274 static const struct ephy_info e_info_8168ep_3[] = { 3275 { 0x00, 0x0000, 0x0080 }, 3276 { 0x0d, 0x0100, 0x0200 }, 3277 { 0x19, 0x8021, 0x0000 }, 3278 { 0x1e, 0x0000, 0x2000 }, 3279 }; 3280 3281 /* disable aspm and clock request before access ephy */ 3282 rtl_hw_aspm_clkreq_enable(tp, false); 3283 rtl_ephy_init(tp, e_info_8168ep_3); 3284 3285 rtl_hw_start_8168ep(tp); 3286 3287 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3288 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3289 3290 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 3291 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3292 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3293 3294 rtl_hw_aspm_clkreq_enable(tp, true); 3295 } 3296 3297 static void rtl_hw_start_8117(struct rtl8169_private *tp) 3298 { 3299 static const struct ephy_info e_info_8117[] = { 3300 { 0x19, 0x0040, 0x1100 }, 3301 { 0x59, 0x0040, 0x1100 }, 3302 }; 3303 int rg_saw_cnt; 3304 3305 rtl8168ep_stop_cmac(tp); 3306 3307 /* disable aspm and clock request before access ephy */ 3308 rtl_hw_aspm_clkreq_enable(tp, false); 3309 rtl_ephy_init(tp, e_info_8117); 3310 3311 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3312 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3313 3314 rtl_set_def_aspm_entry_latency(tp); 3315 3316 rtl_reset_packet_filter(tp); 3317 3318 rtl_eri_set_bits(tp, 0xd4, 0x0010); 3319 3320 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3321 3322 rtl_disable_rxdvgate(tp); 3323 3324 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3325 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3326 3327 rtl8168_config_eee_mac(tp); 3328 3329 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3330 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3331 3332 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3333 3334 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3335 3336 rtl_pcie_state_l2l3_disable(tp); 3337 3338 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3339 if (rg_saw_cnt > 0) { 3340 u16 sw_cnt_1ms_ini; 3341 3342 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; 3343 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3344 } 3345 3346 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3347 r8168_mac_ocp_write(tp, 0xea80, 0x0003); 3348 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); 3349 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3350 3351 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3352 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3353 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3354 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3355 3356 /* firmware is for MAC only */ 3357 r8169_apply_firmware(tp); 3358 3359 rtl_hw_aspm_clkreq_enable(tp, true); 3360 } 3361 3362 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 3363 { 3364 static const struct ephy_info e_info_8102e_1[] = { 3365 { 0x01, 0, 0x6e65 }, 3366 { 0x02, 0, 0x091f }, 3367 { 0x03, 0, 0xc2f9 }, 3368 { 0x06, 0, 0xafb5 }, 3369 { 0x07, 0, 0x0e00 }, 3370 { 0x19, 0, 0xec80 }, 3371 { 0x01, 0, 0x2e65 }, 3372 { 0x01, 0, 0x6e65 } 3373 }; 3374 u8 cfg1; 3375 3376 rtl_set_def_aspm_entry_latency(tp); 3377 3378 RTL_W8(tp, DBG_REG, FIX_NAK_1); 3379 3380 RTL_W8(tp, Config1, 3381 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 3382 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3383 3384 cfg1 = RTL_R8(tp, Config1); 3385 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 3386 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 3387 3388 rtl_ephy_init(tp, e_info_8102e_1); 3389 } 3390 3391 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 3392 { 3393 rtl_set_def_aspm_entry_latency(tp); 3394 3395 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 3396 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3397 } 3398 3399 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 3400 { 3401 rtl_hw_start_8102e_2(tp); 3402 3403 rtl_ephy_write(tp, 0x03, 0xc2f9); 3404 } 3405 3406 static void rtl_hw_start_8401(struct rtl8169_private *tp) 3407 { 3408 static const struct ephy_info e_info_8401[] = { 3409 { 0x01, 0xffff, 0x6fe5 }, 3410 { 0x03, 0xffff, 0x0599 }, 3411 { 0x06, 0xffff, 0xaf25 }, 3412 { 0x07, 0xffff, 0x8e68 }, 3413 }; 3414 3415 rtl_ephy_init(tp, e_info_8401); 3416 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3417 } 3418 3419 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 3420 { 3421 static const struct ephy_info e_info_8105e_1[] = { 3422 { 0x07, 0, 0x4000 }, 3423 { 0x19, 0, 0x0200 }, 3424 { 0x19, 0, 0x0020 }, 3425 { 0x1e, 0, 0x2000 }, 3426 { 0x03, 0, 0x0001 }, 3427 { 0x19, 0, 0x0100 }, 3428 { 0x19, 0, 0x0004 }, 3429 { 0x0a, 0, 0x0020 } 3430 }; 3431 3432 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3433 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3434 3435 /* Disable Early Tally Counter */ 3436 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 3437 3438 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3439 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3440 3441 rtl_ephy_init(tp, e_info_8105e_1); 3442 3443 rtl_pcie_state_l2l3_disable(tp); 3444 } 3445 3446 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 3447 { 3448 rtl_hw_start_8105e_1(tp); 3449 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 3450 } 3451 3452 static void rtl_hw_start_8402(struct rtl8169_private *tp) 3453 { 3454 static const struct ephy_info e_info_8402[] = { 3455 { 0x19, 0xffff, 0xff64 }, 3456 { 0x1e, 0, 0x4000 } 3457 }; 3458 3459 rtl_set_def_aspm_entry_latency(tp); 3460 3461 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3462 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3463 3464 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3465 3466 rtl_ephy_init(tp, e_info_8402); 3467 3468 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 3469 rtl_reset_packet_filter(tp); 3470 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3471 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3472 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00); 3473 3474 /* disable EEE */ 3475 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3476 3477 rtl_pcie_state_l2l3_disable(tp); 3478 } 3479 3480 static void rtl_hw_start_8106(struct rtl8169_private *tp) 3481 { 3482 rtl_hw_aspm_clkreq_enable(tp, false); 3483 3484 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3485 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3486 3487 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 3488 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3489 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3490 3491 /* L0 7us, L1 32us - needed to avoid issues with link-up detection */ 3492 rtl_set_aspm_entry_latency(tp, 0x2f); 3493 3494 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3495 3496 /* disable EEE */ 3497 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3498 3499 rtl_pcie_state_l2l3_disable(tp); 3500 rtl_hw_aspm_clkreq_enable(tp, true); 3501 } 3502 3503 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 3504 { 3505 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 3506 } 3507 3508 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 3509 { 3510 rtl_pcie_state_l2l3_disable(tp); 3511 3512 RTL_W16(tp, 0x382, 0x221b); 3513 RTL_W8(tp, 0x4500, 0); 3514 RTL_W16(tp, 0x4800, 0); 3515 3516 /* disable UPS */ 3517 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 3518 3519 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 3520 3521 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 3522 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 3523 3524 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 3525 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3526 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3527 3528 /* disable new tx descriptor format */ 3529 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 3530 3531 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3532 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); 3533 else 3534 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 3535 3536 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3537 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000); 3538 else 3539 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 3540 3541 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 3542 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 3543 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 3544 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 3545 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 3546 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); 3547 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 3548 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068); 3549 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 3550 3551 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3552 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 3553 udelay(1); 3554 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 3555 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 3556 3557 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 3558 3559 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 3560 3561 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3562 rtl8125b_config_eee_mac(tp); 3563 else 3564 rtl8125a_config_eee_mac(tp); 3565 3566 rtl_disable_rxdvgate(tp); 3567 } 3568 3569 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp) 3570 { 3571 static const struct ephy_info e_info_8125a_2[] = { 3572 { 0x04, 0xffff, 0xd000 }, 3573 { 0x0a, 0xffff, 0x8653 }, 3574 { 0x23, 0xffff, 0xab66 }, 3575 { 0x20, 0xffff, 0x9455 }, 3576 { 0x21, 0xffff, 0x99ff }, 3577 { 0x29, 0xffff, 0xfe04 }, 3578 3579 { 0x44, 0xffff, 0xd000 }, 3580 { 0x4a, 0xffff, 0x8653 }, 3581 { 0x63, 0xffff, 0xab66 }, 3582 { 0x60, 0xffff, 0x9455 }, 3583 { 0x61, 0xffff, 0x99ff }, 3584 { 0x69, 0xffff, 0xfe04 }, 3585 }; 3586 3587 rtl_set_def_aspm_entry_latency(tp); 3588 3589 /* disable aspm and clock request before access ephy */ 3590 rtl_hw_aspm_clkreq_enable(tp, false); 3591 rtl_ephy_init(tp, e_info_8125a_2); 3592 3593 rtl_hw_start_8125_common(tp); 3594 rtl_hw_aspm_clkreq_enable(tp, true); 3595 } 3596 3597 static void rtl_hw_start_8125b(struct rtl8169_private *tp) 3598 { 3599 static const struct ephy_info e_info_8125b[] = { 3600 { 0x0b, 0xffff, 0xa908 }, 3601 { 0x1e, 0xffff, 0x20eb }, 3602 { 0x4b, 0xffff, 0xa908 }, 3603 { 0x5e, 0xffff, 0x20eb }, 3604 { 0x22, 0x0030, 0x0020 }, 3605 { 0x62, 0x0030, 0x0020 }, 3606 }; 3607 3608 rtl_set_def_aspm_entry_latency(tp); 3609 rtl_hw_aspm_clkreq_enable(tp, false); 3610 3611 rtl_ephy_init(tp, e_info_8125b); 3612 rtl_hw_start_8125_common(tp); 3613 3614 rtl_hw_aspm_clkreq_enable(tp, true); 3615 } 3616 3617 static void rtl_hw_config(struct rtl8169_private *tp) 3618 { 3619 static const rtl_generic_fct hw_configs[] = { 3620 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 3621 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 3622 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 3623 [RTL_GIGA_MAC_VER_10] = NULL, 3624 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b, 3625 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401, 3626 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 3627 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 3628 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 3629 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 3630 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2, 3631 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 3632 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 3633 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 3634 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 3635 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 3636 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 3637 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 3638 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 3639 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 3640 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 3641 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 3642 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 3643 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 3644 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 3645 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 3646 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 3647 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 3648 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 3649 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 3650 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 3651 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 3652 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 3653 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 3654 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 3655 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, 3656 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117, 3657 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2, 3658 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, 3659 }; 3660 3661 if (hw_configs[tp->mac_version]) 3662 hw_configs[tp->mac_version](tp); 3663 } 3664 3665 static void rtl_hw_start_8125(struct rtl8169_private *tp) 3666 { 3667 int i; 3668 3669 /* disable interrupt coalescing */ 3670 for (i = 0xa00; i < 0xb00; i += 4) 3671 RTL_W32(tp, i, 0); 3672 3673 rtl_hw_config(tp); 3674 } 3675 3676 static void rtl_hw_start_8168(struct rtl8169_private *tp) 3677 { 3678 if (rtl_is_8168evl_up(tp)) 3679 RTL_W8(tp, MaxTxPacketSize, EarlySize); 3680 else 3681 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 3682 3683 rtl_hw_config(tp); 3684 3685 /* disable interrupt coalescing */ 3686 RTL_W16(tp, IntrMitigate, 0x0000); 3687 } 3688 3689 static void rtl_hw_start_8169(struct rtl8169_private *tp) 3690 { 3691 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 3692 3693 tp->cp_cmd |= PCIMulRW; 3694 3695 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 3696 tp->mac_version == RTL_GIGA_MAC_VER_03) 3697 tp->cp_cmd |= EnAnaPLL; 3698 3699 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3700 3701 rtl8169_set_magic_reg(tp); 3702 3703 /* disable interrupt coalescing */ 3704 RTL_W16(tp, IntrMitigate, 0x0000); 3705 } 3706 3707 static void rtl_hw_start(struct rtl8169_private *tp) 3708 { 3709 rtl_unlock_config_regs(tp); 3710 3711 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3712 3713 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 3714 rtl_hw_start_8169(tp); 3715 else if (rtl_is_8125(tp)) 3716 rtl_hw_start_8125(tp); 3717 else 3718 rtl_hw_start_8168(tp); 3719 3720 rtl_enable_exit_l1(tp); 3721 rtl_set_rx_max_size(tp); 3722 rtl_set_rx_tx_desc_registers(tp); 3723 rtl_lock_config_regs(tp); 3724 3725 rtl_jumbo_config(tp); 3726 3727 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 3728 rtl_pci_commit(tp); 3729 3730 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 3731 rtl_init_rxcfg(tp); 3732 rtl_set_tx_config_registers(tp); 3733 rtl_set_rx_config_features(tp, tp->dev->features); 3734 rtl_set_rx_mode(tp->dev); 3735 rtl_irq_enable(tp); 3736 } 3737 3738 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 3739 { 3740 struct rtl8169_private *tp = netdev_priv(dev); 3741 3742 dev->mtu = new_mtu; 3743 netdev_update_features(dev); 3744 rtl_jumbo_config(tp); 3745 3746 switch (tp->mac_version) { 3747 case RTL_GIGA_MAC_VER_61: 3748 case RTL_GIGA_MAC_VER_63: 3749 rtl8125_set_eee_txidle_timer(tp); 3750 break; 3751 default: 3752 break; 3753 } 3754 3755 return 0; 3756 } 3757 3758 static void rtl8169_mark_to_asic(struct RxDesc *desc) 3759 { 3760 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 3761 3762 desc->opts2 = 0; 3763 /* Force memory writes to complete before releasing descriptor */ 3764 dma_wmb(); 3765 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE)); 3766 } 3767 3768 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 3769 struct RxDesc *desc) 3770 { 3771 struct device *d = tp_to_dev(tp); 3772 int node = dev_to_node(d); 3773 dma_addr_t mapping; 3774 struct page *data; 3775 3776 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 3777 if (!data) 3778 return NULL; 3779 3780 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3781 if (unlikely(dma_mapping_error(d, mapping))) { 3782 netdev_err(tp->dev, "Failed to map RX DMA!\n"); 3783 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 3784 return NULL; 3785 } 3786 3787 desc->addr = cpu_to_le64(mapping); 3788 rtl8169_mark_to_asic(desc); 3789 3790 return data; 3791 } 3792 3793 static void rtl8169_rx_clear(struct rtl8169_private *tp) 3794 { 3795 int i; 3796 3797 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 3798 dma_unmap_page(tp_to_dev(tp), 3799 le64_to_cpu(tp->RxDescArray[i].addr), 3800 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3801 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 3802 tp->Rx_databuff[i] = NULL; 3803 tp->RxDescArray[i].addr = 0; 3804 tp->RxDescArray[i].opts1 = 0; 3805 } 3806 } 3807 3808 static int rtl8169_rx_fill(struct rtl8169_private *tp) 3809 { 3810 int i; 3811 3812 for (i = 0; i < NUM_RX_DESC; i++) { 3813 struct page *data; 3814 3815 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 3816 if (!data) { 3817 rtl8169_rx_clear(tp); 3818 return -ENOMEM; 3819 } 3820 tp->Rx_databuff[i] = data; 3821 } 3822 3823 /* mark as last descriptor in the ring */ 3824 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd); 3825 3826 return 0; 3827 } 3828 3829 static int rtl8169_init_ring(struct rtl8169_private *tp) 3830 { 3831 rtl8169_init_ring_indexes(tp); 3832 3833 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 3834 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 3835 3836 return rtl8169_rx_fill(tp); 3837 } 3838 3839 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry) 3840 { 3841 struct ring_info *tx_skb = tp->tx_skb + entry; 3842 struct TxDesc *desc = tp->TxDescArray + entry; 3843 3844 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len, 3845 DMA_TO_DEVICE); 3846 memset(desc, 0, sizeof(*desc)); 3847 memset(tx_skb, 0, sizeof(*tx_skb)); 3848 } 3849 3850 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 3851 unsigned int n) 3852 { 3853 unsigned int i; 3854 3855 for (i = 0; i < n; i++) { 3856 unsigned int entry = (start + i) % NUM_TX_DESC; 3857 struct ring_info *tx_skb = tp->tx_skb + entry; 3858 unsigned int len = tx_skb->len; 3859 3860 if (len) { 3861 struct sk_buff *skb = tx_skb->skb; 3862 3863 rtl8169_unmap_tx_skb(tp, entry); 3864 if (skb) 3865 dev_consume_skb_any(skb); 3866 } 3867 } 3868 } 3869 3870 static void rtl8169_tx_clear(struct rtl8169_private *tp) 3871 { 3872 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 3873 netdev_reset_queue(tp->dev); 3874 } 3875 3876 static void rtl8169_cleanup(struct rtl8169_private *tp) 3877 { 3878 napi_disable(&tp->napi); 3879 3880 /* Give a racing hard_start_xmit a few cycles to complete. */ 3881 synchronize_net(); 3882 3883 /* Disable interrupts */ 3884 rtl8169_irq_mask_and_ack(tp); 3885 3886 rtl_rx_close(tp); 3887 3888 switch (tp->mac_version) { 3889 case RTL_GIGA_MAC_VER_28: 3890 case RTL_GIGA_MAC_VER_31: 3891 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000); 3892 break; 3893 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 3894 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3895 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 3896 break; 3897 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 3898 rtl_enable_rxdvgate(tp); 3899 fsleep(2000); 3900 break; 3901 default: 3902 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3903 fsleep(100); 3904 break; 3905 } 3906 3907 rtl_hw_reset(tp); 3908 3909 rtl8169_tx_clear(tp); 3910 rtl8169_init_ring_indexes(tp); 3911 } 3912 3913 static void rtl_reset_work(struct rtl8169_private *tp) 3914 { 3915 int i; 3916 3917 netif_stop_queue(tp->dev); 3918 3919 rtl8169_cleanup(tp); 3920 3921 for (i = 0; i < NUM_RX_DESC; i++) 3922 rtl8169_mark_to_asic(tp->RxDescArray + i); 3923 3924 napi_enable(&tp->napi); 3925 rtl_hw_start(tp); 3926 } 3927 3928 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue) 3929 { 3930 struct rtl8169_private *tp = netdev_priv(dev); 3931 3932 rtl_schedule_task(tp, RTL_FLAG_TASK_TX_TIMEOUT); 3933 } 3934 3935 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len, 3936 void *addr, unsigned int entry, bool desc_own) 3937 { 3938 struct TxDesc *txd = tp->TxDescArray + entry; 3939 struct device *d = tp_to_dev(tp); 3940 dma_addr_t mapping; 3941 u32 opts1; 3942 int ret; 3943 3944 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 3945 ret = dma_mapping_error(d, mapping); 3946 if (unlikely(ret)) { 3947 if (net_ratelimit()) 3948 netdev_err(tp->dev, "Failed to map TX data!\n"); 3949 return ret; 3950 } 3951 3952 txd->addr = cpu_to_le64(mapping); 3953 txd->opts2 = cpu_to_le32(opts[1]); 3954 3955 opts1 = opts[0] | len; 3956 if (entry == NUM_TX_DESC - 1) 3957 opts1 |= RingEnd; 3958 if (desc_own) 3959 opts1 |= DescOwn; 3960 txd->opts1 = cpu_to_le32(opts1); 3961 3962 tp->tx_skb[entry].len = len; 3963 3964 return 0; 3965 } 3966 3967 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 3968 const u32 *opts, unsigned int entry) 3969 { 3970 struct skb_shared_info *info = skb_shinfo(skb); 3971 unsigned int cur_frag; 3972 3973 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 3974 const skb_frag_t *frag = info->frags + cur_frag; 3975 void *addr = skb_frag_address(frag); 3976 u32 len = skb_frag_size(frag); 3977 3978 entry = (entry + 1) % NUM_TX_DESC; 3979 3980 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true))) 3981 goto err_out; 3982 } 3983 3984 return 0; 3985 3986 err_out: 3987 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 3988 return -EIO; 3989 } 3990 3991 static bool rtl_skb_is_udp(struct sk_buff *skb) 3992 { 3993 int no = skb_network_offset(skb); 3994 struct ipv6hdr *i6h, _i6h; 3995 struct iphdr *ih, _ih; 3996 3997 switch (vlan_get_protocol(skb)) { 3998 case htons(ETH_P_IP): 3999 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih); 4000 return ih && ih->protocol == IPPROTO_UDP; 4001 case htons(ETH_P_IPV6): 4002 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h); 4003 return i6h && i6h->nexthdr == IPPROTO_UDP; 4004 default: 4005 return false; 4006 } 4007 } 4008 4009 #define RTL_MIN_PATCH_LEN 47 4010 4011 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */ 4012 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp, 4013 struct sk_buff *skb) 4014 { 4015 unsigned int padto = 0, len = skb->len; 4016 4017 if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN && 4018 rtl_skb_is_udp(skb) && skb_transport_header_was_set(skb)) { 4019 unsigned int trans_data_len = skb_tail_pointer(skb) - 4020 skb_transport_header(skb); 4021 4022 if (trans_data_len >= offsetof(struct udphdr, len) && 4023 trans_data_len < RTL_MIN_PATCH_LEN) { 4024 u16 dest = ntohs(udp_hdr(skb)->dest); 4025 4026 /* dest is a standard PTP port */ 4027 if (dest == 319 || dest == 320) 4028 padto = len + RTL_MIN_PATCH_LEN - trans_data_len; 4029 } 4030 4031 if (trans_data_len < sizeof(struct udphdr)) 4032 padto = max_t(unsigned int, padto, 4033 len + sizeof(struct udphdr) - trans_data_len); 4034 } 4035 4036 return padto; 4037 } 4038 4039 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp, 4040 struct sk_buff *skb) 4041 { 4042 unsigned int padto; 4043 4044 padto = rtl8125_quirk_udp_padto(tp, skb); 4045 4046 switch (tp->mac_version) { 4047 case RTL_GIGA_MAC_VER_34: 4048 case RTL_GIGA_MAC_VER_61: 4049 case RTL_GIGA_MAC_VER_63: 4050 padto = max_t(unsigned int, padto, ETH_ZLEN); 4051 break; 4052 default: 4053 break; 4054 } 4055 4056 return padto; 4057 } 4058 4059 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 4060 { 4061 u32 mss = skb_shinfo(skb)->gso_size; 4062 4063 if (mss) { 4064 opts[0] |= TD_LSO; 4065 opts[0] |= mss << TD0_MSS_SHIFT; 4066 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4067 const struct iphdr *ip = ip_hdr(skb); 4068 4069 if (ip->protocol == IPPROTO_TCP) 4070 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 4071 else if (ip->protocol == IPPROTO_UDP) 4072 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 4073 else 4074 WARN_ON_ONCE(1); 4075 } 4076 } 4077 4078 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 4079 struct sk_buff *skb, u32 *opts) 4080 { 4081 struct skb_shared_info *shinfo = skb_shinfo(skb); 4082 u32 mss = shinfo->gso_size; 4083 4084 if (mss) { 4085 if (shinfo->gso_type & SKB_GSO_TCPV4) { 4086 opts[0] |= TD1_GTSENV4; 4087 } else if (shinfo->gso_type & SKB_GSO_TCPV6) { 4088 if (skb_cow_head(skb, 0)) 4089 return false; 4090 4091 tcp_v6_gso_csum_prep(skb); 4092 opts[0] |= TD1_GTSENV6; 4093 } else { 4094 WARN_ON_ONCE(1); 4095 } 4096 4097 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT; 4098 opts[1] |= mss << TD1_MSS_SHIFT; 4099 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4100 u8 ip_protocol; 4101 4102 switch (vlan_get_protocol(skb)) { 4103 case htons(ETH_P_IP): 4104 opts[1] |= TD1_IPv4_CS; 4105 ip_protocol = ip_hdr(skb)->protocol; 4106 break; 4107 4108 case htons(ETH_P_IPV6): 4109 opts[1] |= TD1_IPv6_CS; 4110 ip_protocol = ipv6_hdr(skb)->nexthdr; 4111 break; 4112 4113 default: 4114 ip_protocol = IPPROTO_RAW; 4115 break; 4116 } 4117 4118 if (ip_protocol == IPPROTO_TCP) 4119 opts[1] |= TD1_TCP_CS; 4120 else if (ip_protocol == IPPROTO_UDP) 4121 opts[1] |= TD1_UDP_CS; 4122 else 4123 WARN_ON_ONCE(1); 4124 4125 opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT; 4126 } else { 4127 unsigned int padto = rtl_quirk_packet_padto(tp, skb); 4128 4129 /* skb_padto would free the skb on error */ 4130 return !__skb_put_padto(skb, padto, false); 4131 } 4132 4133 return true; 4134 } 4135 4136 static bool rtl_tx_slots_avail(struct rtl8169_private *tp) 4137 { 4138 unsigned int slots_avail = READ_ONCE(tp->dirty_tx) + NUM_TX_DESC 4139 - READ_ONCE(tp->cur_tx); 4140 4141 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */ 4142 return slots_avail > MAX_SKB_FRAGS; 4143 } 4144 4145 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 4146 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 4147 { 4148 switch (tp->mac_version) { 4149 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4150 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4151 return false; 4152 default: 4153 return true; 4154 } 4155 } 4156 4157 static void rtl8169_doorbell(struct rtl8169_private *tp) 4158 { 4159 if (rtl_is_8125(tp)) 4160 RTL_W16(tp, TxPoll_8125, BIT(0)); 4161 else 4162 RTL_W8(tp, TxPoll, NPQ); 4163 } 4164 4165 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 4166 struct net_device *dev) 4167 { 4168 unsigned int frags = skb_shinfo(skb)->nr_frags; 4169 struct rtl8169_private *tp = netdev_priv(dev); 4170 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 4171 struct TxDesc *txd_first, *txd_last; 4172 bool stop_queue, door_bell; 4173 u32 opts[2]; 4174 4175 if (unlikely(!rtl_tx_slots_avail(tp))) { 4176 if (net_ratelimit()) 4177 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 4178 goto err_stop_0; 4179 } 4180 4181 opts[1] = rtl8169_tx_vlan_tag(skb); 4182 opts[0] = 0; 4183 4184 if (!rtl_chip_supports_csum_v2(tp)) 4185 rtl8169_tso_csum_v1(skb, opts); 4186 else if (!rtl8169_tso_csum_v2(tp, skb, opts)) 4187 goto err_dma_0; 4188 4189 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data, 4190 entry, false))) 4191 goto err_dma_0; 4192 4193 txd_first = tp->TxDescArray + entry; 4194 4195 if (frags) { 4196 if (rtl8169_xmit_frags(tp, skb, opts, entry)) 4197 goto err_dma_1; 4198 entry = (entry + frags) % NUM_TX_DESC; 4199 } 4200 4201 txd_last = tp->TxDescArray + entry; 4202 txd_last->opts1 |= cpu_to_le32(LastFrag); 4203 tp->tx_skb[entry].skb = skb; 4204 4205 skb_tx_timestamp(skb); 4206 4207 /* Force memory writes to complete before releasing descriptor */ 4208 dma_wmb(); 4209 4210 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 4211 4212 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag); 4213 4214 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */ 4215 smp_wmb(); 4216 4217 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1); 4218 4219 stop_queue = !rtl_tx_slots_avail(tp); 4220 if (unlikely(stop_queue)) { 4221 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must 4222 * not miss a ring update when it notices a stopped queue. 4223 */ 4224 smp_wmb(); 4225 netif_stop_queue(dev); 4226 /* Sync with rtl_tx: 4227 * - publish queue status and cur_tx ring index (write barrier) 4228 * - refresh dirty_tx ring index (read barrier). 4229 * May the current thread have a pessimistic view of the ring 4230 * status and forget to wake up queue, a racing rtl_tx thread 4231 * can't. 4232 */ 4233 smp_mb__after_atomic(); 4234 if (rtl_tx_slots_avail(tp)) 4235 netif_start_queue(dev); 4236 door_bell = true; 4237 } 4238 4239 if (door_bell) 4240 rtl8169_doorbell(tp); 4241 4242 return NETDEV_TX_OK; 4243 4244 err_dma_1: 4245 rtl8169_unmap_tx_skb(tp, entry); 4246 err_dma_0: 4247 dev_kfree_skb_any(skb); 4248 dev->stats.tx_dropped++; 4249 return NETDEV_TX_OK; 4250 4251 err_stop_0: 4252 netif_stop_queue(dev); 4253 dev->stats.tx_dropped++; 4254 return NETDEV_TX_BUSY; 4255 } 4256 4257 static unsigned int rtl_last_frag_len(struct sk_buff *skb) 4258 { 4259 struct skb_shared_info *info = skb_shinfo(skb); 4260 unsigned int nr_frags = info->nr_frags; 4261 4262 if (!nr_frags) 4263 return UINT_MAX; 4264 4265 return skb_frag_size(info->frags + nr_frags - 1); 4266 } 4267 4268 /* Workaround for hw issues with TSO on RTL8168evl */ 4269 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb, 4270 netdev_features_t features) 4271 { 4272 /* IPv4 header has options field */ 4273 if (vlan_get_protocol(skb) == htons(ETH_P_IP) && 4274 ip_hdrlen(skb) > sizeof(struct iphdr)) 4275 features &= ~NETIF_F_ALL_TSO; 4276 4277 /* IPv4 TCP header has options field */ 4278 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 && 4279 tcp_hdrlen(skb) > sizeof(struct tcphdr)) 4280 features &= ~NETIF_F_ALL_TSO; 4281 4282 else if (rtl_last_frag_len(skb) <= 6) 4283 features &= ~NETIF_F_ALL_TSO; 4284 4285 return features; 4286 } 4287 4288 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 4289 struct net_device *dev, 4290 netdev_features_t features) 4291 { 4292 struct rtl8169_private *tp = netdev_priv(dev); 4293 4294 if (skb_is_gso(skb)) { 4295 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 4296 features = rtl8168evl_fix_tso(skb, features); 4297 4298 if (skb_transport_offset(skb) > GTTCPHO_MAX && 4299 rtl_chip_supports_csum_v2(tp)) 4300 features &= ~NETIF_F_ALL_TSO; 4301 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4302 /* work around hw bug on some chip versions */ 4303 if (skb->len < ETH_ZLEN) 4304 features &= ~NETIF_F_CSUM_MASK; 4305 4306 if (rtl_quirk_packet_padto(tp, skb)) 4307 features &= ~NETIF_F_CSUM_MASK; 4308 4309 if (skb_transport_offset(skb) > TCPHO_MAX && 4310 rtl_chip_supports_csum_v2(tp)) 4311 features &= ~NETIF_F_CSUM_MASK; 4312 } 4313 4314 return vlan_features_check(skb, features); 4315 } 4316 4317 static void rtl8169_pcierr_interrupt(struct net_device *dev) 4318 { 4319 struct rtl8169_private *tp = netdev_priv(dev); 4320 struct pci_dev *pdev = tp->pci_dev; 4321 int pci_status_errs; 4322 u16 pci_cmd; 4323 4324 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4325 4326 pci_status_errs = pci_status_get_and_clear_errors(pdev); 4327 4328 if (net_ratelimit()) 4329 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", 4330 pci_cmd, pci_status_errs); 4331 4332 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4333 } 4334 4335 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 4336 int budget) 4337 { 4338 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0; 4339 struct sk_buff *skb; 4340 4341 dirty_tx = tp->dirty_tx; 4342 4343 while (READ_ONCE(tp->cur_tx) != dirty_tx) { 4344 unsigned int entry = dirty_tx % NUM_TX_DESC; 4345 u32 status; 4346 4347 status = le32_to_cpu(tp->TxDescArray[entry].opts1); 4348 if (status & DescOwn) 4349 break; 4350 4351 skb = tp->tx_skb[entry].skb; 4352 rtl8169_unmap_tx_skb(tp, entry); 4353 4354 if (skb) { 4355 pkts_compl++; 4356 bytes_compl += skb->len; 4357 napi_consume_skb(skb, budget); 4358 } 4359 dirty_tx++; 4360 } 4361 4362 if (tp->dirty_tx != dirty_tx) { 4363 netdev_completed_queue(dev, pkts_compl, bytes_compl); 4364 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl); 4365 4366 /* Sync with rtl8169_start_xmit: 4367 * - publish dirty_tx ring index (write barrier) 4368 * - refresh cur_tx ring index and queue status (read barrier) 4369 * May the current thread miss the stopped queue condition, 4370 * a racing xmit thread can only have a right view of the 4371 * ring status. 4372 */ 4373 smp_store_mb(tp->dirty_tx, dirty_tx); 4374 if (netif_queue_stopped(dev) && rtl_tx_slots_avail(tp)) 4375 netif_wake_queue(dev); 4376 /* 4377 * 8168 hack: TxPoll requests are lost when the Tx packets are 4378 * too close. Let's kick an extra TxPoll request when a burst 4379 * of start_xmit activity is detected (if it is not detected, 4380 * it is slow enough). -- FR 4381 * If skb is NULL then we come here again once a tx irq is 4382 * triggered after the last fragment is marked transmitted. 4383 */ 4384 if (tp->cur_tx != dirty_tx && skb) 4385 rtl8169_doorbell(tp); 4386 } 4387 } 4388 4389 static inline int rtl8169_fragmented_frame(u32 status) 4390 { 4391 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 4392 } 4393 4394 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 4395 { 4396 u32 status = opts1 & (RxProtoMask | RxCSFailMask); 4397 4398 if (status == RxProtoTCP || status == RxProtoUDP) 4399 skb->ip_summed = CHECKSUM_UNNECESSARY; 4400 else 4401 skb_checksum_none_assert(skb); 4402 } 4403 4404 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget) 4405 { 4406 struct device *d = tp_to_dev(tp); 4407 int count; 4408 4409 for (count = 0; count < budget; count++, tp->cur_rx++) { 4410 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC; 4411 struct RxDesc *desc = tp->RxDescArray + entry; 4412 struct sk_buff *skb; 4413 const void *rx_buf; 4414 dma_addr_t addr; 4415 u32 status; 4416 4417 status = le32_to_cpu(desc->opts1); 4418 if (status & DescOwn) 4419 break; 4420 4421 /* This barrier is needed to keep us from reading 4422 * any other fields out of the Rx descriptor until 4423 * we know the status of DescOwn 4424 */ 4425 dma_rmb(); 4426 4427 if (unlikely(status & RxRES)) { 4428 if (net_ratelimit()) 4429 netdev_warn(dev, "Rx ERROR. status = %08x\n", 4430 status); 4431 dev->stats.rx_errors++; 4432 if (status & (RxRWT | RxRUNT)) 4433 dev->stats.rx_length_errors++; 4434 if (status & RxCRC) 4435 dev->stats.rx_crc_errors++; 4436 4437 if (!(dev->features & NETIF_F_RXALL)) 4438 goto release_descriptor; 4439 else if (status & RxRWT || !(status & (RxRUNT | RxCRC))) 4440 goto release_descriptor; 4441 } 4442 4443 pkt_size = status & GENMASK(13, 0); 4444 if (likely(!(dev->features & NETIF_F_RXFCS))) 4445 pkt_size -= ETH_FCS_LEN; 4446 4447 /* The driver does not support incoming fragmented frames. 4448 * They are seen as a symptom of over-mtu sized frames. 4449 */ 4450 if (unlikely(rtl8169_fragmented_frame(status))) { 4451 dev->stats.rx_dropped++; 4452 dev->stats.rx_length_errors++; 4453 goto release_descriptor; 4454 } 4455 4456 skb = napi_alloc_skb(&tp->napi, pkt_size); 4457 if (unlikely(!skb)) { 4458 dev->stats.rx_dropped++; 4459 goto release_descriptor; 4460 } 4461 4462 addr = le64_to_cpu(desc->addr); 4463 rx_buf = page_address(tp->Rx_databuff[entry]); 4464 4465 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); 4466 prefetch(rx_buf); 4467 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 4468 skb->tail += pkt_size; 4469 skb->len = pkt_size; 4470 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); 4471 4472 rtl8169_rx_csum(skb, status); 4473 skb->protocol = eth_type_trans(skb, dev); 4474 4475 rtl8169_rx_vlan_tag(desc, skb); 4476 4477 if (skb->pkt_type == PACKET_MULTICAST) 4478 dev->stats.multicast++; 4479 4480 napi_gro_receive(&tp->napi, skb); 4481 4482 dev_sw_netstats_rx_add(dev, pkt_size); 4483 release_descriptor: 4484 rtl8169_mark_to_asic(desc); 4485 } 4486 4487 return count; 4488 } 4489 4490 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 4491 { 4492 struct rtl8169_private *tp = dev_instance; 4493 u32 status = rtl_get_events(tp); 4494 4495 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask)) 4496 return IRQ_NONE; 4497 4498 if (unlikely(status & SYSErr)) { 4499 rtl8169_pcierr_interrupt(tp->dev); 4500 goto out; 4501 } 4502 4503 if (status & LinkChg) 4504 phy_mac_interrupt(tp->phydev); 4505 4506 if (unlikely(status & RxFIFOOver && 4507 tp->mac_version == RTL_GIGA_MAC_VER_11)) { 4508 netif_stop_queue(tp->dev); 4509 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4510 } 4511 4512 if (napi_schedule_prep(&tp->napi)) { 4513 rtl_irq_disable(tp); 4514 __napi_schedule(&tp->napi); 4515 } 4516 out: 4517 rtl_ack_events(tp, status); 4518 4519 return IRQ_HANDLED; 4520 } 4521 4522 static void rtl_task(struct work_struct *work) 4523 { 4524 struct rtl8169_private *tp = 4525 container_of(work, struct rtl8169_private, wk.work); 4526 int ret; 4527 4528 rtnl_lock(); 4529 4530 if (!netif_running(tp->dev) || 4531 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 4532 goto out_unlock; 4533 4534 if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) { 4535 /* if chip isn't accessible, reset bus to revive it */ 4536 if (RTL_R32(tp, TxConfig) == ~0) { 4537 ret = pci_reset_bus(tp->pci_dev); 4538 if (ret < 0) { 4539 netdev_err(tp->dev, "Can't reset secondary PCI bus, detach NIC\n"); 4540 netif_device_detach(tp->dev); 4541 goto out_unlock; 4542 } 4543 } 4544 4545 /* ASPM compatibility issues are a typical reason for tx timeouts */ 4546 ret = pci_disable_link_state(tp->pci_dev, PCIE_LINK_STATE_L1 | 4547 PCIE_LINK_STATE_L0S); 4548 if (!ret) 4549 netdev_warn_once(tp->dev, "ASPM disabled on Tx timeout\n"); 4550 goto reset; 4551 } 4552 4553 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) { 4554 reset: 4555 rtl_reset_work(tp); 4556 netif_wake_queue(tp->dev); 4557 } 4558 out_unlock: 4559 rtnl_unlock(); 4560 } 4561 4562 static int rtl8169_poll(struct napi_struct *napi, int budget) 4563 { 4564 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 4565 struct net_device *dev = tp->dev; 4566 int work_done; 4567 4568 rtl_tx(dev, tp, budget); 4569 4570 work_done = rtl_rx(dev, tp, budget); 4571 4572 if (work_done < budget && napi_complete_done(napi, work_done)) 4573 rtl_irq_enable(tp); 4574 4575 return work_done; 4576 } 4577 4578 static void r8169_phylink_handler(struct net_device *ndev) 4579 { 4580 struct rtl8169_private *tp = netdev_priv(ndev); 4581 struct device *d = tp_to_dev(tp); 4582 4583 if (netif_carrier_ok(ndev)) { 4584 rtl_link_chg_patch(tp); 4585 pm_request_resume(d); 4586 } else { 4587 pm_runtime_idle(d); 4588 } 4589 4590 phy_print_status(tp->phydev); 4591 } 4592 4593 static int r8169_phy_connect(struct rtl8169_private *tp) 4594 { 4595 struct phy_device *phydev = tp->phydev; 4596 phy_interface_t phy_mode; 4597 int ret; 4598 4599 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 4600 PHY_INTERFACE_MODE_MII; 4601 4602 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 4603 phy_mode); 4604 if (ret) 4605 return ret; 4606 4607 if (!tp->supports_gmii) 4608 phy_set_max_speed(phydev, SPEED_100); 4609 4610 phy_attached_info(phydev); 4611 4612 return 0; 4613 } 4614 4615 static void rtl8169_down(struct rtl8169_private *tp) 4616 { 4617 /* Clear all task flags */ 4618 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4619 4620 phy_stop(tp->phydev); 4621 4622 rtl8169_update_counters(tp); 4623 4624 pci_clear_master(tp->pci_dev); 4625 rtl_pci_commit(tp); 4626 4627 rtl8169_cleanup(tp); 4628 rtl_disable_exit_l1(tp); 4629 rtl_prepare_power_down(tp); 4630 } 4631 4632 static void rtl8169_up(struct rtl8169_private *tp) 4633 { 4634 pci_set_master(tp->pci_dev); 4635 phy_init_hw(tp->phydev); 4636 phy_resume(tp->phydev); 4637 rtl8169_init_phy(tp); 4638 napi_enable(&tp->napi); 4639 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 4640 rtl_reset_work(tp); 4641 4642 phy_start(tp->phydev); 4643 } 4644 4645 static int rtl8169_close(struct net_device *dev) 4646 { 4647 struct rtl8169_private *tp = netdev_priv(dev); 4648 struct pci_dev *pdev = tp->pci_dev; 4649 4650 pm_runtime_get_sync(&pdev->dev); 4651 4652 netif_stop_queue(dev); 4653 rtl8169_down(tp); 4654 rtl8169_rx_clear(tp); 4655 4656 cancel_work_sync(&tp->wk.work); 4657 4658 free_irq(tp->irq, tp); 4659 4660 phy_disconnect(tp->phydev); 4661 4662 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4663 tp->RxPhyAddr); 4664 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4665 tp->TxPhyAddr); 4666 tp->TxDescArray = NULL; 4667 tp->RxDescArray = NULL; 4668 4669 pm_runtime_put_sync(&pdev->dev); 4670 4671 return 0; 4672 } 4673 4674 #ifdef CONFIG_NET_POLL_CONTROLLER 4675 static void rtl8169_netpoll(struct net_device *dev) 4676 { 4677 struct rtl8169_private *tp = netdev_priv(dev); 4678 4679 rtl8169_interrupt(tp->irq, tp); 4680 } 4681 #endif 4682 4683 static int rtl_open(struct net_device *dev) 4684 { 4685 struct rtl8169_private *tp = netdev_priv(dev); 4686 struct pci_dev *pdev = tp->pci_dev; 4687 unsigned long irqflags; 4688 int retval = -ENOMEM; 4689 4690 pm_runtime_get_sync(&pdev->dev); 4691 4692 /* 4693 * Rx and Tx descriptors needs 256 bytes alignment. 4694 * dma_alloc_coherent provides more. 4695 */ 4696 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 4697 &tp->TxPhyAddr, GFP_KERNEL); 4698 if (!tp->TxDescArray) 4699 goto out; 4700 4701 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 4702 &tp->RxPhyAddr, GFP_KERNEL); 4703 if (!tp->RxDescArray) 4704 goto err_free_tx_0; 4705 4706 retval = rtl8169_init_ring(tp); 4707 if (retval < 0) 4708 goto err_free_rx_1; 4709 4710 rtl_request_firmware(tp); 4711 4712 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED; 4713 retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp); 4714 if (retval < 0) 4715 goto err_release_fw_2; 4716 4717 retval = r8169_phy_connect(tp); 4718 if (retval) 4719 goto err_free_irq; 4720 4721 rtl8169_up(tp); 4722 rtl8169_init_counter_offsets(tp); 4723 netif_start_queue(dev); 4724 out: 4725 pm_runtime_put_sync(&pdev->dev); 4726 4727 return retval; 4728 4729 err_free_irq: 4730 free_irq(tp->irq, tp); 4731 err_release_fw_2: 4732 rtl_release_firmware(tp); 4733 rtl8169_rx_clear(tp); 4734 err_free_rx_1: 4735 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4736 tp->RxPhyAddr); 4737 tp->RxDescArray = NULL; 4738 err_free_tx_0: 4739 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4740 tp->TxPhyAddr); 4741 tp->TxDescArray = NULL; 4742 goto out; 4743 } 4744 4745 static void 4746 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 4747 { 4748 struct rtl8169_private *tp = netdev_priv(dev); 4749 struct pci_dev *pdev = tp->pci_dev; 4750 struct rtl8169_counters *counters = tp->counters; 4751 4752 pm_runtime_get_noresume(&pdev->dev); 4753 4754 netdev_stats_to_stats64(stats, &dev->stats); 4755 dev_fetch_sw_netstats(stats, dev->tstats); 4756 4757 /* 4758 * Fetch additional counter values missing in stats collected by driver 4759 * from tally counters. 4760 */ 4761 if (pm_runtime_active(&pdev->dev)) 4762 rtl8169_update_counters(tp); 4763 4764 /* 4765 * Subtract values fetched during initalization. 4766 * See rtl8169_init_counter_offsets for a description why we do that. 4767 */ 4768 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 4769 le64_to_cpu(tp->tc_offset.tx_errors); 4770 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 4771 le32_to_cpu(tp->tc_offset.tx_multi_collision); 4772 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 4773 le16_to_cpu(tp->tc_offset.tx_aborted); 4774 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) - 4775 le16_to_cpu(tp->tc_offset.rx_missed); 4776 4777 pm_runtime_put_noidle(&pdev->dev); 4778 } 4779 4780 static void rtl8169_net_suspend(struct rtl8169_private *tp) 4781 { 4782 netif_device_detach(tp->dev); 4783 4784 if (netif_running(tp->dev)) 4785 rtl8169_down(tp); 4786 } 4787 4788 static int rtl8169_runtime_resume(struct device *dev) 4789 { 4790 struct rtl8169_private *tp = dev_get_drvdata(dev); 4791 4792 rtl_rar_set(tp, tp->dev->dev_addr); 4793 __rtl8169_set_wol(tp, tp->saved_wolopts); 4794 4795 if (tp->TxDescArray) 4796 rtl8169_up(tp); 4797 4798 netif_device_attach(tp->dev); 4799 4800 return 0; 4801 } 4802 4803 static int rtl8169_suspend(struct device *device) 4804 { 4805 struct rtl8169_private *tp = dev_get_drvdata(device); 4806 4807 rtnl_lock(); 4808 rtl8169_net_suspend(tp); 4809 if (!device_may_wakeup(tp_to_dev(tp))) 4810 clk_disable_unprepare(tp->clk); 4811 rtnl_unlock(); 4812 4813 return 0; 4814 } 4815 4816 static int rtl8169_resume(struct device *device) 4817 { 4818 struct rtl8169_private *tp = dev_get_drvdata(device); 4819 4820 if (!device_may_wakeup(tp_to_dev(tp))) 4821 clk_prepare_enable(tp->clk); 4822 4823 /* Reportedly at least Asus X453MA truncates packets otherwise */ 4824 if (tp->mac_version == RTL_GIGA_MAC_VER_37) 4825 rtl_init_rxcfg(tp); 4826 4827 return rtl8169_runtime_resume(device); 4828 } 4829 4830 static int rtl8169_runtime_suspend(struct device *device) 4831 { 4832 struct rtl8169_private *tp = dev_get_drvdata(device); 4833 4834 if (!tp->TxDescArray) { 4835 netif_device_detach(tp->dev); 4836 return 0; 4837 } 4838 4839 rtnl_lock(); 4840 __rtl8169_set_wol(tp, WAKE_PHY); 4841 rtl8169_net_suspend(tp); 4842 rtnl_unlock(); 4843 4844 return 0; 4845 } 4846 4847 static int rtl8169_runtime_idle(struct device *device) 4848 { 4849 struct rtl8169_private *tp = dev_get_drvdata(device); 4850 4851 if (tp->dash_type != RTL_DASH_NONE) 4852 return -EBUSY; 4853 4854 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev)) 4855 pm_schedule_suspend(device, 10000); 4856 4857 return -EBUSY; 4858 } 4859 4860 static const struct dev_pm_ops rtl8169_pm_ops = { 4861 SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume) 4862 RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume, 4863 rtl8169_runtime_idle) 4864 }; 4865 4866 static void rtl_shutdown(struct pci_dev *pdev) 4867 { 4868 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4869 4870 rtnl_lock(); 4871 rtl8169_net_suspend(tp); 4872 rtnl_unlock(); 4873 4874 /* Restore original MAC address */ 4875 rtl_rar_set(tp, tp->dev->perm_addr); 4876 4877 if (system_state == SYSTEM_POWER_OFF && 4878 tp->dash_type == RTL_DASH_NONE) { 4879 pci_wake_from_d3(pdev, tp->saved_wolopts); 4880 pci_set_power_state(pdev, PCI_D3hot); 4881 } 4882 } 4883 4884 static void rtl_remove_one(struct pci_dev *pdev) 4885 { 4886 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4887 4888 if (pci_dev_run_wake(pdev)) 4889 pm_runtime_get_noresume(&pdev->dev); 4890 4891 unregister_netdev(tp->dev); 4892 4893 if (tp->dash_type != RTL_DASH_NONE) 4894 rtl8168_driver_stop(tp); 4895 4896 rtl_release_firmware(tp); 4897 4898 /* restore original MAC address */ 4899 rtl_rar_set(tp, tp->dev->perm_addr); 4900 } 4901 4902 static const struct net_device_ops rtl_netdev_ops = { 4903 .ndo_open = rtl_open, 4904 .ndo_stop = rtl8169_close, 4905 .ndo_get_stats64 = rtl8169_get_stats64, 4906 .ndo_start_xmit = rtl8169_start_xmit, 4907 .ndo_features_check = rtl8169_features_check, 4908 .ndo_tx_timeout = rtl8169_tx_timeout, 4909 .ndo_validate_addr = eth_validate_addr, 4910 .ndo_change_mtu = rtl8169_change_mtu, 4911 .ndo_fix_features = rtl8169_fix_features, 4912 .ndo_set_features = rtl8169_set_features, 4913 .ndo_set_mac_address = rtl_set_mac_address, 4914 .ndo_eth_ioctl = phy_do_ioctl_running, 4915 .ndo_set_rx_mode = rtl_set_rx_mode, 4916 #ifdef CONFIG_NET_POLL_CONTROLLER 4917 .ndo_poll_controller = rtl8169_netpoll, 4918 #endif 4919 4920 }; 4921 4922 static void rtl_set_irq_mask(struct rtl8169_private *tp) 4923 { 4924 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg; 4925 4926 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 4927 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver; 4928 else if (tp->mac_version == RTL_GIGA_MAC_VER_11) 4929 /* special workaround needed */ 4930 tp->irq_mask |= RxFIFOOver; 4931 else 4932 tp->irq_mask |= RxOverflow; 4933 } 4934 4935 static int rtl_alloc_irq(struct rtl8169_private *tp) 4936 { 4937 unsigned int flags; 4938 4939 switch (tp->mac_version) { 4940 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4941 rtl_unlock_config_regs(tp); 4942 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 4943 rtl_lock_config_regs(tp); 4944 fallthrough; 4945 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17: 4946 flags = PCI_IRQ_LEGACY; 4947 break; 4948 default: 4949 flags = PCI_IRQ_ALL_TYPES; 4950 break; 4951 } 4952 4953 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 4954 } 4955 4956 static void rtl_read_mac_address(struct rtl8169_private *tp, 4957 u8 mac_addr[ETH_ALEN]) 4958 { 4959 /* Get MAC address */ 4960 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 4961 u32 value; 4962 4963 value = rtl_eri_read(tp, 0xe0); 4964 put_unaligned_le32(value, mac_addr); 4965 value = rtl_eri_read(tp, 0xe4); 4966 put_unaligned_le16(value, mac_addr + 4); 4967 } else if (rtl_is_8125(tp)) { 4968 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 4969 } 4970 } 4971 4972 DECLARE_RTL_COND(rtl_link_list_ready_cond) 4973 { 4974 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 4975 } 4976 4977 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp) 4978 { 4979 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 4980 } 4981 4982 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 4983 { 4984 struct rtl8169_private *tp = mii_bus->priv; 4985 4986 if (phyaddr > 0) 4987 return -ENODEV; 4988 4989 return rtl_readphy(tp, phyreg); 4990 } 4991 4992 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 4993 int phyreg, u16 val) 4994 { 4995 struct rtl8169_private *tp = mii_bus->priv; 4996 4997 if (phyaddr > 0) 4998 return -ENODEV; 4999 5000 rtl_writephy(tp, phyreg, val); 5001 5002 return 0; 5003 } 5004 5005 static int r8169_mdio_register(struct rtl8169_private *tp) 5006 { 5007 struct pci_dev *pdev = tp->pci_dev; 5008 struct mii_bus *new_bus; 5009 int ret; 5010 5011 new_bus = devm_mdiobus_alloc(&pdev->dev); 5012 if (!new_bus) 5013 return -ENOMEM; 5014 5015 new_bus->name = "r8169"; 5016 new_bus->priv = tp; 5017 new_bus->parent = &pdev->dev; 5018 new_bus->irq[0] = PHY_MAC_INTERRUPT; 5019 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x", 5020 pci_domain_nr(pdev->bus), pci_dev_id(pdev)); 5021 5022 new_bus->read = r8169_mdio_read_reg; 5023 new_bus->write = r8169_mdio_write_reg; 5024 5025 ret = devm_mdiobus_register(&pdev->dev, new_bus); 5026 if (ret) 5027 return ret; 5028 5029 tp->phydev = mdiobus_get_phy(new_bus, 0); 5030 if (!tp->phydev) { 5031 return -ENODEV; 5032 } else if (!tp->phydev->drv) { 5033 /* Most chip versions fail with the genphy driver. 5034 * Therefore ensure that the dedicated PHY driver is loaded. 5035 */ 5036 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n", 5037 tp->phydev->phy_id); 5038 return -EUNATCH; 5039 } 5040 5041 tp->phydev->mac_managed_pm = true; 5042 5043 phy_support_asym_pause(tp->phydev); 5044 5045 /* PHY will be woken up in rtl_open() */ 5046 phy_suspend(tp->phydev); 5047 5048 return 0; 5049 } 5050 5051 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 5052 { 5053 rtl_enable_rxdvgate(tp); 5054 5055 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5056 msleep(1); 5057 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5058 5059 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5060 r8168g_wait_ll_share_fifo_ready(tp); 5061 5062 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 5063 r8168g_wait_ll_share_fifo_ready(tp); 5064 } 5065 5066 static void rtl_hw_init_8125(struct rtl8169_private *tp) 5067 { 5068 rtl_enable_rxdvgate(tp); 5069 5070 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5071 msleep(1); 5072 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5073 5074 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5075 r8168g_wait_ll_share_fifo_ready(tp); 5076 5077 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 5078 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 5079 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 5080 r8168g_wait_ll_share_fifo_ready(tp); 5081 } 5082 5083 static void rtl_hw_initialize(struct rtl8169_private *tp) 5084 { 5085 switch (tp->mac_version) { 5086 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 5087 rtl8168ep_stop_cmac(tp); 5088 fallthrough; 5089 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 5090 rtl_hw_init_8168g(tp); 5091 break; 5092 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 5093 rtl_hw_init_8125(tp); 5094 break; 5095 default: 5096 break; 5097 } 5098 } 5099 5100 static int rtl_jumbo_max(struct rtl8169_private *tp) 5101 { 5102 /* Non-GBit versions don't support jumbo frames */ 5103 if (!tp->supports_gmii) 5104 return 0; 5105 5106 switch (tp->mac_version) { 5107 /* RTL8169 */ 5108 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5109 return JUMBO_7K; 5110 /* RTL8168b */ 5111 case RTL_GIGA_MAC_VER_11: 5112 case RTL_GIGA_MAC_VER_17: 5113 return JUMBO_4K; 5114 /* RTL8168c */ 5115 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 5116 return JUMBO_6K; 5117 default: 5118 return JUMBO_9K; 5119 } 5120 } 5121 5122 static void rtl_init_mac_address(struct rtl8169_private *tp) 5123 { 5124 u8 mac_addr[ETH_ALEN] __aligned(2) = {}; 5125 struct net_device *dev = tp->dev; 5126 int rc; 5127 5128 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 5129 if (!rc) 5130 goto done; 5131 5132 rtl_read_mac_address(tp, mac_addr); 5133 if (is_valid_ether_addr(mac_addr)) 5134 goto done; 5135 5136 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 5137 if (is_valid_ether_addr(mac_addr)) 5138 goto done; 5139 5140 eth_random_addr(mac_addr); 5141 dev->addr_assign_type = NET_ADDR_RANDOM; 5142 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 5143 done: 5144 eth_hw_addr_set(dev, mac_addr); 5145 rtl_rar_set(tp, mac_addr); 5146 } 5147 5148 /* register is set if system vendor successfully tested ASPM 1.2 */ 5149 static bool rtl_aspm_is_safe(struct rtl8169_private *tp) 5150 { 5151 if (tp->mac_version >= RTL_GIGA_MAC_VER_61 && 5152 r8168_mac_ocp_read(tp, 0xc0b2) & 0xf) 5153 return true; 5154 5155 return false; 5156 } 5157 5158 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5159 { 5160 struct rtl8169_private *tp; 5161 int jumbo_max, region, rc; 5162 enum mac_version chipset; 5163 struct net_device *dev; 5164 u16 xid; 5165 5166 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 5167 if (!dev) 5168 return -ENOMEM; 5169 5170 SET_NETDEV_DEV(dev, &pdev->dev); 5171 dev->netdev_ops = &rtl_netdev_ops; 5172 tp = netdev_priv(dev); 5173 tp->dev = dev; 5174 tp->pci_dev = pdev; 5175 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 5176 tp->eee_adv = -1; 5177 tp->ocp_base = OCP_STD_PHY_BASE; 5178 5179 dev->tstats = devm_netdev_alloc_pcpu_stats(&pdev->dev, 5180 struct pcpu_sw_netstats); 5181 if (!dev->tstats) 5182 return -ENOMEM; 5183 5184 /* Get the *optional* external "ether_clk" used on some boards */ 5185 tp->clk = devm_clk_get_optional_enabled(&pdev->dev, "ether_clk"); 5186 if (IS_ERR(tp->clk)) 5187 return dev_err_probe(&pdev->dev, PTR_ERR(tp->clk), "failed to get ether_clk\n"); 5188 5189 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 5190 rc = pcim_enable_device(pdev); 5191 if (rc < 0) { 5192 dev_err(&pdev->dev, "enable failure\n"); 5193 return rc; 5194 } 5195 5196 if (pcim_set_mwi(pdev) < 0) 5197 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 5198 5199 /* use first MMIO region */ 5200 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 5201 if (region < 0) { 5202 dev_err(&pdev->dev, "no MMIO resource found\n"); 5203 return -ENODEV; 5204 } 5205 5206 rc = pcim_iomap_regions(pdev, BIT(region), KBUILD_MODNAME); 5207 if (rc < 0) { 5208 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n"); 5209 return rc; 5210 } 5211 5212 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 5213 5214 xid = (RTL_R32(tp, TxConfig) >> 20) & 0xfcf; 5215 5216 /* Identify chip attached to board */ 5217 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii); 5218 if (chipset == RTL_GIGA_MAC_NONE) { 5219 dev_err(&pdev->dev, "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n", xid); 5220 return -ENODEV; 5221 } 5222 5223 tp->mac_version = chipset; 5224 5225 /* Disable ASPM L1 as that cause random device stop working 5226 * problems as well as full system hangs for some PCIe devices users. 5227 * Chips from RTL8168h partially have issues with L1.2, but seem 5228 * to work fine with L1 and L1.1. 5229 */ 5230 if (rtl_aspm_is_safe(tp)) 5231 rc = 0; 5232 else if (tp->mac_version >= RTL_GIGA_MAC_VER_46) 5233 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1_2); 5234 else 5235 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1); 5236 tp->aspm_manageable = !rc; 5237 5238 tp->dash_type = rtl_check_dash(tp); 5239 5240 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK; 5241 5242 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 5243 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 5244 dev->features |= NETIF_F_HIGHDMA; 5245 5246 rtl_init_rxcfg(tp); 5247 5248 rtl8169_irq_mask_and_ack(tp); 5249 5250 rtl_hw_initialize(tp); 5251 5252 rtl_hw_reset(tp); 5253 5254 rc = rtl_alloc_irq(tp); 5255 if (rc < 0) { 5256 dev_err(&pdev->dev, "Can't allocate interrupt\n"); 5257 return rc; 5258 } 5259 tp->irq = pci_irq_vector(pdev, 0); 5260 5261 INIT_WORK(&tp->wk.work, rtl_task); 5262 5263 rtl_init_mac_address(tp); 5264 5265 dev->ethtool_ops = &rtl8169_ethtool_ops; 5266 5267 netif_napi_add(dev, &tp->napi, rtl8169_poll); 5268 5269 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 5270 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 5271 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 5272 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5273 5274 /* 5275 * Pretend we are using VLANs; This bypasses a nasty bug where 5276 * Interrupts stop flowing on high load on 8110SCd controllers. 5277 */ 5278 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5279 /* Disallow toggling */ 5280 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 5281 5282 if (rtl_chip_supports_csum_v2(tp)) 5283 dev->hw_features |= NETIF_F_IPV6_CSUM; 5284 5285 dev->features |= dev->hw_features; 5286 5287 /* There has been a number of reports that using SG/TSO results in 5288 * tx timeouts. However for a lot of people SG/TSO works fine. 5289 * Therefore disable both features by default, but allow users to 5290 * enable them. Use at own risk! 5291 */ 5292 if (rtl_chip_supports_csum_v2(tp)) { 5293 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6; 5294 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V2); 5295 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V2); 5296 } else { 5297 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO; 5298 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V1); 5299 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V1); 5300 } 5301 5302 dev->hw_features |= NETIF_F_RXALL; 5303 dev->hw_features |= NETIF_F_RXFCS; 5304 5305 netdev_sw_irq_coalesce_default_on(dev); 5306 5307 /* configure chip for default features */ 5308 rtl8169_set_features(dev, dev->features); 5309 5310 if (tp->dash_type == RTL_DASH_NONE) { 5311 rtl_set_d3_pll_down(tp, true); 5312 } else { 5313 rtl_set_d3_pll_down(tp, false); 5314 dev->wol_enabled = 1; 5315 } 5316 5317 jumbo_max = rtl_jumbo_max(tp); 5318 if (jumbo_max) 5319 dev->max_mtu = jumbo_max; 5320 5321 rtl_set_irq_mask(tp); 5322 5323 tp->fw_name = rtl_chip_infos[chipset].fw_name; 5324 5325 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 5326 &tp->counters_phys_addr, 5327 GFP_KERNEL); 5328 if (!tp->counters) 5329 return -ENOMEM; 5330 5331 pci_set_drvdata(pdev, tp); 5332 5333 rc = r8169_mdio_register(tp); 5334 if (rc) 5335 return rc; 5336 5337 rc = register_netdev(dev); 5338 if (rc) 5339 return rc; 5340 5341 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n", 5342 rtl_chip_infos[chipset].name, dev->dev_addr, xid, tp->irq); 5343 5344 if (jumbo_max) 5345 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 5346 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 5347 "ok" : "ko"); 5348 5349 if (tp->dash_type != RTL_DASH_NONE) { 5350 netdev_info(dev, "DASH enabled\n"); 5351 rtl8168_driver_start(tp); 5352 } 5353 5354 if (pci_dev_run_wake(pdev)) 5355 pm_runtime_put_sync(&pdev->dev); 5356 5357 return 0; 5358 } 5359 5360 static struct pci_driver rtl8169_pci_driver = { 5361 .name = KBUILD_MODNAME, 5362 .id_table = rtl8169_pci_tbl, 5363 .probe = rtl_init_one, 5364 .remove = rtl_remove_one, 5365 .shutdown = rtl_shutdown, 5366 .driver.pm = pm_ptr(&rtl8169_pm_ops), 5367 }; 5368 5369 module_pci_driver(rtl8169_pci_driver); 5370