1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 #ifndef _IXGBE_H_ 5 #define _IXGBE_H_ 6 7 #include <linux/bitops.h> 8 #include <linux/types.h> 9 #include <linux/pci.h> 10 #include <linux/netdevice.h> 11 #include <linux/cpumask.h> 12 #include <linux/aer.h> 13 #include <linux/if_vlan.h> 14 #include <linux/jiffies.h> 15 #include <linux/phy.h> 16 17 #include <linux/timecounter.h> 18 #include <linux/net_tstamp.h> 19 #include <linux/ptp_clock_kernel.h> 20 21 #include "ixgbe_type.h" 22 #include "ixgbe_common.h" 23 #include "ixgbe_dcb.h" 24 #if IS_ENABLED(CONFIG_FCOE) 25 #define IXGBE_FCOE 26 #include "ixgbe_fcoe.h" 27 #endif /* IS_ENABLED(CONFIG_FCOE) */ 28 #ifdef CONFIG_IXGBE_DCA 29 #include <linux/dca.h> 30 #endif 31 #include "ixgbe_ipsec.h" 32 33 #include <net/xdp.h> 34 35 /* common prefix used by pr_<> macros */ 36 #undef pr_fmt 37 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 38 39 /* TX/RX descriptor defines */ 40 #define IXGBE_DEFAULT_TXD 512 41 #define IXGBE_DEFAULT_TX_WORK 256 42 #define IXGBE_MAX_TXD_82598 4096 43 #define IXGBE_MAX_TXD_82599 8192 44 #define IXGBE_MAX_TXD_X540 8192 45 #define IXGBE_MAX_TXD_X550 32768 46 #define IXGBE_MIN_TXD 64 47 48 #if (PAGE_SIZE < 8192) 49 #define IXGBE_DEFAULT_RXD 512 50 #else 51 #define IXGBE_DEFAULT_RXD 128 52 #endif 53 #define IXGBE_MAX_RXD_82598 4096 54 #define IXGBE_MAX_RXD_82599 8192 55 #define IXGBE_MAX_RXD_X540 8192 56 #define IXGBE_MAX_RXD_X550 32768 57 #define IXGBE_MIN_RXD 64 58 59 /* flow control */ 60 #define IXGBE_MIN_FCRTL 0x40 61 #define IXGBE_MAX_FCRTL 0x7FF80 62 #define IXGBE_MIN_FCRTH 0x600 63 #define IXGBE_MAX_FCRTH 0x7FFF0 64 #define IXGBE_DEFAULT_FCPAUSE 0xFFFF 65 #define IXGBE_MIN_FCPAUSE 0 66 #define IXGBE_MAX_FCPAUSE 0xFFFF 67 68 /* Supported Rx Buffer Sizes */ 69 #define IXGBE_RXBUFFER_256 256 /* Used for skb receive header */ 70 #define IXGBE_RXBUFFER_1536 1536 71 #define IXGBE_RXBUFFER_2K 2048 72 #define IXGBE_RXBUFFER_3K 3072 73 #define IXGBE_RXBUFFER_4K 4096 74 #define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */ 75 76 #define IXGBE_PKT_HDR_PAD (ETH_HLEN + ETH_FCS_LEN + (VLAN_HLEN * 2)) 77 78 /* Attempt to maximize the headroom available for incoming frames. We 79 * use a 2K buffer for receives and need 1536/1534 to store the data for 80 * the frame. This leaves us with 512 bytes of room. From that we need 81 * to deduct the space needed for the shared info and the padding needed 82 * to IP align the frame. 83 * 84 * Note: For cache line sizes 256 or larger this value is going to end 85 * up negative. In these cases we should fall back to the 3K 86 * buffers. 87 */ 88 #if (PAGE_SIZE < 8192) 89 #define IXGBE_MAX_2K_FRAME_BUILD_SKB (IXGBE_RXBUFFER_1536 - NET_IP_ALIGN) 90 #define IXGBE_2K_TOO_SMALL_WITH_PADDING \ 91 ((NET_SKB_PAD + IXGBE_RXBUFFER_1536) > SKB_WITH_OVERHEAD(IXGBE_RXBUFFER_2K)) 92 93 static inline int ixgbe_compute_pad(int rx_buf_len) 94 { 95 int page_size, pad_size; 96 97 page_size = ALIGN(rx_buf_len, PAGE_SIZE / 2); 98 pad_size = SKB_WITH_OVERHEAD(page_size) - rx_buf_len; 99 100 return pad_size; 101 } 102 103 static inline int ixgbe_skb_pad(void) 104 { 105 int rx_buf_len; 106 107 /* If a 2K buffer cannot handle a standard Ethernet frame then 108 * optimize padding for a 3K buffer instead of a 1.5K buffer. 109 * 110 * For a 3K buffer we need to add enough padding to allow for 111 * tailroom due to NET_IP_ALIGN possibly shifting us out of 112 * cache-line alignment. 113 */ 114 if (IXGBE_2K_TOO_SMALL_WITH_PADDING) 115 rx_buf_len = IXGBE_RXBUFFER_3K + SKB_DATA_ALIGN(NET_IP_ALIGN); 116 else 117 rx_buf_len = IXGBE_RXBUFFER_1536; 118 119 /* if needed make room for NET_IP_ALIGN */ 120 rx_buf_len -= NET_IP_ALIGN; 121 122 return ixgbe_compute_pad(rx_buf_len); 123 } 124 125 #define IXGBE_SKB_PAD ixgbe_skb_pad() 126 #else 127 #define IXGBE_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) 128 #endif 129 130 /* 131 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we 132 * reserve 64 more, and skb_shared_info adds an additional 320 bytes more, 133 * this adds up to 448 bytes of extra data. 134 * 135 * Since netdev_alloc_skb now allocates a page fragment we can use a value 136 * of 256 and the resultant skb will have a truesize of 960 or less. 137 */ 138 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256 139 140 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 141 #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 142 143 #define IXGBE_RX_DMA_ATTR \ 144 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) 145 146 enum ixgbe_tx_flags { 147 /* cmd_type flags */ 148 IXGBE_TX_FLAGS_HW_VLAN = 0x01, 149 IXGBE_TX_FLAGS_TSO = 0x02, 150 IXGBE_TX_FLAGS_TSTAMP = 0x04, 151 152 /* olinfo flags */ 153 IXGBE_TX_FLAGS_CC = 0x08, 154 IXGBE_TX_FLAGS_IPV4 = 0x10, 155 IXGBE_TX_FLAGS_CSUM = 0x20, 156 IXGBE_TX_FLAGS_IPSEC = 0x40, 157 158 /* software defined flags */ 159 IXGBE_TX_FLAGS_SW_VLAN = 0x80, 160 IXGBE_TX_FLAGS_FCOE = 0x100, 161 }; 162 163 /* VLAN info */ 164 #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000 165 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000 166 #define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29 167 #define IXGBE_TX_FLAGS_VLAN_SHIFT 16 168 169 #define IXGBE_MAX_VF_MC_ENTRIES 30 170 #define IXGBE_MAX_VF_FUNCTIONS 64 171 #define IXGBE_MAX_VFTA_ENTRIES 128 172 #define MAX_EMULATION_MAC_ADDRS 16 173 #define IXGBE_MAX_PF_MACVLANS 15 174 #define VMDQ_P(p) ((p) + adapter->ring_feature[RING_F_VMDQ].offset) 175 #define IXGBE_82599_VF_DEVICE_ID 0x10ED 176 #define IXGBE_X540_VF_DEVICE_ID 0x1515 177 178 #define UPDATE_VF_COUNTER_32bit(reg, last_counter, counter) \ 179 { \ 180 u32 current_counter = IXGBE_READ_REG(hw, reg); \ 181 if (current_counter < last_counter) \ 182 counter += 0x100000000LL; \ 183 last_counter = current_counter; \ 184 counter &= 0xFFFFFFFF00000000LL; \ 185 counter |= current_counter; \ 186 } 187 188 #define UPDATE_VF_COUNTER_36bit(reg_lsb, reg_msb, last_counter, counter) \ 189 { \ 190 u64 current_counter_lsb = IXGBE_READ_REG(hw, reg_lsb); \ 191 u64 current_counter_msb = IXGBE_READ_REG(hw, reg_msb); \ 192 u64 current_counter = (current_counter_msb << 32) | \ 193 current_counter_lsb; \ 194 if (current_counter < last_counter) \ 195 counter += 0x1000000000LL; \ 196 last_counter = current_counter; \ 197 counter &= 0xFFFFFFF000000000LL; \ 198 counter |= current_counter; \ 199 } 200 201 struct vf_stats { 202 u64 gprc; 203 u64 gorc; 204 u64 gptc; 205 u64 gotc; 206 u64 mprc; 207 }; 208 209 struct vf_data_storage { 210 struct pci_dev *vfdev; 211 unsigned char vf_mac_addresses[ETH_ALEN]; 212 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES]; 213 u16 num_vf_mc_hashes; 214 bool clear_to_send; 215 struct vf_stats vfstats; 216 struct vf_stats last_vfstats; 217 struct vf_stats saved_rst_vfstats; 218 bool pf_set_mac; 219 u16 pf_vlan; /* When set, guest VLAN config not allowed. */ 220 u16 pf_qos; 221 u16 tx_rate; 222 int link_enable; 223 int link_state; 224 u8 spoofchk_enabled; 225 bool rss_query_enabled; 226 u8 trusted; 227 int xcast_mode; 228 unsigned int vf_api; 229 u8 primary_abort_count; 230 }; 231 232 enum ixgbevf_xcast_modes { 233 IXGBEVF_XCAST_MODE_NONE = 0, 234 IXGBEVF_XCAST_MODE_MULTI, 235 IXGBEVF_XCAST_MODE_ALLMULTI, 236 IXGBEVF_XCAST_MODE_PROMISC, 237 }; 238 239 struct vf_macvlans { 240 struct list_head l; 241 int vf; 242 bool free; 243 bool is_macvlan; 244 u8 vf_macvlan[ETH_ALEN]; 245 }; 246 247 #define IXGBE_MAX_TXD_PWR 14 248 #define IXGBE_MAX_DATA_PER_TXD (1u << IXGBE_MAX_TXD_PWR) 249 250 /* Tx Descriptors needed, worst case */ 251 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD) 252 #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 253 254 /* wrapper around a pointer to a socket buffer, 255 * so a DMA handle can be stored along with the buffer */ 256 struct ixgbe_tx_buffer { 257 union ixgbe_adv_tx_desc *next_to_watch; 258 unsigned long time_stamp; 259 union { 260 struct sk_buff *skb; 261 struct xdp_frame *xdpf; 262 }; 263 unsigned int bytecount; 264 unsigned short gso_segs; 265 __be16 protocol; 266 DEFINE_DMA_UNMAP_ADDR(dma); 267 DEFINE_DMA_UNMAP_LEN(len); 268 u32 tx_flags; 269 }; 270 271 struct ixgbe_rx_buffer { 272 union { 273 struct { 274 struct sk_buff *skb; 275 dma_addr_t dma; 276 struct page *page; 277 __u32 page_offset; 278 __u16 pagecnt_bias; 279 }; 280 struct { 281 bool discard; 282 struct xdp_buff *xdp; 283 }; 284 }; 285 }; 286 287 struct ixgbe_queue_stats { 288 u64 packets; 289 u64 bytes; 290 }; 291 292 struct ixgbe_tx_queue_stats { 293 u64 restart_queue; 294 u64 tx_busy; 295 u64 tx_done_old; 296 }; 297 298 struct ixgbe_rx_queue_stats { 299 u64 rsc_count; 300 u64 rsc_flush; 301 u64 non_eop_descs; 302 u64 alloc_rx_page; 303 u64 alloc_rx_page_failed; 304 u64 alloc_rx_buff_failed; 305 u64 csum_err; 306 }; 307 308 #define IXGBE_TS_HDR_LEN 8 309 310 enum ixgbe_ring_state_t { 311 __IXGBE_RX_3K_BUFFER, 312 __IXGBE_RX_BUILD_SKB_ENABLED, 313 __IXGBE_RX_RSC_ENABLED, 314 __IXGBE_RX_CSUM_UDP_ZERO_ERR, 315 __IXGBE_RX_FCOE, 316 __IXGBE_TX_FDIR_INIT_DONE, 317 __IXGBE_TX_XPS_INIT_DONE, 318 __IXGBE_TX_DETECT_HANG, 319 __IXGBE_HANG_CHECK_ARMED, 320 __IXGBE_TX_XDP_RING, 321 __IXGBE_TX_DISABLED, 322 }; 323 324 #define ring_uses_build_skb(ring) \ 325 test_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &(ring)->state) 326 327 struct ixgbe_fwd_adapter { 328 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 329 struct net_device *netdev; 330 unsigned int tx_base_queue; 331 unsigned int rx_base_queue; 332 int pool; 333 }; 334 335 #define check_for_tx_hang(ring) \ 336 test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 337 #define set_check_for_tx_hang(ring) \ 338 set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 339 #define clear_check_for_tx_hang(ring) \ 340 clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) 341 #define ring_is_rsc_enabled(ring) \ 342 test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 343 #define set_ring_rsc_enabled(ring) \ 344 set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 345 #define clear_ring_rsc_enabled(ring) \ 346 clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) 347 #define ring_is_xdp(ring) \ 348 test_bit(__IXGBE_TX_XDP_RING, &(ring)->state) 349 #define set_ring_xdp(ring) \ 350 set_bit(__IXGBE_TX_XDP_RING, &(ring)->state) 351 #define clear_ring_xdp(ring) \ 352 clear_bit(__IXGBE_TX_XDP_RING, &(ring)->state) 353 struct ixgbe_ring { 354 struct ixgbe_ring *next; /* pointer to next ring in q_vector */ 355 struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */ 356 struct net_device *netdev; /* netdev ring belongs to */ 357 struct bpf_prog *xdp_prog; 358 struct device *dev; /* device for DMA mapping */ 359 void *desc; /* descriptor ring memory */ 360 union { 361 struct ixgbe_tx_buffer *tx_buffer_info; 362 struct ixgbe_rx_buffer *rx_buffer_info; 363 }; 364 unsigned long state; 365 u8 __iomem *tail; 366 dma_addr_t dma; /* phys. address of descriptor ring */ 367 unsigned int size; /* length in bytes */ 368 369 u16 count; /* amount of descriptors */ 370 371 u8 queue_index; /* needed for multiqueue queue management */ 372 u8 reg_idx; /* holds the special value that gets 373 * the hardware register offset 374 * associated with this ring, which is 375 * different for DCB and RSS modes 376 */ 377 u16 next_to_use; 378 u16 next_to_clean; 379 380 unsigned long last_rx_timestamp; 381 382 union { 383 u16 next_to_alloc; 384 struct { 385 u8 atr_sample_rate; 386 u8 atr_count; 387 }; 388 }; 389 390 u8 dcb_tc; 391 struct ixgbe_queue_stats stats; 392 struct u64_stats_sync syncp; 393 union { 394 struct ixgbe_tx_queue_stats tx_stats; 395 struct ixgbe_rx_queue_stats rx_stats; 396 }; 397 u16 rx_offset; 398 struct xdp_rxq_info xdp_rxq; 399 spinlock_t tx_lock; /* used in XDP mode */ 400 struct xsk_buff_pool *xsk_pool; 401 u16 ring_idx; /* {rx,tx,xdp}_ring back reference idx */ 402 u16 rx_buf_len; 403 } ____cacheline_internodealigned_in_smp; 404 405 enum ixgbe_ring_f_enum { 406 RING_F_NONE = 0, 407 RING_F_VMDQ, /* SR-IOV uses the same ring feature */ 408 RING_F_RSS, 409 RING_F_FDIR, 410 #ifdef IXGBE_FCOE 411 RING_F_FCOE, 412 #endif /* IXGBE_FCOE */ 413 414 RING_F_ARRAY_SIZE /* must be last in enum set */ 415 }; 416 417 #define IXGBE_MAX_RSS_INDICES 16 418 #define IXGBE_MAX_RSS_INDICES_X550 63 419 #define IXGBE_MAX_VMDQ_INDICES 64 420 #define IXGBE_MAX_FDIR_INDICES 63 /* based on q_vector limit */ 421 #define IXGBE_MAX_FCOE_INDICES 8 422 #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) 423 #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1) 424 #define IXGBE_MAX_XDP_QS (IXGBE_MAX_FDIR_INDICES + 1) 425 #define IXGBE_MAX_L2A_QUEUES 4 426 #define IXGBE_BAD_L2A_QUEUE 3 427 #define IXGBE_MAX_MACVLANS 63 428 429 DECLARE_STATIC_KEY_FALSE(ixgbe_xdp_locking_key); 430 431 struct ixgbe_ring_feature { 432 u16 limit; /* upper limit on feature indices */ 433 u16 indices; /* current value of indices */ 434 u16 mask; /* Mask used for feature to ring mapping */ 435 u16 offset; /* offset to start of feature */ 436 } ____cacheline_internodealigned_in_smp; 437 438 #define IXGBE_82599_VMDQ_8Q_MASK 0x78 439 #define IXGBE_82599_VMDQ_4Q_MASK 0x7C 440 #define IXGBE_82599_VMDQ_2Q_MASK 0x7E 441 442 /* 443 * FCoE requires that all Rx buffers be over 2200 bytes in length. Since 444 * this is twice the size of a half page we need to double the page order 445 * for FCoE enabled Rx queues. 446 */ 447 static inline unsigned int ixgbe_rx_bufsz(struct ixgbe_ring *ring) 448 { 449 if (test_bit(__IXGBE_RX_3K_BUFFER, &ring->state)) 450 return IXGBE_RXBUFFER_3K; 451 #if (PAGE_SIZE < 8192) 452 if (ring_uses_build_skb(ring)) 453 return IXGBE_MAX_2K_FRAME_BUILD_SKB; 454 #endif 455 return IXGBE_RXBUFFER_2K; 456 } 457 458 static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring) 459 { 460 #if (PAGE_SIZE < 8192) 461 if (test_bit(__IXGBE_RX_3K_BUFFER, &ring->state)) 462 return 1; 463 #endif 464 return 0; 465 } 466 #define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring)) 467 468 #define IXGBE_ITR_ADAPTIVE_MIN_INC 2 469 #define IXGBE_ITR_ADAPTIVE_MIN_USECS 10 470 #define IXGBE_ITR_ADAPTIVE_MAX_USECS 126 471 #define IXGBE_ITR_ADAPTIVE_LATENCY 0x80 472 #define IXGBE_ITR_ADAPTIVE_BULK 0x00 473 474 struct ixgbe_ring_container { 475 struct ixgbe_ring *ring; /* pointer to linked list of rings */ 476 unsigned long next_update; /* jiffies value of last update */ 477 unsigned int total_bytes; /* total bytes processed this int */ 478 unsigned int total_packets; /* total packets processed this int */ 479 u16 work_limit; /* total work allowed per interrupt */ 480 u8 count; /* total number of rings in vector */ 481 u8 itr; /* current ITR setting for ring */ 482 }; 483 484 /* iterator for handling rings in ring container */ 485 #define ixgbe_for_each_ring(pos, head) \ 486 for (pos = (head).ring; pos != NULL; pos = pos->next) 487 488 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \ 489 ? 8 : 1) 490 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS 491 492 /* MAX_Q_VECTORS of these are allocated, 493 * but we only use one per queue-specific vector. 494 */ 495 struct ixgbe_q_vector { 496 struct ixgbe_adapter *adapter; 497 #ifdef CONFIG_IXGBE_DCA 498 int cpu; /* CPU for DCA */ 499 #endif 500 u16 v_idx; /* index of q_vector within array, also used for 501 * finding the bit in EICR and friends that 502 * represents the vector for this ring */ 503 u16 itr; /* Interrupt throttle rate written to EITR */ 504 struct ixgbe_ring_container rx, tx; 505 506 struct napi_struct napi; 507 cpumask_t affinity_mask; 508 int numa_node; 509 struct rcu_head rcu; /* to avoid race with update stats on free */ 510 char name[IFNAMSIZ + 9]; 511 512 /* for dynamic allocation of rings associated with this q_vector */ 513 struct ixgbe_ring ring[] ____cacheline_internodealigned_in_smp; 514 }; 515 516 #ifdef CONFIG_IXGBE_HWMON 517 518 #define IXGBE_HWMON_TYPE_LOC 0 519 #define IXGBE_HWMON_TYPE_TEMP 1 520 #define IXGBE_HWMON_TYPE_CAUTION 2 521 #define IXGBE_HWMON_TYPE_MAX 3 522 523 struct hwmon_attr { 524 struct device_attribute dev_attr; 525 struct ixgbe_hw *hw; 526 struct ixgbe_thermal_diode_data *sensor; 527 char name[12]; 528 }; 529 530 struct hwmon_buff { 531 struct attribute_group group; 532 const struct attribute_group *groups[2]; 533 struct attribute *attrs[IXGBE_MAX_SENSORS * 4 + 1]; 534 struct hwmon_attr hwmon_list[IXGBE_MAX_SENSORS * 4]; 535 unsigned int n_hwmon; 536 }; 537 #endif /* CONFIG_IXGBE_HWMON */ 538 539 /* 540 * microsecond values for various ITR rates shifted by 2 to fit itr register 541 * with the first 3 bits reserved 0 542 */ 543 #define IXGBE_MIN_RSC_ITR 24 544 #define IXGBE_100K_ITR 40 545 #define IXGBE_20K_ITR 200 546 #define IXGBE_12K_ITR 336 547 548 /* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */ 549 static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc, 550 const u32 stat_err_bits) 551 { 552 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 553 } 554 555 static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring) 556 { 557 u16 ntc = ring->next_to_clean; 558 u16 ntu = ring->next_to_use; 559 560 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 561 } 562 563 #define IXGBE_RX_DESC(R, i) \ 564 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i])) 565 #define IXGBE_TX_DESC(R, i) \ 566 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i])) 567 #define IXGBE_TX_CTXTDESC(R, i) \ 568 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i])) 569 570 #define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */ 571 #ifdef IXGBE_FCOE 572 /* Use 3K as the baby jumbo frame size for FCoE */ 573 #define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072 574 #endif /* IXGBE_FCOE */ 575 576 #define OTHER_VECTOR 1 577 #define NON_Q_VECTORS (OTHER_VECTOR) 578 579 #define MAX_MSIX_VECTORS_82599 64 580 #define MAX_Q_VECTORS_82599 64 581 #define MAX_MSIX_VECTORS_82598 18 582 #define MAX_Q_VECTORS_82598 16 583 584 struct ixgbe_mac_addr { 585 u8 addr[ETH_ALEN]; 586 u16 pool; 587 u16 state; /* bitmask */ 588 }; 589 590 #define IXGBE_MAC_STATE_DEFAULT 0x1 591 #define IXGBE_MAC_STATE_MODIFIED 0x2 592 #define IXGBE_MAC_STATE_IN_USE 0x4 593 594 #define MAX_Q_VECTORS MAX_Q_VECTORS_82599 595 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599 596 597 #define MIN_MSIX_Q_VECTORS 1 598 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS) 599 600 /* default to trying for four seconds */ 601 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ) 602 #define IXGBE_SFP_POLL_JIFFIES (2 * HZ) /* SFP poll every 2 seconds */ 603 604 #define IXGBE_PRIMARY_ABORT_LIMIT 5 605 606 /* board specific private data structure */ 607 struct ixgbe_adapter { 608 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 609 /* OS defined structs */ 610 struct net_device *netdev; 611 struct bpf_prog *xdp_prog; 612 struct pci_dev *pdev; 613 struct mii_bus *mii_bus; 614 615 unsigned long state; 616 617 /* Some features need tri-state capability, 618 * thus the additional *_CAPABLE flags. 619 */ 620 u32 flags; 621 #define IXGBE_FLAG_MSI_ENABLED BIT(1) 622 #define IXGBE_FLAG_MSIX_ENABLED BIT(3) 623 #define IXGBE_FLAG_RX_1BUF_CAPABLE BIT(4) 624 #define IXGBE_FLAG_RX_PS_CAPABLE BIT(5) 625 #define IXGBE_FLAG_RX_PS_ENABLED BIT(6) 626 #define IXGBE_FLAG_DCA_ENABLED BIT(8) 627 #define IXGBE_FLAG_DCA_CAPABLE BIT(9) 628 #define IXGBE_FLAG_IMIR_ENABLED BIT(10) 629 #define IXGBE_FLAG_MQ_CAPABLE BIT(11) 630 #define IXGBE_FLAG_DCB_ENABLED BIT(12) 631 #define IXGBE_FLAG_VMDQ_CAPABLE BIT(13) 632 #define IXGBE_FLAG_VMDQ_ENABLED BIT(14) 633 #define IXGBE_FLAG_FAN_FAIL_CAPABLE BIT(15) 634 #define IXGBE_FLAG_NEED_LINK_UPDATE BIT(16) 635 #define IXGBE_FLAG_NEED_LINK_CONFIG BIT(17) 636 #define IXGBE_FLAG_FDIR_HASH_CAPABLE BIT(18) 637 #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE BIT(19) 638 #define IXGBE_FLAG_FCOE_CAPABLE BIT(20) 639 #define IXGBE_FLAG_FCOE_ENABLED BIT(21) 640 #define IXGBE_FLAG_SRIOV_CAPABLE BIT(22) 641 #define IXGBE_FLAG_SRIOV_ENABLED BIT(23) 642 #define IXGBE_FLAG_RX_HWTSTAMP_ENABLED BIT(25) 643 #define IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER BIT(26) 644 #define IXGBE_FLAG_DCB_CAPABLE BIT(27) 645 646 u32 flags2; 647 #define IXGBE_FLAG2_RSC_CAPABLE BIT(0) 648 #define IXGBE_FLAG2_RSC_ENABLED BIT(1) 649 #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE BIT(2) 650 #define IXGBE_FLAG2_TEMP_SENSOR_EVENT BIT(3) 651 #define IXGBE_FLAG2_SEARCH_FOR_SFP BIT(4) 652 #define IXGBE_FLAG2_SFP_NEEDS_RESET BIT(5) 653 #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT BIT(7) 654 #define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP BIT(8) 655 #define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP BIT(9) 656 #define IXGBE_FLAG2_PTP_PPS_ENABLED BIT(10) 657 #define IXGBE_FLAG2_PHY_INTERRUPT BIT(11) 658 #define IXGBE_FLAG2_VLAN_PROMISC BIT(13) 659 #define IXGBE_FLAG2_EEE_CAPABLE BIT(14) 660 #define IXGBE_FLAG2_EEE_ENABLED BIT(15) 661 #define IXGBE_FLAG2_RX_LEGACY BIT(16) 662 #define IXGBE_FLAG2_IPSEC_ENABLED BIT(17) 663 #define IXGBE_FLAG2_VF_IPSEC_ENABLED BIT(18) 664 #define IXGBE_FLAG2_AUTO_DISABLE_VF BIT(19) 665 666 /* Tx fast path data */ 667 int num_tx_queues; 668 u16 tx_itr_setting; 669 u16 tx_work_limit; 670 u64 tx_ipsec; 671 672 /* Rx fast path data */ 673 int num_rx_queues; 674 u16 rx_itr_setting; 675 u64 rx_ipsec; 676 677 /* Port number used to identify VXLAN traffic */ 678 __be16 vxlan_port; 679 __be16 geneve_port; 680 681 /* XDP */ 682 int num_xdp_queues; 683 struct ixgbe_ring *xdp_ring[IXGBE_MAX_XDP_QS]; 684 unsigned long *af_xdp_zc_qps; /* tracks AF_XDP ZC enabled rings */ 685 686 /* TX */ 687 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp; 688 689 u64 restart_queue; 690 u64 lsc_int; 691 u32 tx_timeout_count; 692 693 /* RX */ 694 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES]; 695 int num_rx_pools; /* == num_rx_queues in 82598 */ 696 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */ 697 u64 hw_csum_rx_error; 698 u64 hw_rx_no_dma_resources; 699 u64 rsc_total_count; 700 u64 rsc_total_flush; 701 u64 non_eop_descs; 702 u32 alloc_rx_page; 703 u32 alloc_rx_page_failed; 704 u32 alloc_rx_buff_failed; 705 706 struct ixgbe_q_vector *q_vector[MAX_Q_VECTORS]; 707 708 /* DCB parameters */ 709 struct ieee_pfc *ixgbe_ieee_pfc; 710 struct ieee_ets *ixgbe_ieee_ets; 711 struct ixgbe_dcb_config dcb_cfg; 712 struct ixgbe_dcb_config temp_dcb_cfg; 713 u8 hw_tcs; 714 u8 dcb_set_bitmap; 715 u8 dcbx_cap; 716 enum ixgbe_fc_mode last_lfc_mode; 717 718 int num_q_vectors; /* current number of q_vectors for device */ 719 int max_q_vectors; /* true count of q_vectors for device */ 720 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE]; 721 struct msix_entry *msix_entries; 722 723 u32 test_icr; 724 struct ixgbe_ring test_tx_ring; 725 struct ixgbe_ring test_rx_ring; 726 727 /* structs defined in ixgbe_hw.h */ 728 struct ixgbe_hw hw; 729 u16 msg_enable; 730 struct ixgbe_hw_stats stats; 731 732 u64 tx_busy; 733 unsigned int tx_ring_count; 734 unsigned int xdp_ring_count; 735 unsigned int rx_ring_count; 736 737 u32 link_speed; 738 bool link_up; 739 unsigned long sfp_poll_time; 740 unsigned long link_check_timeout; 741 742 struct timer_list service_timer; 743 struct work_struct service_task; 744 745 struct hlist_head fdir_filter_list; 746 unsigned long fdir_overflow; /* number of times ATR was backed off */ 747 union ixgbe_atr_input fdir_mask; 748 int fdir_filter_count; 749 u32 fdir_pballoc; 750 u32 atr_sample_rate; 751 spinlock_t fdir_perfect_lock; 752 753 #ifdef IXGBE_FCOE 754 struct ixgbe_fcoe fcoe; 755 #endif /* IXGBE_FCOE */ 756 u8 __iomem *io_addr; /* Mainly for iounmap use */ 757 u32 wol; 758 759 u16 bridge_mode; 760 761 char eeprom_id[NVM_VER_SIZE]; 762 u16 eeprom_cap; 763 764 u32 interrupt_event; 765 u32 led_reg; 766 767 struct ptp_clock *ptp_clock; 768 struct ptp_clock_info ptp_caps; 769 struct work_struct ptp_tx_work; 770 struct sk_buff *ptp_tx_skb; 771 struct hwtstamp_config tstamp_config; 772 unsigned long ptp_tx_start; 773 unsigned long last_overflow_check; 774 unsigned long last_rx_ptp_check; 775 unsigned long last_rx_timestamp; 776 spinlock_t tmreg_lock; 777 struct cyclecounter hw_cc; 778 struct timecounter hw_tc; 779 u32 base_incval; 780 u32 tx_hwtstamp_timeouts; 781 u32 tx_hwtstamp_skipped; 782 u32 rx_hwtstamp_cleared; 783 void (*ptp_setup_sdp)(struct ixgbe_adapter *); 784 785 /* SR-IOV */ 786 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS); 787 unsigned int num_vfs; 788 struct vf_data_storage *vfinfo; 789 int vf_rate_link_speed; 790 struct vf_macvlans vf_mvs; 791 struct vf_macvlans *mv_list; 792 793 u32 timer_event_accumulator; 794 u32 vferr_refcount; 795 struct ixgbe_mac_addr *mac_table; 796 struct kobject *info_kobj; 797 #ifdef CONFIG_IXGBE_HWMON 798 struct hwmon_buff *ixgbe_hwmon_buff; 799 #endif /* CONFIG_IXGBE_HWMON */ 800 #ifdef CONFIG_DEBUG_FS 801 struct dentry *ixgbe_dbg_adapter; 802 #endif /*CONFIG_DEBUG_FS*/ 803 804 u8 default_up; 805 /* Bitmask indicating in use pools */ 806 DECLARE_BITMAP(fwd_bitmask, IXGBE_MAX_MACVLANS + 1); 807 808 #define IXGBE_MAX_LINK_HANDLE 10 809 struct ixgbe_jump_table *jump_tables[IXGBE_MAX_LINK_HANDLE]; 810 unsigned long tables; 811 812 /* maximum number of RETA entries among all devices supported by ixgbe 813 * driver: currently it's x550 device in non-SRIOV mode 814 */ 815 #define IXGBE_MAX_RETA_ENTRIES 512 816 u8 rss_indir_tbl[IXGBE_MAX_RETA_ENTRIES]; 817 818 #define IXGBE_RSS_KEY_SIZE 40 /* size of RSS Hash Key in bytes */ 819 u32 *rss_key; 820 821 #ifdef CONFIG_IXGBE_IPSEC 822 struct ixgbe_ipsec *ipsec; 823 #endif /* CONFIG_IXGBE_IPSEC */ 824 spinlock_t vfs_lock; 825 }; 826 827 static inline int ixgbe_determine_xdp_q_idx(int cpu) 828 { 829 if (static_key_enabled(&ixgbe_xdp_locking_key)) 830 return cpu % IXGBE_MAX_XDP_QS; 831 else 832 return cpu; 833 } 834 835 static inline 836 struct ixgbe_ring *ixgbe_determine_xdp_ring(struct ixgbe_adapter *adapter) 837 { 838 int index = ixgbe_determine_xdp_q_idx(smp_processor_id()); 839 840 return adapter->xdp_ring[index]; 841 } 842 843 static inline u8 ixgbe_max_rss_indices(struct ixgbe_adapter *adapter) 844 { 845 switch (adapter->hw.mac.type) { 846 case ixgbe_mac_82598EB: 847 case ixgbe_mac_82599EB: 848 case ixgbe_mac_X540: 849 return IXGBE_MAX_RSS_INDICES; 850 case ixgbe_mac_X550: 851 case ixgbe_mac_X550EM_x: 852 case ixgbe_mac_x550em_a: 853 return IXGBE_MAX_RSS_INDICES_X550; 854 default: 855 return 0; 856 } 857 } 858 859 struct ixgbe_fdir_filter { 860 struct hlist_node fdir_node; 861 union ixgbe_atr_input filter; 862 u16 sw_idx; 863 u64 action; 864 }; 865 866 enum ixgbe_state_t { 867 __IXGBE_TESTING, 868 __IXGBE_RESETTING, 869 __IXGBE_DOWN, 870 __IXGBE_DISABLED, 871 __IXGBE_REMOVING, 872 __IXGBE_SERVICE_SCHED, 873 __IXGBE_SERVICE_INITED, 874 __IXGBE_IN_SFP_INIT, 875 __IXGBE_PTP_RUNNING, 876 __IXGBE_PTP_TX_IN_PROGRESS, 877 __IXGBE_RESET_REQUESTED, 878 }; 879 880 struct ixgbe_cb { 881 union { /* Union defining head/tail partner */ 882 struct sk_buff *head; 883 struct sk_buff *tail; 884 }; 885 dma_addr_t dma; 886 u16 append_cnt; 887 bool page_released; 888 }; 889 #define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb) 890 891 enum ixgbe_boards { 892 board_82598, 893 board_82599, 894 board_X540, 895 board_X550, 896 board_X550EM_x, 897 board_x550em_x_fw, 898 board_x550em_a, 899 board_x550em_a_fw, 900 }; 901 902 extern const struct ixgbe_info ixgbe_82598_info; 903 extern const struct ixgbe_info ixgbe_82599_info; 904 extern const struct ixgbe_info ixgbe_X540_info; 905 extern const struct ixgbe_info ixgbe_X550_info; 906 extern const struct ixgbe_info ixgbe_X550EM_x_info; 907 extern const struct ixgbe_info ixgbe_x550em_x_fw_info; 908 extern const struct ixgbe_info ixgbe_x550em_a_info; 909 extern const struct ixgbe_info ixgbe_x550em_a_fw_info; 910 #ifdef CONFIG_IXGBE_DCB 911 extern const struct dcbnl_rtnl_ops ixgbe_dcbnl_ops; 912 #endif 913 914 extern char ixgbe_driver_name[]; 915 #ifdef IXGBE_FCOE 916 extern char ixgbe_default_device_descr[]; 917 #endif /* IXGBE_FCOE */ 918 919 int ixgbe_open(struct net_device *netdev); 920 int ixgbe_close(struct net_device *netdev); 921 void ixgbe_up(struct ixgbe_adapter *adapter); 922 void ixgbe_down(struct ixgbe_adapter *adapter); 923 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter); 924 void ixgbe_reset(struct ixgbe_adapter *adapter); 925 void ixgbe_set_ethtool_ops(struct net_device *netdev); 926 int ixgbe_setup_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *); 927 int ixgbe_setup_tx_resources(struct ixgbe_ring *); 928 void ixgbe_free_rx_resources(struct ixgbe_ring *); 929 void ixgbe_free_tx_resources(struct ixgbe_ring *); 930 void ixgbe_configure_rx_ring(struct ixgbe_adapter *, struct ixgbe_ring *); 931 void ixgbe_configure_tx_ring(struct ixgbe_adapter *, struct ixgbe_ring *); 932 void ixgbe_disable_rx(struct ixgbe_adapter *adapter); 933 void ixgbe_disable_tx(struct ixgbe_adapter *adapter); 934 void ixgbe_update_stats(struct ixgbe_adapter *adapter); 935 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter); 936 bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, 937 u16 subdevice_id); 938 #ifdef CONFIG_PCI_IOV 939 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter); 940 #endif 941 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, 942 const u8 *addr, u16 queue); 943 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, 944 const u8 *addr, u16 queue); 945 void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid); 946 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter); 947 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *, struct ixgbe_adapter *, 948 struct ixgbe_ring *); 949 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *, 950 struct ixgbe_tx_buffer *); 951 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16); 952 void ixgbe_write_eitr(struct ixgbe_q_vector *); 953 int ixgbe_poll(struct napi_struct *napi, int budget); 954 int ethtool_ioctl(struct ifreq *ifr); 955 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw); 956 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl); 957 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl); 958 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, 959 union ixgbe_atr_hash_dword input, 960 union ixgbe_atr_hash_dword common, 961 u8 queue); 962 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, 963 union ixgbe_atr_input *input_mask); 964 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, 965 union ixgbe_atr_input *input, 966 u16 soft_id, u8 queue); 967 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, 968 union ixgbe_atr_input *input, 969 u16 soft_id); 970 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, 971 union ixgbe_atr_input *mask); 972 int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter, 973 struct ixgbe_fdir_filter *input, 974 u16 sw_idx); 975 void ixgbe_set_rx_mode(struct net_device *netdev); 976 #ifdef CONFIG_IXGBE_DCB 977 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter); 978 #endif 979 int ixgbe_setup_tc(struct net_device *dev, u8 tc); 980 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32); 981 void ixgbe_do_reset(struct net_device *netdev); 982 #ifdef CONFIG_IXGBE_HWMON 983 void ixgbe_sysfs_exit(struct ixgbe_adapter *adapter); 984 int ixgbe_sysfs_init(struct ixgbe_adapter *adapter); 985 #endif /* CONFIG_IXGBE_HWMON */ 986 #ifdef IXGBE_FCOE 987 void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter); 988 int ixgbe_fso(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first, 989 u8 *hdr_len); 990 int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter, 991 union ixgbe_adv_rx_desc *rx_desc, struct sk_buff *skb); 992 int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid, 993 struct scatterlist *sgl, unsigned int sgc); 994 int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid, 995 struct scatterlist *sgl, unsigned int sgc); 996 int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid); 997 int ixgbe_setup_fcoe_ddp_resources(struct ixgbe_adapter *adapter); 998 void ixgbe_free_fcoe_ddp_resources(struct ixgbe_adapter *adapter); 999 int ixgbe_fcoe_enable(struct net_device *netdev); 1000 int ixgbe_fcoe_disable(struct net_device *netdev); 1001 #ifdef CONFIG_IXGBE_DCB 1002 u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter); 1003 u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up); 1004 #endif /* CONFIG_IXGBE_DCB */ 1005 int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type); 1006 int ixgbe_fcoe_get_hbainfo(struct net_device *netdev, 1007 struct netdev_fcoe_hbainfo *info); 1008 u8 ixgbe_fcoe_get_tc(struct ixgbe_adapter *adapter); 1009 #endif /* IXGBE_FCOE */ 1010 #ifdef CONFIG_DEBUG_FS 1011 void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter); 1012 void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter); 1013 void ixgbe_dbg_init(void); 1014 void ixgbe_dbg_exit(void); 1015 #else 1016 static inline void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter) {} 1017 static inline void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter) {} 1018 static inline void ixgbe_dbg_init(void) {} 1019 static inline void ixgbe_dbg_exit(void) {} 1020 #endif /* CONFIG_DEBUG_FS */ 1021 static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring) 1022 { 1023 return netdev_get_tx_queue(ring->netdev, ring->queue_index); 1024 } 1025 1026 void ixgbe_ptp_init(struct ixgbe_adapter *adapter); 1027 void ixgbe_ptp_suspend(struct ixgbe_adapter *adapter); 1028 void ixgbe_ptp_stop(struct ixgbe_adapter *adapter); 1029 void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter); 1030 void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter); 1031 void ixgbe_ptp_tx_hang(struct ixgbe_adapter *adapter); 1032 void ixgbe_ptp_rx_pktstamp(struct ixgbe_q_vector *, struct sk_buff *); 1033 void ixgbe_ptp_rx_rgtstamp(struct ixgbe_q_vector *, struct sk_buff *skb); 1034 static inline void ixgbe_ptp_rx_hwtstamp(struct ixgbe_ring *rx_ring, 1035 union ixgbe_adv_rx_desc *rx_desc, 1036 struct sk_buff *skb) 1037 { 1038 if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_TSIP))) { 1039 ixgbe_ptp_rx_pktstamp(rx_ring->q_vector, skb); 1040 return; 1041 } 1042 1043 if (unlikely(!ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS))) 1044 return; 1045 1046 ixgbe_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 1047 1048 /* Update the last_rx_timestamp timer in order to enable watchdog check 1049 * for error case of latched timestamp on a dropped packet. 1050 */ 1051 rx_ring->last_rx_timestamp = jiffies; 1052 } 1053 1054 int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr); 1055 int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr); 1056 void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter); 1057 void ixgbe_ptp_reset(struct ixgbe_adapter *adapter); 1058 void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter); 1059 #ifdef CONFIG_PCI_IOV 1060 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter); 1061 #endif 1062 1063 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, 1064 struct ixgbe_adapter *adapter, 1065 struct ixgbe_ring *tx_ring); 1066 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter); 1067 void ixgbe_store_key(struct ixgbe_adapter *adapter); 1068 void ixgbe_store_reta(struct ixgbe_adapter *adapter); 1069 s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, 1070 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm); 1071 #ifdef CONFIG_IXGBE_IPSEC 1072 void ixgbe_init_ipsec_offload(struct ixgbe_adapter *adapter); 1073 void ixgbe_stop_ipsec_offload(struct ixgbe_adapter *adapter); 1074 void ixgbe_ipsec_restore(struct ixgbe_adapter *adapter); 1075 void ixgbe_ipsec_rx(struct ixgbe_ring *rx_ring, 1076 union ixgbe_adv_rx_desc *rx_desc, 1077 struct sk_buff *skb); 1078 int ixgbe_ipsec_tx(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first, 1079 struct ixgbe_ipsec_tx_data *itd); 1080 void ixgbe_ipsec_vf_clear(struct ixgbe_adapter *adapter, u32 vf); 1081 int ixgbe_ipsec_vf_add_sa(struct ixgbe_adapter *adapter, u32 *mbuf, u32 vf); 1082 int ixgbe_ipsec_vf_del_sa(struct ixgbe_adapter *adapter, u32 *mbuf, u32 vf); 1083 #else 1084 static inline void ixgbe_init_ipsec_offload(struct ixgbe_adapter *adapter) { } 1085 static inline void ixgbe_stop_ipsec_offload(struct ixgbe_adapter *adapter) { } 1086 static inline void ixgbe_ipsec_restore(struct ixgbe_adapter *adapter) { } 1087 static inline void ixgbe_ipsec_rx(struct ixgbe_ring *rx_ring, 1088 union ixgbe_adv_rx_desc *rx_desc, 1089 struct sk_buff *skb) { } 1090 static inline int ixgbe_ipsec_tx(struct ixgbe_ring *tx_ring, 1091 struct ixgbe_tx_buffer *first, 1092 struct ixgbe_ipsec_tx_data *itd) { return 0; } 1093 static inline void ixgbe_ipsec_vf_clear(struct ixgbe_adapter *adapter, 1094 u32 vf) { } 1095 static inline int ixgbe_ipsec_vf_add_sa(struct ixgbe_adapter *adapter, 1096 u32 *mbuf, u32 vf) { return -EACCES; } 1097 static inline int ixgbe_ipsec_vf_del_sa(struct ixgbe_adapter *adapter, 1098 u32 *mbuf, u32 vf) { return -EACCES; } 1099 #endif /* CONFIG_IXGBE_IPSEC */ 1100 1101 static inline bool ixgbe_enabled_xdp_adapter(struct ixgbe_adapter *adapter) 1102 { 1103 return !!adapter->xdp_prog; 1104 } 1105 1106 #endif /* _IXGBE_H_ */ 1107