1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * NVM Express device driver 4 * Copyright (c) 2011-2014, Intel Corporation. 5 */ 6 7 #include <linux/acpi.h> 8 #include <linux/aer.h> 9 #include <linux/async.h> 10 #include <linux/blkdev.h> 11 #include <linux/blk-mq.h> 12 #include <linux/blk-mq-pci.h> 13 #include <linux/blk-integrity.h> 14 #include <linux/dmi.h> 15 #include <linux/init.h> 16 #include <linux/interrupt.h> 17 #include <linux/io.h> 18 #include <linux/memremap.h> 19 #include <linux/mm.h> 20 #include <linux/module.h> 21 #include <linux/mutex.h> 22 #include <linux/once.h> 23 #include <linux/pci.h> 24 #include <linux/suspend.h> 25 #include <linux/t10-pi.h> 26 #include <linux/types.h> 27 #include <linux/io-64-nonatomic-lo-hi.h> 28 #include <linux/io-64-nonatomic-hi-lo.h> 29 #include <linux/sed-opal.h> 30 #include <linux/pci-p2pdma.h> 31 32 #include "trace.h" 33 #include "nvme.h" 34 35 #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes) 36 #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion)) 37 38 #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 39 40 /* 41 * These can be higher, but we need to ensure that any command doesn't 42 * require an sg allocation that needs more than a page of data. 43 */ 44 #define NVME_MAX_KB_SZ 4096 45 #define NVME_MAX_SEGS 127 46 47 static int use_threaded_interrupts; 48 module_param(use_threaded_interrupts, int, 0444); 49 50 static bool use_cmb_sqes = true; 51 module_param(use_cmb_sqes, bool, 0444); 52 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 53 54 static unsigned int max_host_mem_size_mb = 128; 55 module_param(max_host_mem_size_mb, uint, 0444); 56 MODULE_PARM_DESC(max_host_mem_size_mb, 57 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 58 59 static unsigned int sgl_threshold = SZ_32K; 60 module_param(sgl_threshold, uint, 0644); 61 MODULE_PARM_DESC(sgl_threshold, 62 "Use SGLs when average request segment size is larger or equal to " 63 "this size. Use 0 to disable SGLs."); 64 65 #define NVME_PCI_MIN_QUEUE_SIZE 2 66 #define NVME_PCI_MAX_QUEUE_SIZE 4095 67 static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 68 static const struct kernel_param_ops io_queue_depth_ops = { 69 .set = io_queue_depth_set, 70 .get = param_get_uint, 71 }; 72 73 static unsigned int io_queue_depth = 1024; 74 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 75 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096"); 76 77 static int io_queue_count_set(const char *val, const struct kernel_param *kp) 78 { 79 unsigned int n; 80 int ret; 81 82 ret = kstrtouint(val, 10, &n); 83 if (ret != 0 || n > num_possible_cpus()) 84 return -EINVAL; 85 return param_set_uint(val, kp); 86 } 87 88 static const struct kernel_param_ops io_queue_count_ops = { 89 .set = io_queue_count_set, 90 .get = param_get_uint, 91 }; 92 93 static unsigned int write_queues; 94 module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644); 95 MODULE_PARM_DESC(write_queues, 96 "Number of queues to use for writes. If not set, reads and writes " 97 "will share a queue set."); 98 99 static unsigned int poll_queues; 100 module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644); 101 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 102 103 static bool noacpi; 104 module_param(noacpi, bool, 0444); 105 MODULE_PARM_DESC(noacpi, "disable acpi bios quirks"); 106 107 struct nvme_dev; 108 struct nvme_queue; 109 110 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 111 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode); 112 113 /* 114 * Represents an NVM Express device. Each nvme_dev is a PCI function. 115 */ 116 struct nvme_dev { 117 struct nvme_queue *queues; 118 struct blk_mq_tag_set tagset; 119 struct blk_mq_tag_set admin_tagset; 120 u32 __iomem *dbs; 121 struct device *dev; 122 struct dma_pool *prp_page_pool; 123 struct dma_pool *prp_small_pool; 124 unsigned online_queues; 125 unsigned max_qid; 126 unsigned io_queues[HCTX_MAX_TYPES]; 127 unsigned int num_vecs; 128 u32 q_depth; 129 int io_sqes; 130 u32 db_stride; 131 void __iomem *bar; 132 unsigned long bar_mapped_size; 133 struct work_struct remove_work; 134 struct mutex shutdown_lock; 135 bool subsystem; 136 u64 cmb_size; 137 bool cmb_use_sqes; 138 u32 cmbsz; 139 u32 cmbloc; 140 struct nvme_ctrl ctrl; 141 u32 last_ps; 142 bool hmb; 143 144 mempool_t *iod_mempool; 145 146 /* shadow doorbell buffer support: */ 147 u32 *dbbuf_dbs; 148 dma_addr_t dbbuf_dbs_dma_addr; 149 u32 *dbbuf_eis; 150 dma_addr_t dbbuf_eis_dma_addr; 151 152 /* host memory buffer support: */ 153 u64 host_mem_size; 154 u32 nr_host_mem_descs; 155 dma_addr_t host_mem_descs_dma; 156 struct nvme_host_mem_buf_desc *host_mem_descs; 157 void **host_mem_desc_bufs; 158 unsigned int nr_allocated_queues; 159 unsigned int nr_write_queues; 160 unsigned int nr_poll_queues; 161 162 bool attrs_added; 163 }; 164 165 static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 166 { 167 return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE, 168 NVME_PCI_MAX_QUEUE_SIZE); 169 } 170 171 static inline unsigned int sq_idx(unsigned int qid, u32 stride) 172 { 173 return qid * 2 * stride; 174 } 175 176 static inline unsigned int cq_idx(unsigned int qid, u32 stride) 177 { 178 return (qid * 2 + 1) * stride; 179 } 180 181 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 182 { 183 return container_of(ctrl, struct nvme_dev, ctrl); 184 } 185 186 /* 187 * An NVM Express queue. Each device has at least two (one for admin 188 * commands and one for I/O commands). 189 */ 190 struct nvme_queue { 191 struct nvme_dev *dev; 192 spinlock_t sq_lock; 193 void *sq_cmds; 194 /* only used for poll queues: */ 195 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; 196 struct nvme_completion *cqes; 197 dma_addr_t sq_dma_addr; 198 dma_addr_t cq_dma_addr; 199 u32 __iomem *q_db; 200 u32 q_depth; 201 u16 cq_vector; 202 u16 sq_tail; 203 u16 last_sq_tail; 204 u16 cq_head; 205 u16 qid; 206 u8 cq_phase; 207 u8 sqes; 208 unsigned long flags; 209 #define NVMEQ_ENABLED 0 210 #define NVMEQ_SQ_CMB 1 211 #define NVMEQ_DELETE_ERROR 2 212 #define NVMEQ_POLLED 3 213 u32 *dbbuf_sq_db; 214 u32 *dbbuf_cq_db; 215 u32 *dbbuf_sq_ei; 216 u32 *dbbuf_cq_ei; 217 struct completion delete_done; 218 }; 219 220 /* 221 * The nvme_iod describes the data in an I/O. 222 * 223 * The sg pointer contains the list of PRP/SGL chunk allocations in addition 224 * to the actual struct scatterlist. 225 */ 226 struct nvme_iod { 227 struct nvme_request req; 228 struct nvme_command cmd; 229 bool use_sgl; 230 bool aborted; 231 s8 nr_allocations; /* PRP list pool allocations. 0 means small 232 pool in use */ 233 unsigned int dma_len; /* length of single DMA segment mapping */ 234 dma_addr_t first_dma; 235 dma_addr_t meta_dma; 236 struct sg_table sgt; 237 }; 238 239 static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev) 240 { 241 return dev->nr_allocated_queues * 8 * dev->db_stride; 242 } 243 244 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 245 { 246 unsigned int mem_size = nvme_dbbuf_size(dev); 247 248 if (dev->dbbuf_dbs) { 249 /* 250 * Clear the dbbuf memory so the driver doesn't observe stale 251 * values from the previous instantiation. 252 */ 253 memset(dev->dbbuf_dbs, 0, mem_size); 254 memset(dev->dbbuf_eis, 0, mem_size); 255 return 0; 256 } 257 258 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 259 &dev->dbbuf_dbs_dma_addr, 260 GFP_KERNEL); 261 if (!dev->dbbuf_dbs) 262 return -ENOMEM; 263 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 264 &dev->dbbuf_eis_dma_addr, 265 GFP_KERNEL); 266 if (!dev->dbbuf_eis) { 267 dma_free_coherent(dev->dev, mem_size, 268 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 269 dev->dbbuf_dbs = NULL; 270 return -ENOMEM; 271 } 272 273 return 0; 274 } 275 276 static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 277 { 278 unsigned int mem_size = nvme_dbbuf_size(dev); 279 280 if (dev->dbbuf_dbs) { 281 dma_free_coherent(dev->dev, mem_size, 282 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 283 dev->dbbuf_dbs = NULL; 284 } 285 if (dev->dbbuf_eis) { 286 dma_free_coherent(dev->dev, mem_size, 287 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 288 dev->dbbuf_eis = NULL; 289 } 290 } 291 292 static void nvme_dbbuf_init(struct nvme_dev *dev, 293 struct nvme_queue *nvmeq, int qid) 294 { 295 if (!dev->dbbuf_dbs || !qid) 296 return; 297 298 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 299 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 300 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 301 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 302 } 303 304 static void nvme_dbbuf_free(struct nvme_queue *nvmeq) 305 { 306 if (!nvmeq->qid) 307 return; 308 309 nvmeq->dbbuf_sq_db = NULL; 310 nvmeq->dbbuf_cq_db = NULL; 311 nvmeq->dbbuf_sq_ei = NULL; 312 nvmeq->dbbuf_cq_ei = NULL; 313 } 314 315 static void nvme_dbbuf_set(struct nvme_dev *dev) 316 { 317 struct nvme_command c = { }; 318 unsigned int i; 319 320 if (!dev->dbbuf_dbs) 321 return; 322 323 c.dbbuf.opcode = nvme_admin_dbbuf; 324 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 325 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 326 327 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 328 dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 329 /* Free memory and continue on */ 330 nvme_dbbuf_dma_free(dev); 331 332 for (i = 1; i <= dev->online_queues; i++) 333 nvme_dbbuf_free(&dev->queues[i]); 334 } 335 } 336 337 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 338 { 339 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 340 } 341 342 /* Update dbbuf and return true if an MMIO is required */ 343 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 344 volatile u32 *dbbuf_ei) 345 { 346 if (dbbuf_db) { 347 u16 old_value; 348 349 /* 350 * Ensure that the queue is written before updating 351 * the doorbell in memory 352 */ 353 wmb(); 354 355 old_value = *dbbuf_db; 356 *dbbuf_db = value; 357 358 /* 359 * Ensure that the doorbell is updated before reading the event 360 * index from memory. The controller needs to provide similar 361 * ordering to ensure the envent index is updated before reading 362 * the doorbell. 363 */ 364 mb(); 365 366 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 367 return false; 368 } 369 370 return true; 371 } 372 373 /* 374 * Will slightly overestimate the number of pages needed. This is OK 375 * as it only leads to a small amount of wasted memory for the lifetime of 376 * the I/O. 377 */ 378 static int nvme_pci_npages_prp(void) 379 { 380 unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE, 381 NVME_CTRL_PAGE_SIZE); 382 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 383 } 384 385 /* 386 * Calculates the number of pages needed for the SGL segments. For example a 4k 387 * page can accommodate 256 SGL descriptors. 388 */ 389 static int nvme_pci_npages_sgl(void) 390 { 391 return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc), 392 PAGE_SIZE); 393 } 394 395 static size_t nvme_pci_iod_alloc_size(void) 396 { 397 size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl()); 398 399 return sizeof(__le64 *) * npages + 400 sizeof(struct scatterlist) * NVME_MAX_SEGS; 401 } 402 403 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 404 unsigned int hctx_idx) 405 { 406 struct nvme_dev *dev = data; 407 struct nvme_queue *nvmeq = &dev->queues[0]; 408 409 WARN_ON(hctx_idx != 0); 410 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 411 412 hctx->driver_data = nvmeq; 413 return 0; 414 } 415 416 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 417 unsigned int hctx_idx) 418 { 419 struct nvme_dev *dev = data; 420 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 421 422 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 423 hctx->driver_data = nvmeq; 424 return 0; 425 } 426 427 static int nvme_pci_init_request(struct blk_mq_tag_set *set, 428 struct request *req, unsigned int hctx_idx, 429 unsigned int numa_node) 430 { 431 struct nvme_dev *dev = set->driver_data; 432 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 433 434 nvme_req(req)->ctrl = &dev->ctrl; 435 nvme_req(req)->cmd = &iod->cmd; 436 return 0; 437 } 438 439 static int queue_irq_offset(struct nvme_dev *dev) 440 { 441 /* if we have more than 1 vec, admin queue offsets us by 1 */ 442 if (dev->num_vecs > 1) 443 return 1; 444 445 return 0; 446 } 447 448 static void nvme_pci_map_queues(struct blk_mq_tag_set *set) 449 { 450 struct nvme_dev *dev = set->driver_data; 451 int i, qoff, offset; 452 453 offset = queue_irq_offset(dev); 454 for (i = 0, qoff = 0; i < set->nr_maps; i++) { 455 struct blk_mq_queue_map *map = &set->map[i]; 456 457 map->nr_queues = dev->io_queues[i]; 458 if (!map->nr_queues) { 459 BUG_ON(i == HCTX_TYPE_DEFAULT); 460 continue; 461 } 462 463 /* 464 * The poll queue(s) doesn't have an IRQ (and hence IRQ 465 * affinity), so use the regular blk-mq cpu mapping 466 */ 467 map->queue_offset = qoff; 468 if (i != HCTX_TYPE_POLL && offset) 469 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 470 else 471 blk_mq_map_queues(map); 472 qoff += map->nr_queues; 473 offset += map->nr_queues; 474 } 475 } 476 477 /* 478 * Write sq tail if we are asked to, or if the next command would wrap. 479 */ 480 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) 481 { 482 if (!write_sq) { 483 u16 next_tail = nvmeq->sq_tail + 1; 484 485 if (next_tail == nvmeq->q_depth) 486 next_tail = 0; 487 if (next_tail != nvmeq->last_sq_tail) 488 return; 489 } 490 491 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 492 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 493 writel(nvmeq->sq_tail, nvmeq->q_db); 494 nvmeq->last_sq_tail = nvmeq->sq_tail; 495 } 496 497 static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq, 498 struct nvme_command *cmd) 499 { 500 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes), 501 absolute_pointer(cmd), sizeof(*cmd)); 502 if (++nvmeq->sq_tail == nvmeq->q_depth) 503 nvmeq->sq_tail = 0; 504 } 505 506 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 507 { 508 struct nvme_queue *nvmeq = hctx->driver_data; 509 510 spin_lock(&nvmeq->sq_lock); 511 if (nvmeq->sq_tail != nvmeq->last_sq_tail) 512 nvme_write_sq_db(nvmeq, true); 513 spin_unlock(&nvmeq->sq_lock); 514 } 515 516 static void **nvme_pci_iod_list(struct request *req) 517 { 518 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 519 return (void **)(iod->sgt.sgl + blk_rq_nr_phys_segments(req)); 520 } 521 522 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 523 { 524 struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 525 int nseg = blk_rq_nr_phys_segments(req); 526 unsigned int avg_seg_size; 527 528 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 529 530 if (!nvme_ctrl_sgl_supported(&dev->ctrl)) 531 return false; 532 if (!nvmeq->qid) 533 return false; 534 if (!sgl_threshold || avg_seg_size < sgl_threshold) 535 return false; 536 return true; 537 } 538 539 static void nvme_free_prps(struct nvme_dev *dev, struct request *req) 540 { 541 const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1; 542 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 543 dma_addr_t dma_addr = iod->first_dma; 544 int i; 545 546 for (i = 0; i < iod->nr_allocations; i++) { 547 __le64 *prp_list = nvme_pci_iod_list(req)[i]; 548 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]); 549 550 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr); 551 dma_addr = next_dma_addr; 552 } 553 } 554 555 static void nvme_free_sgls(struct nvme_dev *dev, struct request *req) 556 { 557 const int last_sg = SGES_PER_PAGE - 1; 558 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 559 dma_addr_t dma_addr = iod->first_dma; 560 int i; 561 562 for (i = 0; i < iod->nr_allocations; i++) { 563 struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i]; 564 dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr); 565 566 dma_pool_free(dev->prp_page_pool, sg_list, dma_addr); 567 dma_addr = next_dma_addr; 568 } 569 } 570 571 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 572 { 573 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 574 575 if (iod->dma_len) { 576 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len, 577 rq_dma_dir(req)); 578 return; 579 } 580 581 WARN_ON_ONCE(!iod->sgt.nents); 582 583 dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0); 584 585 if (iod->nr_allocations == 0) 586 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 587 iod->first_dma); 588 else if (iod->use_sgl) 589 nvme_free_sgls(dev, req); 590 else 591 nvme_free_prps(dev, req); 592 mempool_free(iod->sgt.sgl, dev->iod_mempool); 593 } 594 595 static void nvme_print_sgl(struct scatterlist *sgl, int nents) 596 { 597 int i; 598 struct scatterlist *sg; 599 600 for_each_sg(sgl, sg, nents, i) { 601 dma_addr_t phys = sg_phys(sg); 602 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 603 "dma_address:%pad dma_length:%d\n", 604 i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 605 sg_dma_len(sg)); 606 } 607 } 608 609 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 610 struct request *req, struct nvme_rw_command *cmnd) 611 { 612 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 613 struct dma_pool *pool; 614 int length = blk_rq_payload_bytes(req); 615 struct scatterlist *sg = iod->sgt.sgl; 616 int dma_len = sg_dma_len(sg); 617 u64 dma_addr = sg_dma_address(sg); 618 int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1); 619 __le64 *prp_list; 620 void **list = nvme_pci_iod_list(req); 621 dma_addr_t prp_dma; 622 int nprps, i; 623 624 length -= (NVME_CTRL_PAGE_SIZE - offset); 625 if (length <= 0) { 626 iod->first_dma = 0; 627 goto done; 628 } 629 630 dma_len -= (NVME_CTRL_PAGE_SIZE - offset); 631 if (dma_len) { 632 dma_addr += (NVME_CTRL_PAGE_SIZE - offset); 633 } else { 634 sg = sg_next(sg); 635 dma_addr = sg_dma_address(sg); 636 dma_len = sg_dma_len(sg); 637 } 638 639 if (length <= NVME_CTRL_PAGE_SIZE) { 640 iod->first_dma = dma_addr; 641 goto done; 642 } 643 644 nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE); 645 if (nprps <= (256 / 8)) { 646 pool = dev->prp_small_pool; 647 iod->nr_allocations = 0; 648 } else { 649 pool = dev->prp_page_pool; 650 iod->nr_allocations = 1; 651 } 652 653 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 654 if (!prp_list) { 655 iod->nr_allocations = -1; 656 return BLK_STS_RESOURCE; 657 } 658 list[0] = prp_list; 659 iod->first_dma = prp_dma; 660 i = 0; 661 for (;;) { 662 if (i == NVME_CTRL_PAGE_SIZE >> 3) { 663 __le64 *old_prp_list = prp_list; 664 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 665 if (!prp_list) 666 goto free_prps; 667 list[iod->nr_allocations++] = prp_list; 668 prp_list[0] = old_prp_list[i - 1]; 669 old_prp_list[i - 1] = cpu_to_le64(prp_dma); 670 i = 1; 671 } 672 prp_list[i++] = cpu_to_le64(dma_addr); 673 dma_len -= NVME_CTRL_PAGE_SIZE; 674 dma_addr += NVME_CTRL_PAGE_SIZE; 675 length -= NVME_CTRL_PAGE_SIZE; 676 if (length <= 0) 677 break; 678 if (dma_len > 0) 679 continue; 680 if (unlikely(dma_len < 0)) 681 goto bad_sgl; 682 sg = sg_next(sg); 683 dma_addr = sg_dma_address(sg); 684 dma_len = sg_dma_len(sg); 685 } 686 done: 687 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sgt.sgl)); 688 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 689 return BLK_STS_OK; 690 free_prps: 691 nvme_free_prps(dev, req); 692 return BLK_STS_RESOURCE; 693 bad_sgl: 694 WARN(DO_ONCE(nvme_print_sgl, iod->sgt.sgl, iod->sgt.nents), 695 "Invalid SGL for payload:%d nents:%d\n", 696 blk_rq_payload_bytes(req), iod->sgt.nents); 697 return BLK_STS_IOERR; 698 } 699 700 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 701 struct scatterlist *sg) 702 { 703 sge->addr = cpu_to_le64(sg_dma_address(sg)); 704 sge->length = cpu_to_le32(sg_dma_len(sg)); 705 sge->type = NVME_SGL_FMT_DATA_DESC << 4; 706 } 707 708 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 709 dma_addr_t dma_addr, int entries) 710 { 711 sge->addr = cpu_to_le64(dma_addr); 712 if (entries < SGES_PER_PAGE) { 713 sge->length = cpu_to_le32(entries * sizeof(*sge)); 714 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 715 } else { 716 sge->length = cpu_to_le32(PAGE_SIZE); 717 sge->type = NVME_SGL_FMT_SEG_DESC << 4; 718 } 719 } 720 721 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 722 struct request *req, struct nvme_rw_command *cmd) 723 { 724 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 725 struct dma_pool *pool; 726 struct nvme_sgl_desc *sg_list; 727 struct scatterlist *sg = iod->sgt.sgl; 728 unsigned int entries = iod->sgt.nents; 729 dma_addr_t sgl_dma; 730 int i = 0; 731 732 /* setting the transfer type as SGL */ 733 cmd->flags = NVME_CMD_SGL_METABUF; 734 735 if (entries == 1) { 736 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 737 return BLK_STS_OK; 738 } 739 740 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 741 pool = dev->prp_small_pool; 742 iod->nr_allocations = 0; 743 } else { 744 pool = dev->prp_page_pool; 745 iod->nr_allocations = 1; 746 } 747 748 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 749 if (!sg_list) { 750 iod->nr_allocations = -1; 751 return BLK_STS_RESOURCE; 752 } 753 754 nvme_pci_iod_list(req)[0] = sg_list; 755 iod->first_dma = sgl_dma; 756 757 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 758 759 do { 760 if (i == SGES_PER_PAGE) { 761 struct nvme_sgl_desc *old_sg_desc = sg_list; 762 struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 763 764 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 765 if (!sg_list) 766 goto free_sgls; 767 768 i = 0; 769 nvme_pci_iod_list(req)[iod->nr_allocations++] = sg_list; 770 sg_list[i++] = *link; 771 nvme_pci_sgl_set_seg(link, sgl_dma, entries); 772 } 773 774 nvme_pci_sgl_set_data(&sg_list[i++], sg); 775 sg = sg_next(sg); 776 } while (--entries > 0); 777 778 return BLK_STS_OK; 779 free_sgls: 780 nvme_free_sgls(dev, req); 781 return BLK_STS_RESOURCE; 782 } 783 784 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev, 785 struct request *req, struct nvme_rw_command *cmnd, 786 struct bio_vec *bv) 787 { 788 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 789 unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1); 790 unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset; 791 792 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 793 if (dma_mapping_error(dev->dev, iod->first_dma)) 794 return BLK_STS_RESOURCE; 795 iod->dma_len = bv->bv_len; 796 797 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma); 798 if (bv->bv_len > first_prp_len) 799 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len); 800 else 801 cmnd->dptr.prp2 = 0; 802 return BLK_STS_OK; 803 } 804 805 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev, 806 struct request *req, struct nvme_rw_command *cmnd, 807 struct bio_vec *bv) 808 { 809 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 810 811 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 812 if (dma_mapping_error(dev->dev, iod->first_dma)) 813 return BLK_STS_RESOURCE; 814 iod->dma_len = bv->bv_len; 815 816 cmnd->flags = NVME_CMD_SGL_METABUF; 817 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma); 818 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len); 819 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4; 820 return BLK_STS_OK; 821 } 822 823 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 824 struct nvme_command *cmnd) 825 { 826 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 827 blk_status_t ret = BLK_STS_RESOURCE; 828 int rc; 829 830 if (blk_rq_nr_phys_segments(req) == 1) { 831 struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 832 struct bio_vec bv = req_bvec(req); 833 834 if (!is_pci_p2pdma_page(bv.bv_page)) { 835 if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2) 836 return nvme_setup_prp_simple(dev, req, 837 &cmnd->rw, &bv); 838 839 if (nvmeq->qid && sgl_threshold && 840 nvme_ctrl_sgl_supported(&dev->ctrl)) 841 return nvme_setup_sgl_simple(dev, req, 842 &cmnd->rw, &bv); 843 } 844 } 845 846 iod->dma_len = 0; 847 iod->sgt.sgl = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 848 if (!iod->sgt.sgl) 849 return BLK_STS_RESOURCE; 850 sg_init_table(iod->sgt.sgl, blk_rq_nr_phys_segments(req)); 851 iod->sgt.orig_nents = blk_rq_map_sg(req->q, req, iod->sgt.sgl); 852 if (!iod->sgt.orig_nents) 853 goto out_free_sg; 854 855 rc = dma_map_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 856 DMA_ATTR_NO_WARN); 857 if (rc) { 858 if (rc == -EREMOTEIO) 859 ret = BLK_STS_TARGET; 860 goto out_free_sg; 861 } 862 863 iod->use_sgl = nvme_pci_use_sgls(dev, req); 864 if (iod->use_sgl) 865 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw); 866 else 867 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 868 if (ret != BLK_STS_OK) 869 goto out_unmap_sg; 870 return BLK_STS_OK; 871 872 out_unmap_sg: 873 dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0); 874 out_free_sg: 875 mempool_free(iod->sgt.sgl, dev->iod_mempool); 876 return ret; 877 } 878 879 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req, 880 struct nvme_command *cmnd) 881 { 882 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 883 884 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req), 885 rq_dma_dir(req), 0); 886 if (dma_mapping_error(dev->dev, iod->meta_dma)) 887 return BLK_STS_IOERR; 888 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma); 889 return BLK_STS_OK; 890 } 891 892 static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req) 893 { 894 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 895 blk_status_t ret; 896 897 iod->aborted = false; 898 iod->nr_allocations = -1; 899 iod->sgt.nents = 0; 900 901 ret = nvme_setup_cmd(req->q->queuedata, req); 902 if (ret) 903 return ret; 904 905 if (blk_rq_nr_phys_segments(req)) { 906 ret = nvme_map_data(dev, req, &iod->cmd); 907 if (ret) 908 goto out_free_cmd; 909 } 910 911 if (blk_integrity_rq(req)) { 912 ret = nvme_map_metadata(dev, req, &iod->cmd); 913 if (ret) 914 goto out_unmap_data; 915 } 916 917 blk_mq_start_request(req); 918 return BLK_STS_OK; 919 out_unmap_data: 920 nvme_unmap_data(dev, req); 921 out_free_cmd: 922 nvme_cleanup_cmd(req); 923 return ret; 924 } 925 926 /* 927 * NOTE: ns is NULL when called on the admin queue. 928 */ 929 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 930 const struct blk_mq_queue_data *bd) 931 { 932 struct nvme_queue *nvmeq = hctx->driver_data; 933 struct nvme_dev *dev = nvmeq->dev; 934 struct request *req = bd->rq; 935 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 936 blk_status_t ret; 937 938 /* 939 * We should not need to do this, but we're still using this to 940 * ensure we can drain requests on a dying queue. 941 */ 942 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 943 return BLK_STS_IOERR; 944 945 if (unlikely(!nvme_check_ready(&dev->ctrl, req, true))) 946 return nvme_fail_nonready_command(&dev->ctrl, req); 947 948 ret = nvme_prep_rq(dev, req); 949 if (unlikely(ret)) 950 return ret; 951 spin_lock(&nvmeq->sq_lock); 952 nvme_sq_copy_cmd(nvmeq, &iod->cmd); 953 nvme_write_sq_db(nvmeq, bd->last); 954 spin_unlock(&nvmeq->sq_lock); 955 return BLK_STS_OK; 956 } 957 958 static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct request **rqlist) 959 { 960 spin_lock(&nvmeq->sq_lock); 961 while (!rq_list_empty(*rqlist)) { 962 struct request *req = rq_list_pop(rqlist); 963 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 964 965 nvme_sq_copy_cmd(nvmeq, &iod->cmd); 966 } 967 nvme_write_sq_db(nvmeq, true); 968 spin_unlock(&nvmeq->sq_lock); 969 } 970 971 static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req) 972 { 973 /* 974 * We should not need to do this, but we're still using this to 975 * ensure we can drain requests on a dying queue. 976 */ 977 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 978 return false; 979 if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true))) 980 return false; 981 982 req->mq_hctx->tags->rqs[req->tag] = req; 983 return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK; 984 } 985 986 static void nvme_queue_rqs(struct request **rqlist) 987 { 988 struct request *req, *next, *prev = NULL; 989 struct request *requeue_list = NULL; 990 991 rq_list_for_each_safe(rqlist, req, next) { 992 struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 993 994 if (!nvme_prep_rq_batch(nvmeq, req)) { 995 /* detach 'req' and add to remainder list */ 996 rq_list_move(rqlist, &requeue_list, req, prev); 997 998 req = prev; 999 if (!req) 1000 continue; 1001 } 1002 1003 if (!next || req->mq_hctx != next->mq_hctx) { 1004 /* detach rest of list, and submit */ 1005 req->rq_next = NULL; 1006 nvme_submit_cmds(nvmeq, rqlist); 1007 *rqlist = next; 1008 prev = NULL; 1009 } else 1010 prev = req; 1011 } 1012 1013 *rqlist = requeue_list; 1014 } 1015 1016 static __always_inline void nvme_pci_unmap_rq(struct request *req) 1017 { 1018 struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 1019 struct nvme_dev *dev = nvmeq->dev; 1020 1021 if (blk_integrity_rq(req)) { 1022 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1023 1024 dma_unmap_page(dev->dev, iod->meta_dma, 1025 rq_integrity_vec(req)->bv_len, rq_data_dir(req)); 1026 } 1027 1028 if (blk_rq_nr_phys_segments(req)) 1029 nvme_unmap_data(dev, req); 1030 } 1031 1032 static void nvme_pci_complete_rq(struct request *req) 1033 { 1034 nvme_pci_unmap_rq(req); 1035 nvme_complete_rq(req); 1036 } 1037 1038 static void nvme_pci_complete_batch(struct io_comp_batch *iob) 1039 { 1040 nvme_complete_batch(iob, nvme_pci_unmap_rq); 1041 } 1042 1043 /* We read the CQE phase first to check if the rest of the entry is valid */ 1044 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 1045 { 1046 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head]; 1047 1048 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase; 1049 } 1050 1051 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 1052 { 1053 u16 head = nvmeq->cq_head; 1054 1055 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 1056 nvmeq->dbbuf_cq_ei)) 1057 writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 1058 } 1059 1060 static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq) 1061 { 1062 if (!nvmeq->qid) 1063 return nvmeq->dev->admin_tagset.tags[0]; 1064 return nvmeq->dev->tagset.tags[nvmeq->qid - 1]; 1065 } 1066 1067 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, 1068 struct io_comp_batch *iob, u16 idx) 1069 { 1070 struct nvme_completion *cqe = &nvmeq->cqes[idx]; 1071 __u16 command_id = READ_ONCE(cqe->command_id); 1072 struct request *req; 1073 1074 /* 1075 * AEN requests are special as they don't time out and can 1076 * survive any kind of queue freeze and often don't respond to 1077 * aborts. We don't even bother to allocate a struct request 1078 * for them but rather special case them here. 1079 */ 1080 if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) { 1081 nvme_complete_async_event(&nvmeq->dev->ctrl, 1082 cqe->status, &cqe->result); 1083 return; 1084 } 1085 1086 req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id); 1087 if (unlikely(!req)) { 1088 dev_warn(nvmeq->dev->ctrl.device, 1089 "invalid id %d completed on queue %d\n", 1090 command_id, le16_to_cpu(cqe->sq_id)); 1091 return; 1092 } 1093 1094 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); 1095 if (!nvme_try_complete_req(req, cqe->status, cqe->result) && 1096 !blk_mq_add_to_batch(req, iob, nvme_req(req)->status, 1097 nvme_pci_complete_batch)) 1098 nvme_pci_complete_rq(req); 1099 } 1100 1101 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 1102 { 1103 u32 tmp = nvmeq->cq_head + 1; 1104 1105 if (tmp == nvmeq->q_depth) { 1106 nvmeq->cq_head = 0; 1107 nvmeq->cq_phase ^= 1; 1108 } else { 1109 nvmeq->cq_head = tmp; 1110 } 1111 } 1112 1113 static inline int nvme_poll_cq(struct nvme_queue *nvmeq, 1114 struct io_comp_batch *iob) 1115 { 1116 int found = 0; 1117 1118 while (nvme_cqe_pending(nvmeq)) { 1119 found++; 1120 /* 1121 * load-load control dependency between phase and the rest of 1122 * the cqe requires a full read memory barrier 1123 */ 1124 dma_rmb(); 1125 nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head); 1126 nvme_update_cq_head(nvmeq); 1127 } 1128 1129 if (found) 1130 nvme_ring_cq_doorbell(nvmeq); 1131 return found; 1132 } 1133 1134 static irqreturn_t nvme_irq(int irq, void *data) 1135 { 1136 struct nvme_queue *nvmeq = data; 1137 DEFINE_IO_COMP_BATCH(iob); 1138 1139 if (nvme_poll_cq(nvmeq, &iob)) { 1140 if (!rq_list_empty(iob.req_list)) 1141 nvme_pci_complete_batch(&iob); 1142 return IRQ_HANDLED; 1143 } 1144 return IRQ_NONE; 1145 } 1146 1147 static irqreturn_t nvme_irq_check(int irq, void *data) 1148 { 1149 struct nvme_queue *nvmeq = data; 1150 1151 if (nvme_cqe_pending(nvmeq)) 1152 return IRQ_WAKE_THREAD; 1153 return IRQ_NONE; 1154 } 1155 1156 /* 1157 * Poll for completions for any interrupt driven queue 1158 * Can be called from any context. 1159 */ 1160 static void nvme_poll_irqdisable(struct nvme_queue *nvmeq) 1161 { 1162 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1163 1164 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags)); 1165 1166 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1167 nvme_poll_cq(nvmeq, NULL); 1168 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1169 } 1170 1171 static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob) 1172 { 1173 struct nvme_queue *nvmeq = hctx->driver_data; 1174 bool found; 1175 1176 if (!nvme_cqe_pending(nvmeq)) 1177 return 0; 1178 1179 spin_lock(&nvmeq->cq_poll_lock); 1180 found = nvme_poll_cq(nvmeq, iob); 1181 spin_unlock(&nvmeq->cq_poll_lock); 1182 1183 return found; 1184 } 1185 1186 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 1187 { 1188 struct nvme_dev *dev = to_nvme_dev(ctrl); 1189 struct nvme_queue *nvmeq = &dev->queues[0]; 1190 struct nvme_command c = { }; 1191 1192 c.common.opcode = nvme_admin_async_event; 1193 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 1194 1195 spin_lock(&nvmeq->sq_lock); 1196 nvme_sq_copy_cmd(nvmeq, &c); 1197 nvme_write_sq_db(nvmeq, true); 1198 spin_unlock(&nvmeq->sq_lock); 1199 } 1200 1201 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 1202 { 1203 struct nvme_command c = { }; 1204 1205 c.delete_queue.opcode = opcode; 1206 c.delete_queue.qid = cpu_to_le16(id); 1207 1208 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1209 } 1210 1211 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1212 struct nvme_queue *nvmeq, s16 vector) 1213 { 1214 struct nvme_command c = { }; 1215 int flags = NVME_QUEUE_PHYS_CONTIG; 1216 1217 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) 1218 flags |= NVME_CQ_IRQ_ENABLED; 1219 1220 /* 1221 * Note: we (ab)use the fact that the prp fields survive if no data 1222 * is attached to the request. 1223 */ 1224 c.create_cq.opcode = nvme_admin_create_cq; 1225 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 1226 c.create_cq.cqid = cpu_to_le16(qid); 1227 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 1228 c.create_cq.cq_flags = cpu_to_le16(flags); 1229 c.create_cq.irq_vector = cpu_to_le16(vector); 1230 1231 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1232 } 1233 1234 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 1235 struct nvme_queue *nvmeq) 1236 { 1237 struct nvme_ctrl *ctrl = &dev->ctrl; 1238 struct nvme_command c = { }; 1239 int flags = NVME_QUEUE_PHYS_CONTIG; 1240 1241 /* 1242 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 1243 * set. Since URGENT priority is zeroes, it makes all queues 1244 * URGENT. 1245 */ 1246 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 1247 flags |= NVME_SQ_PRIO_MEDIUM; 1248 1249 /* 1250 * Note: we (ab)use the fact that the prp fields survive if no data 1251 * is attached to the request. 1252 */ 1253 c.create_sq.opcode = nvme_admin_create_sq; 1254 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 1255 c.create_sq.sqid = cpu_to_le16(qid); 1256 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 1257 c.create_sq.sq_flags = cpu_to_le16(flags); 1258 c.create_sq.cqid = cpu_to_le16(qid); 1259 1260 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1261 } 1262 1263 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 1264 { 1265 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 1266 } 1267 1268 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 1269 { 1270 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 1271 } 1272 1273 static enum rq_end_io_ret abort_endio(struct request *req, blk_status_t error) 1274 { 1275 struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 1276 1277 dev_warn(nvmeq->dev->ctrl.device, 1278 "Abort status: 0x%x", nvme_req(req)->status); 1279 atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1280 blk_mq_free_request(req); 1281 return RQ_END_IO_NONE; 1282 } 1283 1284 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1285 { 1286 /* If true, indicates loss of adapter communication, possibly by a 1287 * NVMe Subsystem reset. 1288 */ 1289 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1290 1291 /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1292 switch (dev->ctrl.state) { 1293 case NVME_CTRL_RESETTING: 1294 case NVME_CTRL_CONNECTING: 1295 return false; 1296 default: 1297 break; 1298 } 1299 1300 /* We shouldn't reset unless the controller is on fatal error state 1301 * _or_ if we lost the communication with it. 1302 */ 1303 if (!(csts & NVME_CSTS_CFS) && !nssro) 1304 return false; 1305 1306 return true; 1307 } 1308 1309 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1310 { 1311 /* Read a config register to help see what died. */ 1312 u16 pci_status; 1313 int result; 1314 1315 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1316 &pci_status); 1317 if (result == PCIBIOS_SUCCESSFUL) 1318 dev_warn(dev->ctrl.device, 1319 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1320 csts, pci_status); 1321 else 1322 dev_warn(dev->ctrl.device, 1323 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1324 csts, result); 1325 1326 if (csts != ~0) 1327 return; 1328 1329 dev_warn(dev->ctrl.device, 1330 "Does your device have a faulty power saving mode enabled?\n"); 1331 dev_warn(dev->ctrl.device, 1332 "Try \"nvme_core.default_ps_max_latency_us=0 pcie_aspm=off\" and report a bug\n"); 1333 } 1334 1335 static enum blk_eh_timer_return nvme_timeout(struct request *req) 1336 { 1337 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1338 struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 1339 struct nvme_dev *dev = nvmeq->dev; 1340 struct request *abort_req; 1341 struct nvme_command cmd = { }; 1342 u32 csts = readl(dev->bar + NVME_REG_CSTS); 1343 1344 /* If PCI error recovery process is happening, we cannot reset or 1345 * the recovery mechanism will surely fail. 1346 */ 1347 mb(); 1348 if (pci_channel_offline(to_pci_dev(dev->dev))) 1349 return BLK_EH_RESET_TIMER; 1350 1351 /* 1352 * Reset immediately if the controller is failed 1353 */ 1354 if (nvme_should_reset(dev, csts)) { 1355 nvme_warn_reset(dev, csts); 1356 nvme_dev_disable(dev, false); 1357 nvme_reset_ctrl(&dev->ctrl); 1358 return BLK_EH_DONE; 1359 } 1360 1361 /* 1362 * Did we miss an interrupt? 1363 */ 1364 if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) 1365 nvme_poll(req->mq_hctx, NULL); 1366 else 1367 nvme_poll_irqdisable(nvmeq); 1368 1369 if (blk_mq_request_completed(req)) { 1370 dev_warn(dev->ctrl.device, 1371 "I/O %d QID %d timeout, completion polled\n", 1372 req->tag, nvmeq->qid); 1373 return BLK_EH_DONE; 1374 } 1375 1376 /* 1377 * Shutdown immediately if controller times out while starting. The 1378 * reset work will see the pci device disabled when it gets the forced 1379 * cancellation error. All outstanding requests are completed on 1380 * shutdown, so we return BLK_EH_DONE. 1381 */ 1382 switch (dev->ctrl.state) { 1383 case NVME_CTRL_CONNECTING: 1384 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 1385 fallthrough; 1386 case NVME_CTRL_DELETING: 1387 dev_warn_ratelimited(dev->ctrl.device, 1388 "I/O %d QID %d timeout, disable controller\n", 1389 req->tag, nvmeq->qid); 1390 nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1391 nvme_dev_disable(dev, true); 1392 return BLK_EH_DONE; 1393 case NVME_CTRL_RESETTING: 1394 return BLK_EH_RESET_TIMER; 1395 default: 1396 break; 1397 } 1398 1399 /* 1400 * Shutdown the controller immediately and schedule a reset if the 1401 * command was already aborted once before and still hasn't been 1402 * returned to the driver, or if this is the admin queue. 1403 */ 1404 if (!nvmeq->qid || iod->aborted) { 1405 dev_warn(dev->ctrl.device, 1406 "I/O %d QID %d timeout, reset controller\n", 1407 req->tag, nvmeq->qid); 1408 nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1409 nvme_dev_disable(dev, false); 1410 nvme_reset_ctrl(&dev->ctrl); 1411 1412 return BLK_EH_DONE; 1413 } 1414 1415 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1416 atomic_inc(&dev->ctrl.abort_limit); 1417 return BLK_EH_RESET_TIMER; 1418 } 1419 iod->aborted = true; 1420 1421 cmd.abort.opcode = nvme_admin_abort_cmd; 1422 cmd.abort.cid = nvme_cid(req); 1423 cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 1424 1425 dev_warn(nvmeq->dev->ctrl.device, 1426 "I/O %d (%s) QID %d timeout, aborting\n", 1427 req->tag, 1428 nvme_get_opcode_str(nvme_req(req)->cmd->common.opcode), 1429 nvmeq->qid); 1430 1431 abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, nvme_req_op(&cmd), 1432 BLK_MQ_REQ_NOWAIT); 1433 if (IS_ERR(abort_req)) { 1434 atomic_inc(&dev->ctrl.abort_limit); 1435 return BLK_EH_RESET_TIMER; 1436 } 1437 nvme_init_request(abort_req, &cmd); 1438 1439 abort_req->end_io = abort_endio; 1440 abort_req->end_io_data = NULL; 1441 blk_execute_rq_nowait(abort_req, false); 1442 1443 /* 1444 * The aborted req will be completed on receiving the abort req. 1445 * We enable the timer again. If hit twice, it'll cause a device reset, 1446 * as the device then is in a faulty state. 1447 */ 1448 return BLK_EH_RESET_TIMER; 1449 } 1450 1451 static void nvme_free_queue(struct nvme_queue *nvmeq) 1452 { 1453 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq), 1454 (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 1455 if (!nvmeq->sq_cmds) 1456 return; 1457 1458 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 1459 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), 1460 nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1461 } else { 1462 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq), 1463 nvmeq->sq_cmds, nvmeq->sq_dma_addr); 1464 } 1465 } 1466 1467 static void nvme_free_queues(struct nvme_dev *dev, int lowest) 1468 { 1469 int i; 1470 1471 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1472 dev->ctrl.queue_count--; 1473 nvme_free_queue(&dev->queues[i]); 1474 } 1475 } 1476 1477 /** 1478 * nvme_suspend_queue - put queue into suspended state 1479 * @nvmeq: queue to suspend 1480 */ 1481 static int nvme_suspend_queue(struct nvme_queue *nvmeq) 1482 { 1483 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 1484 return 1; 1485 1486 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1487 mb(); 1488 1489 nvmeq->dev->online_queues--; 1490 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1491 nvme_stop_admin_queue(&nvmeq->dev->ctrl); 1492 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) 1493 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq); 1494 return 0; 1495 } 1496 1497 static void nvme_suspend_io_queues(struct nvme_dev *dev) 1498 { 1499 int i; 1500 1501 for (i = dev->ctrl.queue_count - 1; i > 0; i--) 1502 nvme_suspend_queue(&dev->queues[i]); 1503 } 1504 1505 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 1506 { 1507 struct nvme_queue *nvmeq = &dev->queues[0]; 1508 1509 if (shutdown) 1510 nvme_shutdown_ctrl(&dev->ctrl); 1511 else 1512 nvme_disable_ctrl(&dev->ctrl); 1513 1514 nvme_poll_irqdisable(nvmeq); 1515 } 1516 1517 /* 1518 * Called only on a device that has been disabled and after all other threads 1519 * that can check this device's completion queues have synced, except 1520 * nvme_poll(). This is the last chance for the driver to see a natural 1521 * completion before nvme_cancel_request() terminates all incomplete requests. 1522 */ 1523 static void nvme_reap_pending_cqes(struct nvme_dev *dev) 1524 { 1525 int i; 1526 1527 for (i = dev->ctrl.queue_count - 1; i > 0; i--) { 1528 spin_lock(&dev->queues[i].cq_poll_lock); 1529 nvme_poll_cq(&dev->queues[i], NULL); 1530 spin_unlock(&dev->queues[i].cq_poll_lock); 1531 } 1532 } 1533 1534 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 1535 int entry_size) 1536 { 1537 int q_depth = dev->q_depth; 1538 unsigned q_size_aligned = roundup(q_depth * entry_size, 1539 NVME_CTRL_PAGE_SIZE); 1540 1541 if (q_size_aligned * nr_io_queues > dev->cmb_size) { 1542 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 1543 1544 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE); 1545 q_depth = div_u64(mem_per_q, entry_size); 1546 1547 /* 1548 * Ensure the reduced q_depth is above some threshold where it 1549 * would be better to map queues in system memory with the 1550 * original depth 1551 */ 1552 if (q_depth < 64) 1553 return -ENOMEM; 1554 } 1555 1556 return q_depth; 1557 } 1558 1559 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 1560 int qid) 1561 { 1562 struct pci_dev *pdev = to_pci_dev(dev->dev); 1563 1564 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 1565 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq)); 1566 if (nvmeq->sq_cmds) { 1567 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 1568 nvmeq->sq_cmds); 1569 if (nvmeq->sq_dma_addr) { 1570 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 1571 return 0; 1572 } 1573 1574 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1575 } 1576 } 1577 1578 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq), 1579 &nvmeq->sq_dma_addr, GFP_KERNEL); 1580 if (!nvmeq->sq_cmds) 1581 return -ENOMEM; 1582 return 0; 1583 } 1584 1585 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 1586 { 1587 struct nvme_queue *nvmeq = &dev->queues[qid]; 1588 1589 if (dev->ctrl.queue_count > qid) 1590 return 0; 1591 1592 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES; 1593 nvmeq->q_depth = depth; 1594 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq), 1595 &nvmeq->cq_dma_addr, GFP_KERNEL); 1596 if (!nvmeq->cqes) 1597 goto free_nvmeq; 1598 1599 if (nvme_alloc_sq_cmds(dev, nvmeq, qid)) 1600 goto free_cqdma; 1601 1602 nvmeq->dev = dev; 1603 spin_lock_init(&nvmeq->sq_lock); 1604 spin_lock_init(&nvmeq->cq_poll_lock); 1605 nvmeq->cq_head = 0; 1606 nvmeq->cq_phase = 1; 1607 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1608 nvmeq->qid = qid; 1609 dev->ctrl.queue_count++; 1610 1611 return 0; 1612 1613 free_cqdma: 1614 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes, 1615 nvmeq->cq_dma_addr); 1616 free_nvmeq: 1617 return -ENOMEM; 1618 } 1619 1620 static int queue_request_irq(struct nvme_queue *nvmeq) 1621 { 1622 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1623 int nr = nvmeq->dev->ctrl.instance; 1624 1625 if (use_threaded_interrupts) { 1626 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 1627 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 1628 } else { 1629 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 1630 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 1631 } 1632 } 1633 1634 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 1635 { 1636 struct nvme_dev *dev = nvmeq->dev; 1637 1638 nvmeq->sq_tail = 0; 1639 nvmeq->last_sq_tail = 0; 1640 nvmeq->cq_head = 0; 1641 nvmeq->cq_phase = 1; 1642 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1643 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq)); 1644 nvme_dbbuf_init(dev, nvmeq, qid); 1645 dev->online_queues++; 1646 wmb(); /* ensure the first interrupt sees the initialization */ 1647 } 1648 1649 /* 1650 * Try getting shutdown_lock while setting up IO queues. 1651 */ 1652 static int nvme_setup_io_queues_trylock(struct nvme_dev *dev) 1653 { 1654 /* 1655 * Give up if the lock is being held by nvme_dev_disable. 1656 */ 1657 if (!mutex_trylock(&dev->shutdown_lock)) 1658 return -ENODEV; 1659 1660 /* 1661 * Controller is in wrong state, fail early. 1662 */ 1663 if (dev->ctrl.state != NVME_CTRL_CONNECTING) { 1664 mutex_unlock(&dev->shutdown_lock); 1665 return -ENODEV; 1666 } 1667 1668 return 0; 1669 } 1670 1671 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 1672 { 1673 struct nvme_dev *dev = nvmeq->dev; 1674 int result; 1675 u16 vector = 0; 1676 1677 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 1678 1679 /* 1680 * A queue's vector matches the queue identifier unless the controller 1681 * has only one vector available. 1682 */ 1683 if (!polled) 1684 vector = dev->num_vecs == 1 ? 0 : qid; 1685 else 1686 set_bit(NVMEQ_POLLED, &nvmeq->flags); 1687 1688 result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1689 if (result) 1690 return result; 1691 1692 result = adapter_alloc_sq(dev, qid, nvmeq); 1693 if (result < 0) 1694 return result; 1695 if (result) 1696 goto release_cq; 1697 1698 nvmeq->cq_vector = vector; 1699 1700 result = nvme_setup_io_queues_trylock(dev); 1701 if (result) 1702 return result; 1703 nvme_init_queue(nvmeq, qid); 1704 if (!polled) { 1705 result = queue_request_irq(nvmeq); 1706 if (result < 0) 1707 goto release_sq; 1708 } 1709 1710 set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1711 mutex_unlock(&dev->shutdown_lock); 1712 return result; 1713 1714 release_sq: 1715 dev->online_queues--; 1716 mutex_unlock(&dev->shutdown_lock); 1717 adapter_delete_sq(dev, qid); 1718 release_cq: 1719 adapter_delete_cq(dev, qid); 1720 return result; 1721 } 1722 1723 static const struct blk_mq_ops nvme_mq_admin_ops = { 1724 .queue_rq = nvme_queue_rq, 1725 .complete = nvme_pci_complete_rq, 1726 .init_hctx = nvme_admin_init_hctx, 1727 .init_request = nvme_pci_init_request, 1728 .timeout = nvme_timeout, 1729 }; 1730 1731 static const struct blk_mq_ops nvme_mq_ops = { 1732 .queue_rq = nvme_queue_rq, 1733 .queue_rqs = nvme_queue_rqs, 1734 .complete = nvme_pci_complete_rq, 1735 .commit_rqs = nvme_commit_rqs, 1736 .init_hctx = nvme_init_hctx, 1737 .init_request = nvme_pci_init_request, 1738 .map_queues = nvme_pci_map_queues, 1739 .timeout = nvme_timeout, 1740 .poll = nvme_poll, 1741 }; 1742 1743 static void nvme_dev_remove_admin(struct nvme_dev *dev) 1744 { 1745 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 1746 /* 1747 * If the controller was reset during removal, it's possible 1748 * user requests may be waiting on a stopped queue. Start the 1749 * queue to flush these to completion. 1750 */ 1751 nvme_start_admin_queue(&dev->ctrl); 1752 blk_mq_destroy_queue(dev->ctrl.admin_q); 1753 blk_mq_free_tag_set(&dev->admin_tagset); 1754 } 1755 } 1756 1757 static int nvme_pci_alloc_admin_tag_set(struct nvme_dev *dev) 1758 { 1759 struct blk_mq_tag_set *set = &dev->admin_tagset; 1760 1761 set->ops = &nvme_mq_admin_ops; 1762 set->nr_hw_queues = 1; 1763 1764 set->queue_depth = NVME_AQ_MQ_TAG_DEPTH; 1765 set->timeout = NVME_ADMIN_TIMEOUT; 1766 set->numa_node = dev->ctrl.numa_node; 1767 set->cmd_size = sizeof(struct nvme_iod); 1768 set->flags = BLK_MQ_F_NO_SCHED; 1769 set->driver_data = dev; 1770 1771 if (blk_mq_alloc_tag_set(set)) 1772 return -ENOMEM; 1773 dev->ctrl.admin_tagset = set; 1774 1775 dev->ctrl.admin_q = blk_mq_init_queue(set); 1776 if (IS_ERR(dev->ctrl.admin_q)) { 1777 blk_mq_free_tag_set(set); 1778 dev->ctrl.admin_q = NULL; 1779 return -ENOMEM; 1780 } 1781 if (!blk_get_queue(dev->ctrl.admin_q)) { 1782 nvme_dev_remove_admin(dev); 1783 dev->ctrl.admin_q = NULL; 1784 return -ENODEV; 1785 } 1786 return 0; 1787 } 1788 1789 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 1790 { 1791 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 1792 } 1793 1794 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 1795 { 1796 struct pci_dev *pdev = to_pci_dev(dev->dev); 1797 1798 if (size <= dev->bar_mapped_size) 1799 return 0; 1800 if (size > pci_resource_len(pdev, 0)) 1801 return -ENOMEM; 1802 if (dev->bar) 1803 iounmap(dev->bar); 1804 dev->bar = ioremap(pci_resource_start(pdev, 0), size); 1805 if (!dev->bar) { 1806 dev->bar_mapped_size = 0; 1807 return -ENOMEM; 1808 } 1809 dev->bar_mapped_size = size; 1810 dev->dbs = dev->bar + NVME_REG_DBS; 1811 1812 return 0; 1813 } 1814 1815 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 1816 { 1817 int result; 1818 u32 aqa; 1819 struct nvme_queue *nvmeq; 1820 1821 result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 1822 if (result < 0) 1823 return result; 1824 1825 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 1826 NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 1827 1828 if (dev->subsystem && 1829 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 1830 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 1831 1832 result = nvme_disable_ctrl(&dev->ctrl); 1833 if (result < 0) 1834 return result; 1835 1836 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1837 if (result) 1838 return result; 1839 1840 dev->ctrl.numa_node = dev_to_node(dev->dev); 1841 1842 nvmeq = &dev->queues[0]; 1843 aqa = nvmeq->q_depth - 1; 1844 aqa |= aqa << 16; 1845 1846 writel(aqa, dev->bar + NVME_REG_AQA); 1847 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 1848 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 1849 1850 result = nvme_enable_ctrl(&dev->ctrl); 1851 if (result) 1852 return result; 1853 1854 nvmeq->cq_vector = 0; 1855 nvme_init_queue(nvmeq, 0); 1856 result = queue_request_irq(nvmeq); 1857 if (result) { 1858 dev->online_queues--; 1859 return result; 1860 } 1861 1862 set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1863 return result; 1864 } 1865 1866 static int nvme_create_io_queues(struct nvme_dev *dev) 1867 { 1868 unsigned i, max, rw_queues; 1869 int ret = 0; 1870 1871 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1872 if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1873 ret = -ENOMEM; 1874 break; 1875 } 1876 } 1877 1878 max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1879 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1880 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1881 dev->io_queues[HCTX_TYPE_READ]; 1882 } else { 1883 rw_queues = max; 1884 } 1885 1886 for (i = dev->online_queues; i <= max; i++) { 1887 bool polled = i > rw_queues; 1888 1889 ret = nvme_create_queue(&dev->queues[i], i, polled); 1890 if (ret) 1891 break; 1892 } 1893 1894 /* 1895 * Ignore failing Create SQ/CQ commands, we can continue with less 1896 * than the desired amount of queues, and even a controller without 1897 * I/O queues can still be used to issue admin commands. This might 1898 * be useful to upgrade a buggy firmware for example. 1899 */ 1900 return ret >= 0 ? 0 : ret; 1901 } 1902 1903 static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 1904 { 1905 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 1906 1907 return 1ULL << (12 + 4 * szu); 1908 } 1909 1910 static u32 nvme_cmb_size(struct nvme_dev *dev) 1911 { 1912 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 1913 } 1914 1915 static void nvme_map_cmb(struct nvme_dev *dev) 1916 { 1917 u64 size, offset; 1918 resource_size_t bar_size; 1919 struct pci_dev *pdev = to_pci_dev(dev->dev); 1920 int bar; 1921 1922 if (dev->cmb_size) 1923 return; 1924 1925 if (NVME_CAP_CMBS(dev->ctrl.cap)) 1926 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC); 1927 1928 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1929 if (!dev->cmbsz) 1930 return; 1931 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 1932 1933 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 1934 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 1935 bar = NVME_CMB_BIR(dev->cmbloc); 1936 bar_size = pci_resource_len(pdev, bar); 1937 1938 if (offset > bar_size) 1939 return; 1940 1941 /* 1942 * Tell the controller about the host side address mapping the CMB, 1943 * and enable CMB decoding for the NVMe 1.4+ scheme: 1944 */ 1945 if (NVME_CAP_CMBS(dev->ctrl.cap)) { 1946 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE | 1947 (pci_bus_address(pdev, bar) + offset), 1948 dev->bar + NVME_REG_CMBMSC); 1949 } 1950 1951 /* 1952 * Controllers may support a CMB size larger than their BAR, 1953 * for example, due to being behind a bridge. Reduce the CMB to 1954 * the reported size of the BAR 1955 */ 1956 if (size > bar_size - offset) 1957 size = bar_size - offset; 1958 1959 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 1960 dev_warn(dev->ctrl.device, 1961 "failed to register the CMB\n"); 1962 return; 1963 } 1964 1965 dev->cmb_size = size; 1966 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 1967 1968 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 1969 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 1970 pci_p2pmem_publish(pdev, true); 1971 } 1972 1973 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 1974 { 1975 u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT; 1976 u64 dma_addr = dev->host_mem_descs_dma; 1977 struct nvme_command c = { }; 1978 int ret; 1979 1980 c.features.opcode = nvme_admin_set_features; 1981 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 1982 c.features.dword11 = cpu_to_le32(bits); 1983 c.features.dword12 = cpu_to_le32(host_mem_size); 1984 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 1985 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 1986 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 1987 1988 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1989 if (ret) { 1990 dev_warn(dev->ctrl.device, 1991 "failed to set host mem (err %d, flags %#x).\n", 1992 ret, bits); 1993 } else 1994 dev->hmb = bits & NVME_HOST_MEM_ENABLE; 1995 1996 return ret; 1997 } 1998 1999 static void nvme_free_host_mem(struct nvme_dev *dev) 2000 { 2001 int i; 2002 2003 for (i = 0; i < dev->nr_host_mem_descs; i++) { 2004 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 2005 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE; 2006 2007 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], 2008 le64_to_cpu(desc->addr), 2009 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 2010 } 2011 2012 kfree(dev->host_mem_desc_bufs); 2013 dev->host_mem_desc_bufs = NULL; 2014 dma_free_coherent(dev->dev, 2015 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 2016 dev->host_mem_descs, dev->host_mem_descs_dma); 2017 dev->host_mem_descs = NULL; 2018 dev->nr_host_mem_descs = 0; 2019 } 2020 2021 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 2022 u32 chunk_size) 2023 { 2024 struct nvme_host_mem_buf_desc *descs; 2025 u32 max_entries, len; 2026 dma_addr_t descs_dma; 2027 int i = 0; 2028 void **bufs; 2029 u64 size, tmp; 2030 2031 tmp = (preferred + chunk_size - 1); 2032 do_div(tmp, chunk_size); 2033 max_entries = tmp; 2034 2035 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 2036 max_entries = dev->ctrl.hmmaxd; 2037 2038 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), 2039 &descs_dma, GFP_KERNEL); 2040 if (!descs) 2041 goto out; 2042 2043 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 2044 if (!bufs) 2045 goto out_free_descs; 2046 2047 for (size = 0; size < preferred && i < max_entries; size += len) { 2048 dma_addr_t dma_addr; 2049 2050 len = min_t(u64, chunk_size, preferred - size); 2051 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 2052 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 2053 if (!bufs[i]) 2054 break; 2055 2056 descs[i].addr = cpu_to_le64(dma_addr); 2057 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE); 2058 i++; 2059 } 2060 2061 if (!size) 2062 goto out_free_bufs; 2063 2064 dev->nr_host_mem_descs = i; 2065 dev->host_mem_size = size; 2066 dev->host_mem_descs = descs; 2067 dev->host_mem_descs_dma = descs_dma; 2068 dev->host_mem_desc_bufs = bufs; 2069 return 0; 2070 2071 out_free_bufs: 2072 while (--i >= 0) { 2073 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE; 2074 2075 dma_free_attrs(dev->dev, size, bufs[i], 2076 le64_to_cpu(descs[i].addr), 2077 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 2078 } 2079 2080 kfree(bufs); 2081 out_free_descs: 2082 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 2083 descs_dma); 2084 out: 2085 dev->host_mem_descs = NULL; 2086 return -ENOMEM; 2087 } 2088 2089 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 2090 { 2091 u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 2092 u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 2093 u64 chunk_size; 2094 2095 /* start big and work our way down */ 2096 for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) { 2097 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 2098 if (!min || dev->host_mem_size >= min) 2099 return 0; 2100 nvme_free_host_mem(dev); 2101 } 2102 } 2103 2104 return -ENOMEM; 2105 } 2106 2107 static int nvme_setup_host_mem(struct nvme_dev *dev) 2108 { 2109 u64 max = (u64)max_host_mem_size_mb * SZ_1M; 2110 u64 preferred = (u64)dev->ctrl.hmpre * 4096; 2111 u64 min = (u64)dev->ctrl.hmmin * 4096; 2112 u32 enable_bits = NVME_HOST_MEM_ENABLE; 2113 int ret; 2114 2115 preferred = min(preferred, max); 2116 if (min > max) { 2117 dev_warn(dev->ctrl.device, 2118 "min host memory (%lld MiB) above limit (%d MiB).\n", 2119 min >> ilog2(SZ_1M), max_host_mem_size_mb); 2120 nvme_free_host_mem(dev); 2121 return 0; 2122 } 2123 2124 /* 2125 * If we already have a buffer allocated check if we can reuse it. 2126 */ 2127 if (dev->host_mem_descs) { 2128 if (dev->host_mem_size >= min) 2129 enable_bits |= NVME_HOST_MEM_RETURN; 2130 else 2131 nvme_free_host_mem(dev); 2132 } 2133 2134 if (!dev->host_mem_descs) { 2135 if (nvme_alloc_host_mem(dev, min, preferred)) { 2136 dev_warn(dev->ctrl.device, 2137 "failed to allocate host memory buffer.\n"); 2138 return 0; /* controller must work without HMB */ 2139 } 2140 2141 dev_info(dev->ctrl.device, 2142 "allocated %lld MiB host memory buffer.\n", 2143 dev->host_mem_size >> ilog2(SZ_1M)); 2144 } 2145 2146 ret = nvme_set_host_mem(dev, enable_bits); 2147 if (ret) 2148 nvme_free_host_mem(dev); 2149 return ret; 2150 } 2151 2152 static ssize_t cmb_show(struct device *dev, struct device_attribute *attr, 2153 char *buf) 2154 { 2155 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2156 2157 return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz : x%08x\n", 2158 ndev->cmbloc, ndev->cmbsz); 2159 } 2160 static DEVICE_ATTR_RO(cmb); 2161 2162 static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr, 2163 char *buf) 2164 { 2165 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2166 2167 return sysfs_emit(buf, "%u\n", ndev->cmbloc); 2168 } 2169 static DEVICE_ATTR_RO(cmbloc); 2170 2171 static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr, 2172 char *buf) 2173 { 2174 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2175 2176 return sysfs_emit(buf, "%u\n", ndev->cmbsz); 2177 } 2178 static DEVICE_ATTR_RO(cmbsz); 2179 2180 static ssize_t hmb_show(struct device *dev, struct device_attribute *attr, 2181 char *buf) 2182 { 2183 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2184 2185 return sysfs_emit(buf, "%d\n", ndev->hmb); 2186 } 2187 2188 static ssize_t hmb_store(struct device *dev, struct device_attribute *attr, 2189 const char *buf, size_t count) 2190 { 2191 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2192 bool new; 2193 int ret; 2194 2195 if (strtobool(buf, &new) < 0) 2196 return -EINVAL; 2197 2198 if (new == ndev->hmb) 2199 return count; 2200 2201 if (new) { 2202 ret = nvme_setup_host_mem(ndev); 2203 } else { 2204 ret = nvme_set_host_mem(ndev, 0); 2205 if (!ret) 2206 nvme_free_host_mem(ndev); 2207 } 2208 2209 if (ret < 0) 2210 return ret; 2211 2212 return count; 2213 } 2214 static DEVICE_ATTR_RW(hmb); 2215 2216 static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj, 2217 struct attribute *a, int n) 2218 { 2219 struct nvme_ctrl *ctrl = 2220 dev_get_drvdata(container_of(kobj, struct device, kobj)); 2221 struct nvme_dev *dev = to_nvme_dev(ctrl); 2222 2223 if (a == &dev_attr_cmb.attr || 2224 a == &dev_attr_cmbloc.attr || 2225 a == &dev_attr_cmbsz.attr) { 2226 if (!dev->cmbsz) 2227 return 0; 2228 } 2229 if (a == &dev_attr_hmb.attr && !ctrl->hmpre) 2230 return 0; 2231 2232 return a->mode; 2233 } 2234 2235 static struct attribute *nvme_pci_attrs[] = { 2236 &dev_attr_cmb.attr, 2237 &dev_attr_cmbloc.attr, 2238 &dev_attr_cmbsz.attr, 2239 &dev_attr_hmb.attr, 2240 NULL, 2241 }; 2242 2243 static const struct attribute_group nvme_pci_attr_group = { 2244 .attrs = nvme_pci_attrs, 2245 .is_visible = nvme_pci_attrs_are_visible, 2246 }; 2247 2248 /* 2249 * nirqs is the number of interrupts available for write and read 2250 * queues. The core already reserved an interrupt for the admin queue. 2251 */ 2252 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) 2253 { 2254 struct nvme_dev *dev = affd->priv; 2255 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues; 2256 2257 /* 2258 * If there is no interrupt available for queues, ensure that 2259 * the default queue is set to 1. The affinity set size is 2260 * also set to one, but the irq core ignores it for this case. 2261 * 2262 * If only one interrupt is available or 'write_queue' == 0, combine 2263 * write and read queues. 2264 * 2265 * If 'write_queues' > 0, ensure it leaves room for at least one read 2266 * queue. 2267 */ 2268 if (!nrirqs) { 2269 nrirqs = 1; 2270 nr_read_queues = 0; 2271 } else if (nrirqs == 1 || !nr_write_queues) { 2272 nr_read_queues = 0; 2273 } else if (nr_write_queues >= nrirqs) { 2274 nr_read_queues = 1; 2275 } else { 2276 nr_read_queues = nrirqs - nr_write_queues; 2277 } 2278 2279 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2280 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2281 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; 2282 affd->set_size[HCTX_TYPE_READ] = nr_read_queues; 2283 affd->nr_sets = nr_read_queues ? 2 : 1; 2284 } 2285 2286 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) 2287 { 2288 struct pci_dev *pdev = to_pci_dev(dev->dev); 2289 struct irq_affinity affd = { 2290 .pre_vectors = 1, 2291 .calc_sets = nvme_calc_irq_sets, 2292 .priv = dev, 2293 }; 2294 unsigned int irq_queues, poll_queues; 2295 2296 /* 2297 * Poll queues don't need interrupts, but we need at least one I/O queue 2298 * left over for non-polled I/O. 2299 */ 2300 poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1); 2301 dev->io_queues[HCTX_TYPE_POLL] = poll_queues; 2302 2303 /* 2304 * Initialize for the single interrupt case, will be updated in 2305 * nvme_calc_irq_sets(). 2306 */ 2307 dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2308 dev->io_queues[HCTX_TYPE_READ] = 0; 2309 2310 /* 2311 * We need interrupts for the admin queue and each non-polled I/O queue, 2312 * but some Apple controllers require all queues to use the first 2313 * vector. 2314 */ 2315 irq_queues = 1; 2316 if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR)) 2317 irq_queues += (nr_io_queues - poll_queues); 2318 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, 2319 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 2320 } 2321 2322 static void nvme_disable_io_queues(struct nvme_dev *dev) 2323 { 2324 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq)) 2325 __nvme_disable_io_queues(dev, nvme_admin_delete_cq); 2326 } 2327 2328 static unsigned int nvme_max_io_queues(struct nvme_dev *dev) 2329 { 2330 /* 2331 * If tags are shared with admin queue (Apple bug), then 2332 * make sure we only use one IO queue. 2333 */ 2334 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2335 return 1; 2336 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues; 2337 } 2338 2339 static int nvme_setup_io_queues(struct nvme_dev *dev) 2340 { 2341 struct nvme_queue *adminq = &dev->queues[0]; 2342 struct pci_dev *pdev = to_pci_dev(dev->dev); 2343 unsigned int nr_io_queues; 2344 unsigned long size; 2345 int result; 2346 2347 /* 2348 * Sample the module parameters once at reset time so that we have 2349 * stable values to work with. 2350 */ 2351 dev->nr_write_queues = write_queues; 2352 dev->nr_poll_queues = poll_queues; 2353 2354 nr_io_queues = dev->nr_allocated_queues - 1; 2355 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 2356 if (result < 0) 2357 return result; 2358 2359 if (nr_io_queues == 0) 2360 return 0; 2361 2362 /* 2363 * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions 2364 * from set to unset. If there is a window to it is truely freed, 2365 * pci_free_irq_vectors() jumping into this window will crash. 2366 * And take lock to avoid racing with pci_free_irq_vectors() in 2367 * nvme_dev_disable() path. 2368 */ 2369 result = nvme_setup_io_queues_trylock(dev); 2370 if (result) 2371 return result; 2372 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags)) 2373 pci_free_irq(pdev, 0, adminq); 2374 2375 if (dev->cmb_use_sqes) { 2376 result = nvme_cmb_qdepth(dev, nr_io_queues, 2377 sizeof(struct nvme_command)); 2378 if (result > 0) 2379 dev->q_depth = result; 2380 else 2381 dev->cmb_use_sqes = false; 2382 } 2383 2384 do { 2385 size = db_bar_size(dev, nr_io_queues); 2386 result = nvme_remap_bar(dev, size); 2387 if (!result) 2388 break; 2389 if (!--nr_io_queues) { 2390 result = -ENOMEM; 2391 goto out_unlock; 2392 } 2393 } while (1); 2394 adminq->q_db = dev->dbs; 2395 2396 retry: 2397 /* Deregister the admin queue's interrupt */ 2398 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags)) 2399 pci_free_irq(pdev, 0, adminq); 2400 2401 /* 2402 * If we enable msix early due to not intx, disable it again before 2403 * setting up the full range we need. 2404 */ 2405 pci_free_irq_vectors(pdev); 2406 2407 result = nvme_setup_irqs(dev, nr_io_queues); 2408 if (result <= 0) { 2409 result = -EIO; 2410 goto out_unlock; 2411 } 2412 2413 dev->num_vecs = result; 2414 result = max(result - 1, 1); 2415 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 2416 2417 /* 2418 * Should investigate if there's a performance win from allocating 2419 * more queues than interrupt vectors; it might allow the submission 2420 * path to scale better, even if the receive path is limited by the 2421 * number of interrupts. 2422 */ 2423 result = queue_request_irq(adminq); 2424 if (result) 2425 goto out_unlock; 2426 set_bit(NVMEQ_ENABLED, &adminq->flags); 2427 mutex_unlock(&dev->shutdown_lock); 2428 2429 result = nvme_create_io_queues(dev); 2430 if (result || dev->online_queues < 2) 2431 return result; 2432 2433 if (dev->online_queues - 1 < dev->max_qid) { 2434 nr_io_queues = dev->online_queues - 1; 2435 nvme_disable_io_queues(dev); 2436 result = nvme_setup_io_queues_trylock(dev); 2437 if (result) 2438 return result; 2439 nvme_suspend_io_queues(dev); 2440 goto retry; 2441 } 2442 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 2443 dev->io_queues[HCTX_TYPE_DEFAULT], 2444 dev->io_queues[HCTX_TYPE_READ], 2445 dev->io_queues[HCTX_TYPE_POLL]); 2446 return 0; 2447 out_unlock: 2448 mutex_unlock(&dev->shutdown_lock); 2449 return result; 2450 } 2451 2452 static enum rq_end_io_ret nvme_del_queue_end(struct request *req, 2453 blk_status_t error) 2454 { 2455 struct nvme_queue *nvmeq = req->end_io_data; 2456 2457 blk_mq_free_request(req); 2458 complete(&nvmeq->delete_done); 2459 return RQ_END_IO_NONE; 2460 } 2461 2462 static enum rq_end_io_ret nvme_del_cq_end(struct request *req, 2463 blk_status_t error) 2464 { 2465 struct nvme_queue *nvmeq = req->end_io_data; 2466 2467 if (error) 2468 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 2469 2470 return nvme_del_queue_end(req, error); 2471 } 2472 2473 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2474 { 2475 struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2476 struct request *req; 2477 struct nvme_command cmd = { }; 2478 2479 cmd.delete_queue.opcode = opcode; 2480 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2481 2482 req = blk_mq_alloc_request(q, nvme_req_op(&cmd), BLK_MQ_REQ_NOWAIT); 2483 if (IS_ERR(req)) 2484 return PTR_ERR(req); 2485 nvme_init_request(req, &cmd); 2486 2487 if (opcode == nvme_admin_delete_cq) 2488 req->end_io = nvme_del_cq_end; 2489 else 2490 req->end_io = nvme_del_queue_end; 2491 req->end_io_data = nvmeq; 2492 2493 init_completion(&nvmeq->delete_done); 2494 blk_execute_rq_nowait(req, false); 2495 return 0; 2496 } 2497 2498 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode) 2499 { 2500 int nr_queues = dev->online_queues - 1, sent = 0; 2501 unsigned long timeout; 2502 2503 retry: 2504 timeout = NVME_ADMIN_TIMEOUT; 2505 while (nr_queues > 0) { 2506 if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) 2507 break; 2508 nr_queues--; 2509 sent++; 2510 } 2511 while (sent) { 2512 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; 2513 2514 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, 2515 timeout); 2516 if (timeout == 0) 2517 return false; 2518 2519 sent--; 2520 if (nr_queues) 2521 goto retry; 2522 } 2523 return true; 2524 } 2525 2526 static void nvme_pci_alloc_tag_set(struct nvme_dev *dev) 2527 { 2528 struct blk_mq_tag_set * set = &dev->tagset; 2529 int ret; 2530 2531 set->ops = &nvme_mq_ops; 2532 set->nr_hw_queues = dev->online_queues - 1; 2533 set->nr_maps = 1; 2534 if (dev->io_queues[HCTX_TYPE_READ]) 2535 set->nr_maps = 2; 2536 if (dev->io_queues[HCTX_TYPE_POLL]) 2537 set->nr_maps = 3; 2538 set->timeout = NVME_IO_TIMEOUT; 2539 set->numa_node = dev->ctrl.numa_node; 2540 set->queue_depth = min_t(unsigned, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 2541 set->cmd_size = sizeof(struct nvme_iod); 2542 set->flags = BLK_MQ_F_SHOULD_MERGE; 2543 set->driver_data = dev; 2544 2545 /* 2546 * Some Apple controllers requires tags to be unique 2547 * across admin and IO queue, so reserve the first 32 2548 * tags of the IO queue. 2549 */ 2550 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2551 set->reserved_tags = NVME_AQ_DEPTH; 2552 2553 ret = blk_mq_alloc_tag_set(set); 2554 if (ret) { 2555 dev_warn(dev->ctrl.device, 2556 "IO queues tagset allocation failed %d\n", ret); 2557 return; 2558 } 2559 dev->ctrl.tagset = set; 2560 } 2561 2562 static void nvme_pci_update_nr_queues(struct nvme_dev *dev) 2563 { 2564 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2565 /* free previously allocated queues that are no longer usable */ 2566 nvme_free_queues(dev, dev->online_queues); 2567 } 2568 2569 static int nvme_pci_enable(struct nvme_dev *dev) 2570 { 2571 int result = -ENOMEM; 2572 struct pci_dev *pdev = to_pci_dev(dev->dev); 2573 int dma_address_bits = 64; 2574 2575 if (pci_enable_device_mem(pdev)) 2576 return result; 2577 2578 pci_set_master(pdev); 2579 2580 if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48) 2581 dma_address_bits = 48; 2582 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits))) 2583 goto disable; 2584 2585 if (readl(dev->bar + NVME_REG_CSTS) == -1) { 2586 result = -ENODEV; 2587 goto disable; 2588 } 2589 2590 /* 2591 * Some devices and/or platforms don't advertise or work with INTx 2592 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2593 * adjust this later. 2594 */ 2595 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2596 if (result < 0) 2597 return result; 2598 2599 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 2600 2601 dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2602 io_queue_depth); 2603 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */ 2604 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 2605 dev->dbs = dev->bar + 4096; 2606 2607 /* 2608 * Some Apple controllers require a non-standard SQE size. 2609 * Interestingly they also seem to ignore the CC:IOSQES register 2610 * so we don't bother updating it here. 2611 */ 2612 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES) 2613 dev->io_sqes = 7; 2614 else 2615 dev->io_sqes = NVME_NVM_IOSQES; 2616 2617 /* 2618 * Temporary fix for the Apple controller found in the MacBook8,1 and 2619 * some MacBook7,1 to avoid controller resets and data loss. 2620 */ 2621 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 2622 dev->q_depth = 2; 2623 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 2624 "set queue depth=%u to work around controller resets\n", 2625 dev->q_depth); 2626 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2627 (pdev->device == 0xa821 || pdev->device == 0xa822) && 2628 NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2629 dev->q_depth = 64; 2630 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2631 "set queue depth=%u\n", dev->q_depth); 2632 } 2633 2634 /* 2635 * Controllers with the shared tags quirk need the IO queue to be 2636 * big enough so that we get 32 tags for the admin queue 2637 */ 2638 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) && 2639 (dev->q_depth < (NVME_AQ_DEPTH + 2))) { 2640 dev->q_depth = NVME_AQ_DEPTH + 2; 2641 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n", 2642 dev->q_depth); 2643 } 2644 2645 2646 nvme_map_cmb(dev); 2647 2648 pci_enable_pcie_error_reporting(pdev); 2649 pci_save_state(pdev); 2650 return 0; 2651 2652 disable: 2653 pci_disable_device(pdev); 2654 return result; 2655 } 2656 2657 static void nvme_dev_unmap(struct nvme_dev *dev) 2658 { 2659 if (dev->bar) 2660 iounmap(dev->bar); 2661 pci_release_mem_regions(to_pci_dev(dev->dev)); 2662 } 2663 2664 static void nvme_pci_disable(struct nvme_dev *dev) 2665 { 2666 struct pci_dev *pdev = to_pci_dev(dev->dev); 2667 2668 pci_free_irq_vectors(pdev); 2669 2670 if (pci_is_enabled(pdev)) { 2671 pci_disable_pcie_error_reporting(pdev); 2672 pci_disable_device(pdev); 2673 } 2674 } 2675 2676 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 2677 { 2678 bool dead = true, freeze = false; 2679 struct pci_dev *pdev = to_pci_dev(dev->dev); 2680 2681 mutex_lock(&dev->shutdown_lock); 2682 if (pci_is_enabled(pdev)) { 2683 u32 csts; 2684 2685 if (pci_device_is_present(pdev)) 2686 csts = readl(dev->bar + NVME_REG_CSTS); 2687 else 2688 csts = ~0; 2689 2690 if (dev->ctrl.state == NVME_CTRL_LIVE || 2691 dev->ctrl.state == NVME_CTRL_RESETTING) { 2692 freeze = true; 2693 nvme_start_freeze(&dev->ctrl); 2694 } 2695 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2696 pdev->error_state != pci_channel_io_normal); 2697 } 2698 2699 /* 2700 * Give the controller a chance to complete all entered requests if 2701 * doing a safe shutdown. 2702 */ 2703 if (!dead && shutdown && freeze) 2704 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 2705 2706 nvme_stop_queues(&dev->ctrl); 2707 2708 if (!dead && dev->ctrl.queue_count > 0) { 2709 nvme_disable_io_queues(dev); 2710 nvme_disable_admin_queue(dev, shutdown); 2711 } 2712 nvme_suspend_io_queues(dev); 2713 nvme_suspend_queue(&dev->queues[0]); 2714 nvme_pci_disable(dev); 2715 nvme_reap_pending_cqes(dev); 2716 2717 nvme_cancel_tagset(&dev->ctrl); 2718 nvme_cancel_admin_tagset(&dev->ctrl); 2719 2720 /* 2721 * The driver will not be starting up queues again if shutting down so 2722 * must flush all entered requests to their failed completion to avoid 2723 * deadlocking blk-mq hot-cpu notifier. 2724 */ 2725 if (shutdown) { 2726 nvme_start_queues(&dev->ctrl); 2727 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) 2728 nvme_start_admin_queue(&dev->ctrl); 2729 } 2730 mutex_unlock(&dev->shutdown_lock); 2731 } 2732 2733 static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown) 2734 { 2735 if (!nvme_wait_reset(&dev->ctrl)) 2736 return -EBUSY; 2737 nvme_dev_disable(dev, shutdown); 2738 return 0; 2739 } 2740 2741 static int nvme_setup_prp_pools(struct nvme_dev *dev) 2742 { 2743 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 2744 NVME_CTRL_PAGE_SIZE, 2745 NVME_CTRL_PAGE_SIZE, 0); 2746 if (!dev->prp_page_pool) 2747 return -ENOMEM; 2748 2749 /* Optimisation for I/Os between 4k and 128k */ 2750 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 2751 256, 256, 0); 2752 if (!dev->prp_small_pool) { 2753 dma_pool_destroy(dev->prp_page_pool); 2754 return -ENOMEM; 2755 } 2756 return 0; 2757 } 2758 2759 static void nvme_release_prp_pools(struct nvme_dev *dev) 2760 { 2761 dma_pool_destroy(dev->prp_page_pool); 2762 dma_pool_destroy(dev->prp_small_pool); 2763 } 2764 2765 static void nvme_free_tagset(struct nvme_dev *dev) 2766 { 2767 if (dev->tagset.tags) 2768 blk_mq_free_tag_set(&dev->tagset); 2769 dev->ctrl.tagset = NULL; 2770 } 2771 2772 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 2773 { 2774 struct nvme_dev *dev = to_nvme_dev(ctrl); 2775 2776 nvme_dbbuf_dma_free(dev); 2777 nvme_free_tagset(dev); 2778 if (dev->ctrl.admin_q) 2779 blk_put_queue(dev->ctrl.admin_q); 2780 free_opal_dev(dev->ctrl.opal_dev); 2781 mempool_destroy(dev->iod_mempool); 2782 put_device(dev->dev); 2783 kfree(dev->queues); 2784 kfree(dev); 2785 } 2786 2787 static void nvme_remove_dead_ctrl(struct nvme_dev *dev) 2788 { 2789 /* 2790 * Set state to deleting now to avoid blocking nvme_wait_reset(), which 2791 * may be holding this pci_dev's device lock. 2792 */ 2793 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2794 nvme_get_ctrl(&dev->ctrl); 2795 nvme_dev_disable(dev, false); 2796 nvme_kill_queues(&dev->ctrl); 2797 if (!queue_work(nvme_wq, &dev->remove_work)) 2798 nvme_put_ctrl(&dev->ctrl); 2799 } 2800 2801 static void nvme_reset_work(struct work_struct *work) 2802 { 2803 struct nvme_dev *dev = 2804 container_of(work, struct nvme_dev, ctrl.reset_work); 2805 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2806 int result; 2807 2808 if (dev->ctrl.state != NVME_CTRL_RESETTING) { 2809 dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n", 2810 dev->ctrl.state); 2811 result = -ENODEV; 2812 goto out; 2813 } 2814 2815 /* 2816 * If we're called to reset a live controller first shut it down before 2817 * moving on. 2818 */ 2819 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2820 nvme_dev_disable(dev, false); 2821 nvme_sync_queues(&dev->ctrl); 2822 2823 mutex_lock(&dev->shutdown_lock); 2824 result = nvme_pci_enable(dev); 2825 if (result) 2826 goto out_unlock; 2827 2828 result = nvme_pci_configure_admin_queue(dev); 2829 if (result) 2830 goto out_unlock; 2831 2832 if (!dev->ctrl.admin_q) { 2833 result = nvme_pci_alloc_admin_tag_set(dev); 2834 if (result) 2835 goto out_unlock; 2836 } else { 2837 nvme_start_admin_queue(&dev->ctrl); 2838 } 2839 2840 dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1); 2841 2842 /* 2843 * Limit the max command size to prevent iod->sg allocations going 2844 * over a single page. 2845 */ 2846 dev->ctrl.max_hw_sectors = min_t(u32, 2847 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9); 2848 dev->ctrl.max_segments = NVME_MAX_SEGS; 2849 2850 /* 2851 * Don't limit the IOMMU merged segment size. 2852 */ 2853 dma_set_max_seg_size(dev->dev, 0xffffffff); 2854 2855 mutex_unlock(&dev->shutdown_lock); 2856 2857 /* 2858 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 2859 * initializing procedure here. 2860 */ 2861 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 2862 dev_warn(dev->ctrl.device, 2863 "failed to mark controller CONNECTING\n"); 2864 result = -EBUSY; 2865 goto out; 2866 } 2867 2868 /* 2869 * We do not support an SGL for metadata (yet), so we are limited to a 2870 * single integrity segment for the separate metadata pointer. 2871 */ 2872 dev->ctrl.max_integrity_segments = 1; 2873 2874 result = nvme_init_ctrl_finish(&dev->ctrl); 2875 if (result) 2876 goto out; 2877 2878 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2879 if (!dev->ctrl.opal_dev) 2880 dev->ctrl.opal_dev = 2881 init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2882 else if (was_suspend) 2883 opal_unlock_from_suspend(dev->ctrl.opal_dev); 2884 } else { 2885 free_opal_dev(dev->ctrl.opal_dev); 2886 dev->ctrl.opal_dev = NULL; 2887 } 2888 2889 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2890 result = nvme_dbbuf_dma_alloc(dev); 2891 if (result) 2892 dev_warn(dev->dev, 2893 "unable to allocate dma for dbbuf\n"); 2894 } 2895 2896 if (dev->ctrl.hmpre) { 2897 result = nvme_setup_host_mem(dev); 2898 if (result < 0) 2899 goto out; 2900 } 2901 2902 result = nvme_setup_io_queues(dev); 2903 if (result) 2904 goto out; 2905 2906 /* 2907 * Keep the controller around but remove all namespaces if we don't have 2908 * any working I/O queue. 2909 */ 2910 if (dev->online_queues < 2) { 2911 dev_warn(dev->ctrl.device, "IO queues not created\n"); 2912 nvme_kill_queues(&dev->ctrl); 2913 nvme_remove_namespaces(&dev->ctrl); 2914 nvme_free_tagset(dev); 2915 } else { 2916 nvme_start_queues(&dev->ctrl); 2917 nvme_wait_freeze(&dev->ctrl); 2918 if (!dev->ctrl.tagset) 2919 nvme_pci_alloc_tag_set(dev); 2920 else 2921 nvme_pci_update_nr_queues(dev); 2922 nvme_dbbuf_set(dev); 2923 nvme_unfreeze(&dev->ctrl); 2924 } 2925 2926 /* 2927 * If only admin queue live, keep it to do further investigation or 2928 * recovery. 2929 */ 2930 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { 2931 dev_warn(dev->ctrl.device, 2932 "failed to mark controller live state\n"); 2933 result = -ENODEV; 2934 goto out; 2935 } 2936 2937 if (!dev->attrs_added && !sysfs_create_group(&dev->ctrl.device->kobj, 2938 &nvme_pci_attr_group)) 2939 dev->attrs_added = true; 2940 2941 nvme_start_ctrl(&dev->ctrl); 2942 return; 2943 2944 out_unlock: 2945 mutex_unlock(&dev->shutdown_lock); 2946 out: 2947 if (result) 2948 dev_warn(dev->ctrl.device, 2949 "Removing after probe failure status: %d\n", result); 2950 nvme_remove_dead_ctrl(dev); 2951 } 2952 2953 static void nvme_remove_dead_ctrl_work(struct work_struct *work) 2954 { 2955 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 2956 struct pci_dev *pdev = to_pci_dev(dev->dev); 2957 2958 if (pci_get_drvdata(pdev)) 2959 device_release_driver(&pdev->dev); 2960 nvme_put_ctrl(&dev->ctrl); 2961 } 2962 2963 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 2964 { 2965 *val = readl(to_nvme_dev(ctrl)->bar + off); 2966 return 0; 2967 } 2968 2969 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 2970 { 2971 writel(val, to_nvme_dev(ctrl)->bar + off); 2972 return 0; 2973 } 2974 2975 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 2976 { 2977 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off); 2978 return 0; 2979 } 2980 2981 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 2982 { 2983 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 2984 2985 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev)); 2986 } 2987 2988 static void nvme_pci_print_device_info(struct nvme_ctrl *ctrl) 2989 { 2990 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 2991 struct nvme_subsystem *subsys = ctrl->subsys; 2992 2993 dev_err(ctrl->device, 2994 "VID:DID %04x:%04x model:%.*s firmware:%.*s\n", 2995 pdev->vendor, pdev->device, 2996 nvme_strlen(subsys->model, sizeof(subsys->model)), 2997 subsys->model, nvme_strlen(subsys->firmware_rev, 2998 sizeof(subsys->firmware_rev)), 2999 subsys->firmware_rev); 3000 } 3001 3002 static bool nvme_pci_supports_pci_p2pdma(struct nvme_ctrl *ctrl) 3003 { 3004 struct nvme_dev *dev = to_nvme_dev(ctrl); 3005 3006 return dma_pci_p2pdma_supported(dev->dev); 3007 } 3008 3009 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 3010 .name = "pcie", 3011 .module = THIS_MODULE, 3012 .flags = NVME_F_METADATA_SUPPORTED, 3013 .reg_read32 = nvme_pci_reg_read32, 3014 .reg_write32 = nvme_pci_reg_write32, 3015 .reg_read64 = nvme_pci_reg_read64, 3016 .free_ctrl = nvme_pci_free_ctrl, 3017 .submit_async_event = nvme_pci_submit_async_event, 3018 .get_address = nvme_pci_get_address, 3019 .print_device_info = nvme_pci_print_device_info, 3020 .supports_pci_p2pdma = nvme_pci_supports_pci_p2pdma, 3021 }; 3022 3023 static int nvme_dev_map(struct nvme_dev *dev) 3024 { 3025 struct pci_dev *pdev = to_pci_dev(dev->dev); 3026 3027 if (pci_request_mem_regions(pdev, "nvme")) 3028 return -ENODEV; 3029 3030 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 3031 goto release; 3032 3033 return 0; 3034 release: 3035 pci_release_mem_regions(pdev); 3036 return -ENODEV; 3037 } 3038 3039 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 3040 { 3041 if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 3042 /* 3043 * Several Samsung devices seem to drop off the PCIe bus 3044 * randomly when APST is on and uses the deepest sleep state. 3045 * This has been observed on a Samsung "SM951 NVMe SAMSUNG 3046 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 3047 * 950 PRO 256GB", but it seems to be restricted to two Dell 3048 * laptops. 3049 */ 3050 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 3051 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 3052 dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 3053 return NVME_QUIRK_NO_DEEPEST_PS; 3054 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 3055 /* 3056 * Samsung SSD 960 EVO drops off the PCIe bus after system 3057 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 3058 * within few minutes after bootup on a Coffee Lake board - 3059 * ASUS PRIME Z370-A 3060 */ 3061 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 3062 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 3063 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 3064 return NVME_QUIRK_NO_APST; 3065 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 || 3066 pdev->device == 0xa808 || pdev->device == 0xa809)) || 3067 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) { 3068 /* 3069 * Forcing to use host managed nvme power settings for 3070 * lowest idle power with quick resume latency on 3071 * Samsung and Toshiba SSDs based on suspend behavior 3072 * on Coffee Lake board for LENOVO C640 3073 */ 3074 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) && 3075 dmi_match(DMI_BOARD_NAME, "LNVNB161216")) 3076 return NVME_QUIRK_SIMPLE_SUSPEND; 3077 } 3078 3079 return 0; 3080 } 3081 3082 static void nvme_async_probe(void *data, async_cookie_t cookie) 3083 { 3084 struct nvme_dev *dev = data; 3085 3086 flush_work(&dev->ctrl.reset_work); 3087 flush_work(&dev->ctrl.scan_work); 3088 nvme_put_ctrl(&dev->ctrl); 3089 } 3090 3091 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 3092 { 3093 int node, result = -ENOMEM; 3094 struct nvme_dev *dev; 3095 unsigned long quirks = id->driver_data; 3096 size_t alloc_size; 3097 3098 node = dev_to_node(&pdev->dev); 3099 if (node == NUMA_NO_NODE) 3100 set_dev_node(&pdev->dev, first_memory_node); 3101 3102 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 3103 if (!dev) 3104 return -ENOMEM; 3105 3106 dev->nr_write_queues = write_queues; 3107 dev->nr_poll_queues = poll_queues; 3108 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1; 3109 dev->queues = kcalloc_node(dev->nr_allocated_queues, 3110 sizeof(struct nvme_queue), GFP_KERNEL, node); 3111 if (!dev->queues) 3112 goto free; 3113 3114 dev->dev = get_device(&pdev->dev); 3115 pci_set_drvdata(pdev, dev); 3116 3117 result = nvme_dev_map(dev); 3118 if (result) 3119 goto put_pci; 3120 3121 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 3122 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 3123 mutex_init(&dev->shutdown_lock); 3124 3125 result = nvme_setup_prp_pools(dev); 3126 if (result) 3127 goto unmap; 3128 3129 quirks |= check_vendor_combination_bug(pdev); 3130 3131 if (!noacpi && acpi_storage_d3(&pdev->dev)) { 3132 /* 3133 * Some systems use a bios work around to ask for D3 on 3134 * platforms that support kernel managed suspend. 3135 */ 3136 dev_info(&pdev->dev, 3137 "platform quirk: setting simple suspend\n"); 3138 quirks |= NVME_QUIRK_SIMPLE_SUSPEND; 3139 } 3140 3141 /* 3142 * Double check that our mempool alloc size will cover the biggest 3143 * command we support. 3144 */ 3145 alloc_size = nvme_pci_iod_alloc_size(); 3146 WARN_ON_ONCE(alloc_size > PAGE_SIZE); 3147 3148 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc, 3149 mempool_kfree, 3150 (void *) alloc_size, 3151 GFP_KERNEL, node); 3152 if (!dev->iod_mempool) { 3153 result = -ENOMEM; 3154 goto release_pools; 3155 } 3156 3157 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 3158 quirks); 3159 if (result) 3160 goto release_mempool; 3161 3162 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 3163 3164 nvme_reset_ctrl(&dev->ctrl); 3165 async_schedule(nvme_async_probe, dev); 3166 3167 return 0; 3168 3169 release_mempool: 3170 mempool_destroy(dev->iod_mempool); 3171 release_pools: 3172 nvme_release_prp_pools(dev); 3173 unmap: 3174 nvme_dev_unmap(dev); 3175 put_pci: 3176 put_device(dev->dev); 3177 free: 3178 kfree(dev->queues); 3179 kfree(dev); 3180 return result; 3181 } 3182 3183 static void nvme_reset_prepare(struct pci_dev *pdev) 3184 { 3185 struct nvme_dev *dev = pci_get_drvdata(pdev); 3186 3187 /* 3188 * We don't need to check the return value from waiting for the reset 3189 * state as pci_dev device lock is held, making it impossible to race 3190 * with ->remove(). 3191 */ 3192 nvme_disable_prepare_reset(dev, false); 3193 nvme_sync_queues(&dev->ctrl); 3194 } 3195 3196 static void nvme_reset_done(struct pci_dev *pdev) 3197 { 3198 struct nvme_dev *dev = pci_get_drvdata(pdev); 3199 3200 if (!nvme_try_sched_reset(&dev->ctrl)) 3201 flush_work(&dev->ctrl.reset_work); 3202 } 3203 3204 static void nvme_shutdown(struct pci_dev *pdev) 3205 { 3206 struct nvme_dev *dev = pci_get_drvdata(pdev); 3207 3208 nvme_disable_prepare_reset(dev, true); 3209 } 3210 3211 static void nvme_remove_attrs(struct nvme_dev *dev) 3212 { 3213 if (dev->attrs_added) 3214 sysfs_remove_group(&dev->ctrl.device->kobj, 3215 &nvme_pci_attr_group); 3216 } 3217 3218 /* 3219 * The driver's remove may be called on a device in a partially initialized 3220 * state. This function must not have any dependencies on the device state in 3221 * order to proceed. 3222 */ 3223 static void nvme_remove(struct pci_dev *pdev) 3224 { 3225 struct nvme_dev *dev = pci_get_drvdata(pdev); 3226 3227 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 3228 pci_set_drvdata(pdev, NULL); 3229 3230 if (!pci_device_is_present(pdev)) { 3231 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 3232 nvme_dev_disable(dev, true); 3233 } 3234 3235 flush_work(&dev->ctrl.reset_work); 3236 nvme_stop_ctrl(&dev->ctrl); 3237 nvme_remove_namespaces(&dev->ctrl); 3238 nvme_dev_disable(dev, true); 3239 nvme_remove_attrs(dev); 3240 nvme_free_host_mem(dev); 3241 nvme_dev_remove_admin(dev); 3242 nvme_free_queues(dev, 0); 3243 nvme_release_prp_pools(dev); 3244 nvme_dev_unmap(dev); 3245 nvme_uninit_ctrl(&dev->ctrl); 3246 } 3247 3248 #ifdef CONFIG_PM_SLEEP 3249 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps) 3250 { 3251 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps); 3252 } 3253 3254 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps) 3255 { 3256 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL); 3257 } 3258 3259 static int nvme_resume(struct device *dev) 3260 { 3261 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 3262 struct nvme_ctrl *ctrl = &ndev->ctrl; 3263 3264 if (ndev->last_ps == U32_MAX || 3265 nvme_set_power_state(ctrl, ndev->last_ps) != 0) 3266 goto reset; 3267 if (ctrl->hmpre && nvme_setup_host_mem(ndev)) 3268 goto reset; 3269 3270 return 0; 3271 reset: 3272 return nvme_try_sched_reset(ctrl); 3273 } 3274 3275 static int nvme_suspend(struct device *dev) 3276 { 3277 struct pci_dev *pdev = to_pci_dev(dev); 3278 struct nvme_dev *ndev = pci_get_drvdata(pdev); 3279 struct nvme_ctrl *ctrl = &ndev->ctrl; 3280 int ret = -EBUSY; 3281 3282 ndev->last_ps = U32_MAX; 3283 3284 /* 3285 * The platform does not remove power for a kernel managed suspend so 3286 * use host managed nvme power settings for lowest idle power if 3287 * possible. This should have quicker resume latency than a full device 3288 * shutdown. But if the firmware is involved after the suspend or the 3289 * device does not support any non-default power states, shut down the 3290 * device fully. 3291 * 3292 * If ASPM is not enabled for the device, shut down the device and allow 3293 * the PCI bus layer to put it into D3 in order to take the PCIe link 3294 * down, so as to allow the platform to achieve its minimum low-power 3295 * state (which may not be possible if the link is up). 3296 */ 3297 if (pm_suspend_via_firmware() || !ctrl->npss || 3298 !pcie_aspm_enabled(pdev) || 3299 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND)) 3300 return nvme_disable_prepare_reset(ndev, true); 3301 3302 nvme_start_freeze(ctrl); 3303 nvme_wait_freeze(ctrl); 3304 nvme_sync_queues(ctrl); 3305 3306 if (ctrl->state != NVME_CTRL_LIVE) 3307 goto unfreeze; 3308 3309 /* 3310 * Host memory access may not be successful in a system suspend state, 3311 * but the specification allows the controller to access memory in a 3312 * non-operational power state. 3313 */ 3314 if (ndev->hmb) { 3315 ret = nvme_set_host_mem(ndev, 0); 3316 if (ret < 0) 3317 goto unfreeze; 3318 } 3319 3320 ret = nvme_get_power_state(ctrl, &ndev->last_ps); 3321 if (ret < 0) 3322 goto unfreeze; 3323 3324 /* 3325 * A saved state prevents pci pm from generically controlling the 3326 * device's power. If we're using protocol specific settings, we don't 3327 * want pci interfering. 3328 */ 3329 pci_save_state(pdev); 3330 3331 ret = nvme_set_power_state(ctrl, ctrl->npss); 3332 if (ret < 0) 3333 goto unfreeze; 3334 3335 if (ret) { 3336 /* discard the saved state */ 3337 pci_load_saved_state(pdev, NULL); 3338 3339 /* 3340 * Clearing npss forces a controller reset on resume. The 3341 * correct value will be rediscovered then. 3342 */ 3343 ret = nvme_disable_prepare_reset(ndev, true); 3344 ctrl->npss = 0; 3345 } 3346 unfreeze: 3347 nvme_unfreeze(ctrl); 3348 return ret; 3349 } 3350 3351 static int nvme_simple_suspend(struct device *dev) 3352 { 3353 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 3354 3355 return nvme_disable_prepare_reset(ndev, true); 3356 } 3357 3358 static int nvme_simple_resume(struct device *dev) 3359 { 3360 struct pci_dev *pdev = to_pci_dev(dev); 3361 struct nvme_dev *ndev = pci_get_drvdata(pdev); 3362 3363 return nvme_try_sched_reset(&ndev->ctrl); 3364 } 3365 3366 static const struct dev_pm_ops nvme_dev_pm_ops = { 3367 .suspend = nvme_suspend, 3368 .resume = nvme_resume, 3369 .freeze = nvme_simple_suspend, 3370 .thaw = nvme_simple_resume, 3371 .poweroff = nvme_simple_suspend, 3372 .restore = nvme_simple_resume, 3373 }; 3374 #endif /* CONFIG_PM_SLEEP */ 3375 3376 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 3377 pci_channel_state_t state) 3378 { 3379 struct nvme_dev *dev = pci_get_drvdata(pdev); 3380 3381 /* 3382 * A frozen channel requires a reset. When detected, this method will 3383 * shutdown the controller to quiesce. The controller will be restarted 3384 * after the slot reset through driver's slot_reset callback. 3385 */ 3386 switch (state) { 3387 case pci_channel_io_normal: 3388 return PCI_ERS_RESULT_CAN_RECOVER; 3389 case pci_channel_io_frozen: 3390 dev_warn(dev->ctrl.device, 3391 "frozen state error detected, reset controller\n"); 3392 nvme_dev_disable(dev, false); 3393 return PCI_ERS_RESULT_NEED_RESET; 3394 case pci_channel_io_perm_failure: 3395 dev_warn(dev->ctrl.device, 3396 "failure state error detected, request disconnect\n"); 3397 return PCI_ERS_RESULT_DISCONNECT; 3398 } 3399 return PCI_ERS_RESULT_NEED_RESET; 3400 } 3401 3402 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 3403 { 3404 struct nvme_dev *dev = pci_get_drvdata(pdev); 3405 3406 dev_info(dev->ctrl.device, "restart after slot reset\n"); 3407 pci_restore_state(pdev); 3408 nvme_reset_ctrl(&dev->ctrl); 3409 return PCI_ERS_RESULT_RECOVERED; 3410 } 3411 3412 static void nvme_error_resume(struct pci_dev *pdev) 3413 { 3414 struct nvme_dev *dev = pci_get_drvdata(pdev); 3415 3416 flush_work(&dev->ctrl.reset_work); 3417 } 3418 3419 static const struct pci_error_handlers nvme_err_handler = { 3420 .error_detected = nvme_error_detected, 3421 .slot_reset = nvme_slot_reset, 3422 .resume = nvme_error_resume, 3423 .reset_prepare = nvme_reset_prepare, 3424 .reset_done = nvme_reset_done, 3425 }; 3426 3427 static const struct pci_device_id nvme_id_table[] = { 3428 { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */ 3429 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3430 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3431 { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */ 3432 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3433 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3434 { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */ 3435 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3436 NVME_QUIRK_DEALLOCATE_ZEROES | 3437 NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3438 { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */ 3439 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3440 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3441 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 3442 .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3443 NVME_QUIRK_MEDIUM_PRIO_SQ | 3444 NVME_QUIRK_NO_TEMP_THRESH_CHANGE | 3445 NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3446 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ 3447 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3448 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 3449 .driver_data = NVME_QUIRK_IDENTIFY_CNS | 3450 NVME_QUIRK_DISABLE_WRITE_ZEROES | 3451 NVME_QUIRK_BOGUS_NID, }, 3452 { PCI_VDEVICE(REDHAT, 0x0010), /* Qemu emulated controller */ 3453 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3454 { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */ 3455 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST | 3456 NVME_QUIRK_BOGUS_NID, }, 3457 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 3458 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | 3459 NVME_QUIRK_NO_NS_DESC_LIST, }, 3460 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 3461 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3462 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 3463 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3464 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 3465 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3466 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 3467 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3468 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 3469 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | 3470 NVME_QUIRK_DISABLE_WRITE_ZEROES| 3471 NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3472 { PCI_DEVICE(0x1987, 0x5012), /* Phison E12 */ 3473 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3474 { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */ 3475 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN | 3476 NVME_QUIRK_BOGUS_NID, }, 3477 { PCI_DEVICE(0x1987, 0x5019), /* phison E19 */ 3478 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3479 { PCI_DEVICE(0x1987, 0x5021), /* Phison E21 */ 3480 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3481 { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */ 3482 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST | 3483 NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3484 { PCI_DEVICE(0x1cc1, 0x33f8), /* ADATA IM2P33F8ABR1 1 TB */ 3485 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3486 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */ 3487 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN | 3488 NVME_QUIRK_BOGUS_NID, }, 3489 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */ 3490 .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3491 NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3492 { PCI_DEVICE(0x1344, 0x5407), /* Micron Technology Inc NVMe SSD */ 3493 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN }, 3494 { PCI_DEVICE(0x1344, 0x6001), /* Micron Nitro NVMe */ 3495 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3496 { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */ 3497 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3498 { PCI_DEVICE(0x1c5c, 0x174a), /* SK Hynix P31 SSD */ 3499 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3500 { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */ 3501 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3502 { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */ 3503 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3504 { PCI_DEVICE(0x144d, 0xa80b), /* Samsung PM9B1 256G and 512G */ 3505 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3506 { PCI_DEVICE(0x144d, 0xa809), /* Samsung MZALQ256HBJD 256G */ 3507 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3508 { PCI_DEVICE(0x1cc4, 0x6303), /* UMIS RPJTJ512MGE1QDY 512G */ 3509 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3510 { PCI_DEVICE(0x1cc4, 0x6302), /* UMIS RPJTJ256MGE1QDY 256G */ 3511 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3512 { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */ 3513 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3514 { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */ 3515 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3516 { PCI_DEVICE(0x2646, 0x5018), /* KINGSTON OM8SFP4xxxxP OS21012 NVMe SSD */ 3517 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3518 { PCI_DEVICE(0x2646, 0x5016), /* KINGSTON OM3PGP4xxxxP OS21011 NVMe SSD */ 3519 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3520 { PCI_DEVICE(0x2646, 0x501A), /* KINGSTON OM8PGP4xxxxP OS21005 NVMe SSD */ 3521 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3522 { PCI_DEVICE(0x2646, 0x501B), /* KINGSTON OM8PGP4xxxxQ OS21005 NVMe SSD */ 3523 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3524 { PCI_DEVICE(0x2646, 0x501E), /* KINGSTON OM3PGP4xxxxQ OS21011 NVMe SSD */ 3525 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3526 { PCI_DEVICE(0x1f40, 0x5236), /* Netac Technologies Co. NV7000 NVMe SSD */ 3527 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3528 { PCI_DEVICE(0x1e4B, 0x1001), /* MAXIO MAP1001 */ 3529 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3530 { PCI_DEVICE(0x1e4B, 0x1002), /* MAXIO MAP1002 */ 3531 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3532 { PCI_DEVICE(0x1e4B, 0x1202), /* MAXIO MAP1202 */ 3533 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3534 { PCI_DEVICE(0x1cc1, 0x5350), /* ADATA XPG GAMMIX S50 */ 3535 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3536 { PCI_DEVICE(0x1dbe, 0x5236), /* ADATA XPG GAMMIX S70 */ 3537 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3538 { PCI_DEVICE(0x1e49, 0x0021), /* ZHITAI TiPro5000 NVMe SSD */ 3539 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3540 { PCI_DEVICE(0x1e49, 0x0041), /* ZHITAI TiPro7000 NVMe SSD */ 3541 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3542 { PCI_DEVICE(0xc0a9, 0x540a), /* Crucial P2 */ 3543 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3544 { PCI_DEVICE(0x1d97, 0x2263), /* Lexar NM610 */ 3545 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3546 { PCI_DEVICE(0x1d97, 0x2269), /* Lexar NM760 */ 3547 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3548 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061), 3549 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 3550 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065), 3551 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 3552 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061), 3553 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 3554 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00), 3555 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 3556 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01), 3557 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 3558 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02), 3559 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 3560 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001), 3561 .driver_data = NVME_QUIRK_SINGLE_VECTOR }, 3562 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 3563 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005), 3564 .driver_data = NVME_QUIRK_SINGLE_VECTOR | 3565 NVME_QUIRK_128_BYTES_SQES | 3566 NVME_QUIRK_SHARED_TAGS | 3567 NVME_QUIRK_SKIP_CID_GEN }, 3568 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 3569 { 0, } 3570 }; 3571 MODULE_DEVICE_TABLE(pci, nvme_id_table); 3572 3573 static struct pci_driver nvme_driver = { 3574 .name = "nvme", 3575 .id_table = nvme_id_table, 3576 .probe = nvme_probe, 3577 .remove = nvme_remove, 3578 .shutdown = nvme_shutdown, 3579 #ifdef CONFIG_PM_SLEEP 3580 .driver = { 3581 .pm = &nvme_dev_pm_ops, 3582 }, 3583 #endif 3584 .sriov_configure = pci_sriov_configure_simple, 3585 .err_handler = &nvme_err_handler, 3586 }; 3587 3588 static int __init nvme_init(void) 3589 { 3590 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 3591 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 3592 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 3593 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); 3594 BUILD_BUG_ON(DIV_ROUND_UP(nvme_pci_npages_prp(), NVME_CTRL_PAGE_SIZE) > 3595 S8_MAX); 3596 3597 return pci_register_driver(&nvme_driver); 3598 } 3599 3600 static void __exit nvme_exit(void) 3601 { 3602 pci_unregister_driver(&nvme_driver); 3603 flush_workqueue(nvme_wq); 3604 } 3605 3606 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 3607 MODULE_LICENSE("GPL"); 3608 MODULE_VERSION("1.0"); 3609 module_init(nvme_init); 3610 module_exit(nvme_exit); 3611