1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2019 HiSilicon Limited. */ 3 #include <linux/acpi.h> 4 #include <linux/aer.h> 5 #include <linux/bitops.h> 6 #include <linux/debugfs.h> 7 #include <linux/init.h> 8 #include <linux/io.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/seq_file.h> 14 #include <linux/topology.h> 15 #include <linux/uacce.h> 16 #include "zip.h" 17 18 #define PCI_DEVICE_ID_HUAWEI_ZIP_PF 0xa250 19 20 #define HZIP_QUEUE_NUM_V1 4096 21 22 #define HZIP_CLOCK_GATE_CTRL 0x301004 23 #define HZIP_DECOMP_CHECK_ENABLE BIT(16) 24 #define HZIP_FSM_MAX_CNT 0x301008 25 26 #define HZIP_PORT_ARCA_CHE_0 0x301040 27 #define HZIP_PORT_ARCA_CHE_1 0x301044 28 #define HZIP_PORT_AWCA_CHE_0 0x301060 29 #define HZIP_PORT_AWCA_CHE_1 0x301064 30 #define HZIP_CACHE_ALL_EN 0xffffffff 31 32 #define HZIP_BD_RUSER_32_63 0x301110 33 #define HZIP_SGL_RUSER_32_63 0x30111c 34 #define HZIP_DATA_RUSER_32_63 0x301128 35 #define HZIP_DATA_WUSER_32_63 0x301134 36 #define HZIP_BD_WUSER_32_63 0x301140 37 38 #define HZIP_QM_IDEL_STATUS 0x3040e4 39 40 #define HZIP_CORE_DFX_BASE 0x301000 41 #define HZIP_CLOCK_GATED_CONTL 0X301004 42 #define HZIP_CORE_DFX_COMP_0 0x302000 43 #define HZIP_CORE_DFX_COMP_1 0x303000 44 #define HZIP_CORE_DFX_DECOMP_0 0x304000 45 #define HZIP_CORE_DFX_DECOMP_1 0x305000 46 #define HZIP_CORE_DFX_DECOMP_2 0x306000 47 #define HZIP_CORE_DFX_DECOMP_3 0x307000 48 #define HZIP_CORE_DFX_DECOMP_4 0x308000 49 #define HZIP_CORE_DFX_DECOMP_5 0x309000 50 #define HZIP_CORE_REGS_BASE_LEN 0xB0 51 #define HZIP_CORE_REGS_DFX_LEN 0x28 52 53 #define HZIP_CORE_INT_SOURCE 0x3010A0 54 #define HZIP_CORE_INT_MASK_REG 0x3010A4 55 #define HZIP_CORE_INT_SET 0x3010A8 56 #define HZIP_CORE_INT_STATUS 0x3010AC 57 #define HZIP_CORE_INT_STATUS_M_ECC BIT(1) 58 #define HZIP_CORE_SRAM_ECC_ERR_INFO 0x301148 59 #define HZIP_CORE_INT_RAS_CE_ENB 0x301160 60 #define HZIP_CORE_INT_RAS_NFE_ENB 0x301164 61 #define HZIP_CORE_INT_RAS_FE_ENB 0x301168 62 #define HZIP_CORE_INT_RAS_FE_ENB_MASK 0x0 63 #define HZIP_OOO_SHUTDOWN_SEL 0x30120C 64 #define HZIP_SRAM_ECC_ERR_NUM_SHIFT 16 65 #define HZIP_SRAM_ECC_ERR_ADDR_SHIFT 24 66 #define HZIP_CORE_INT_MASK_ALL GENMASK(12, 0) 67 #define HZIP_SQE_SIZE 128 68 #define HZIP_PF_DEF_Q_NUM 64 69 #define HZIP_PF_DEF_Q_BASE 0 70 71 #define HZIP_SOFT_CTRL_CNT_CLR_CE 0x301000 72 #define HZIP_SOFT_CTRL_CNT_CLR_CE_BIT BIT(0) 73 #define HZIP_SOFT_CTRL_ZIP_CONTROL 0x30100C 74 #define HZIP_AXI_SHUTDOWN_ENABLE BIT(14) 75 #define HZIP_WR_PORT BIT(11) 76 77 #define HZIP_DEV_ALG_MAX_LEN 256 78 #define HZIP_ALG_ZLIB_BIT GENMASK(1, 0) 79 #define HZIP_ALG_GZIP_BIT GENMASK(3, 2) 80 #define HZIP_ALG_DEFLATE_BIT GENMASK(5, 4) 81 #define HZIP_ALG_LZ77_BIT GENMASK(7, 6) 82 83 #define HZIP_BUF_SIZE 22 84 #define HZIP_SQE_MASK_OFFSET 64 85 #define HZIP_SQE_MASK_LEN 48 86 87 #define HZIP_CNT_CLR_CE_EN BIT(0) 88 #define HZIP_RO_CNT_CLR_CE_EN BIT(2) 89 #define HZIP_RD_CNT_CLR_CE_EN (HZIP_CNT_CLR_CE_EN | \ 90 HZIP_RO_CNT_CLR_CE_EN) 91 92 #define HZIP_PREFETCH_CFG 0x3011B0 93 #define HZIP_SVA_TRANS 0x3011C4 94 #define HZIP_PREFETCH_ENABLE (~(BIT(26) | BIT(17) | BIT(0))) 95 #define HZIP_SVA_PREFETCH_DISABLE BIT(26) 96 #define HZIP_SVA_DISABLE_READY (BIT(26) | BIT(30)) 97 #define HZIP_SHAPER_RATE_COMPRESS 750 98 #define HZIP_SHAPER_RATE_DECOMPRESS 140 99 #define HZIP_DELAY_1_US 1 100 #define HZIP_POLL_TIMEOUT_US 1000 101 102 /* clock gating */ 103 #define HZIP_PEH_CFG_AUTO_GATE 0x3011A8 104 #define HZIP_PEH_CFG_AUTO_GATE_EN BIT(0) 105 #define HZIP_CORE_GATED_EN GENMASK(15, 8) 106 #define HZIP_CORE_GATED_OOO_EN BIT(29) 107 #define HZIP_CLOCK_GATED_EN (HZIP_CORE_GATED_EN | \ 108 HZIP_CORE_GATED_OOO_EN) 109 110 static const char hisi_zip_name[] = "hisi_zip"; 111 static struct dentry *hzip_debugfs_root; 112 113 struct hisi_zip_hw_error { 114 u32 int_msk; 115 const char *msg; 116 }; 117 118 struct zip_dfx_item { 119 const char *name; 120 u32 offset; 121 }; 122 123 struct zip_dev_alg { 124 u32 alg_msk; 125 const char *algs; 126 }; 127 128 static const struct zip_dev_alg zip_dev_algs[] = { { 129 .alg_msk = HZIP_ALG_ZLIB_BIT, 130 .algs = "zlib\n", 131 }, { 132 .alg_msk = HZIP_ALG_GZIP_BIT, 133 .algs = "gzip\n", 134 }, { 135 .alg_msk = HZIP_ALG_DEFLATE_BIT, 136 .algs = "deflate\n", 137 }, { 138 .alg_msk = HZIP_ALG_LZ77_BIT, 139 .algs = "lz77_zstd\n", 140 }, 141 }; 142 143 static struct hisi_qm_list zip_devices = { 144 .register_to_crypto = hisi_zip_register_to_crypto, 145 .unregister_from_crypto = hisi_zip_unregister_from_crypto, 146 }; 147 148 static struct zip_dfx_item zip_dfx_files[] = { 149 {"send_cnt", offsetof(struct hisi_zip_dfx, send_cnt)}, 150 {"recv_cnt", offsetof(struct hisi_zip_dfx, recv_cnt)}, 151 {"send_busy_cnt", offsetof(struct hisi_zip_dfx, send_busy_cnt)}, 152 {"err_bd_cnt", offsetof(struct hisi_zip_dfx, err_bd_cnt)}, 153 }; 154 155 static const struct hisi_zip_hw_error zip_hw_error[] = { 156 { .int_msk = BIT(0), .msg = "zip_ecc_1bitt_err" }, 157 { .int_msk = BIT(1), .msg = "zip_ecc_2bit_err" }, 158 { .int_msk = BIT(2), .msg = "zip_axi_rresp_err" }, 159 { .int_msk = BIT(3), .msg = "zip_axi_bresp_err" }, 160 { .int_msk = BIT(4), .msg = "zip_src_addr_parse_err" }, 161 { .int_msk = BIT(5), .msg = "zip_dst_addr_parse_err" }, 162 { .int_msk = BIT(6), .msg = "zip_pre_in_addr_err" }, 163 { .int_msk = BIT(7), .msg = "zip_pre_in_data_err" }, 164 { .int_msk = BIT(8), .msg = "zip_com_inf_err" }, 165 { .int_msk = BIT(9), .msg = "zip_enc_inf_err" }, 166 { .int_msk = BIT(10), .msg = "zip_pre_out_err" }, 167 { .int_msk = BIT(11), .msg = "zip_axi_poison_err" }, 168 { .int_msk = BIT(12), .msg = "zip_sva_err" }, 169 { /* sentinel */ } 170 }; 171 172 enum ctrl_debug_file_index { 173 HZIP_CLEAR_ENABLE, 174 HZIP_DEBUG_FILE_NUM, 175 }; 176 177 static const char * const ctrl_debug_file_name[] = { 178 [HZIP_CLEAR_ENABLE] = "clear_enable", 179 }; 180 181 struct ctrl_debug_file { 182 enum ctrl_debug_file_index index; 183 spinlock_t lock; 184 struct hisi_zip_ctrl *ctrl; 185 }; 186 187 /* 188 * One ZIP controller has one PF and multiple VFs, some global configurations 189 * which PF has need this structure. 190 * 191 * Just relevant for PF. 192 */ 193 struct hisi_zip_ctrl { 194 struct hisi_zip *hisi_zip; 195 struct ctrl_debug_file files[HZIP_DEBUG_FILE_NUM]; 196 }; 197 198 enum zip_cap_type { 199 ZIP_QM_NFE_MASK_CAP = 0x0, 200 ZIP_QM_RESET_MASK_CAP, 201 ZIP_QM_OOO_SHUTDOWN_MASK_CAP, 202 ZIP_QM_CE_MASK_CAP, 203 ZIP_NFE_MASK_CAP, 204 ZIP_RESET_MASK_CAP, 205 ZIP_OOO_SHUTDOWN_MASK_CAP, 206 ZIP_CE_MASK_CAP, 207 ZIP_CLUSTER_NUM_CAP, 208 ZIP_CORE_TYPE_NUM_CAP, 209 ZIP_CORE_NUM_CAP, 210 ZIP_CLUSTER_COMP_NUM_CAP, 211 ZIP_CLUSTER_DECOMP_NUM_CAP, 212 ZIP_DECOMP_ENABLE_BITMAP, 213 ZIP_COMP_ENABLE_BITMAP, 214 ZIP_DRV_ALG_BITMAP, 215 ZIP_DEV_ALG_BITMAP, 216 ZIP_CORE1_ALG_BITMAP, 217 ZIP_CORE2_ALG_BITMAP, 218 ZIP_CORE3_ALG_BITMAP, 219 ZIP_CORE4_ALG_BITMAP, 220 ZIP_CORE5_ALG_BITMAP, 221 ZIP_CAP_MAX 222 }; 223 224 static struct hisi_qm_cap_info zip_basic_cap_info[] = { 225 {ZIP_QM_NFE_MASK_CAP, 0x3124, 0, GENMASK(31, 0), 0x0, 0x1C57, 0x7C77}, 226 {ZIP_QM_RESET_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0xC57, 0x6C77}, 227 {ZIP_QM_OOO_SHUTDOWN_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0x4, 0x6C77}, 228 {ZIP_QM_CE_MASK_CAP, 0x312C, 0, GENMASK(31, 0), 0x0, 0x8, 0x8}, 229 {ZIP_NFE_MASK_CAP, 0x3130, 0, GENMASK(31, 0), 0x0, 0x7FE, 0x1FFE}, 230 {ZIP_RESET_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x7FE, 0x7FE}, 231 {ZIP_OOO_SHUTDOWN_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x2, 0x7FE}, 232 {ZIP_CE_MASK_CAP, 0x3138, 0, GENMASK(31, 0), 0x0, 0x1, 0x1}, 233 {ZIP_CLUSTER_NUM_CAP, 0x313C, 28, GENMASK(3, 0), 0x1, 0x1, 0x1}, 234 {ZIP_CORE_TYPE_NUM_CAP, 0x313C, 24, GENMASK(3, 0), 0x2, 0x2, 0x2}, 235 {ZIP_CORE_NUM_CAP, 0x313C, 16, GENMASK(7, 0), 0x8, 0x8, 0x5}, 236 {ZIP_CLUSTER_COMP_NUM_CAP, 0x313C, 8, GENMASK(7, 0), 0x2, 0x2, 0x2}, 237 {ZIP_CLUSTER_DECOMP_NUM_CAP, 0x313C, 0, GENMASK(7, 0), 0x6, 0x6, 0x3}, 238 {ZIP_DECOMP_ENABLE_BITMAP, 0x3140, 16, GENMASK(15, 0), 0xFC, 0xFC, 0x1C}, 239 {ZIP_COMP_ENABLE_BITMAP, 0x3140, 0, GENMASK(15, 0), 0x3, 0x3, 0x3}, 240 {ZIP_DRV_ALG_BITMAP, 0x3144, 0, GENMASK(31, 0), 0xF, 0xF, 0xF}, 241 {ZIP_DEV_ALG_BITMAP, 0x3148, 0, GENMASK(31, 0), 0xF, 0xF, 0xFF}, 242 {ZIP_CORE1_ALG_BITMAP, 0x314C, 0, GENMASK(31, 0), 0x5, 0x5, 0xD5}, 243 {ZIP_CORE2_ALG_BITMAP, 0x3150, 0, GENMASK(31, 0), 0x5, 0x5, 0xD5}, 244 {ZIP_CORE3_ALG_BITMAP, 0x3154, 0, GENMASK(31, 0), 0xA, 0xA, 0x2A}, 245 {ZIP_CORE4_ALG_BITMAP, 0x3158, 0, GENMASK(31, 0), 0xA, 0xA, 0x2A}, 246 {ZIP_CORE5_ALG_BITMAP, 0x315C, 0, GENMASK(31, 0), 0xA, 0xA, 0x2A}, 247 {ZIP_CAP_MAX, 0x317c, 0, GENMASK(0, 0), 0x0, 0x0, 0x0} 248 }; 249 250 enum { 251 HZIP_COMP_CORE0, 252 HZIP_COMP_CORE1, 253 HZIP_DECOMP_CORE0, 254 HZIP_DECOMP_CORE1, 255 HZIP_DECOMP_CORE2, 256 HZIP_DECOMP_CORE3, 257 HZIP_DECOMP_CORE4, 258 HZIP_DECOMP_CORE5, 259 }; 260 261 static const u64 core_offsets[] = { 262 [HZIP_COMP_CORE0] = 0x302000, 263 [HZIP_COMP_CORE1] = 0x303000, 264 [HZIP_DECOMP_CORE0] = 0x304000, 265 [HZIP_DECOMP_CORE1] = 0x305000, 266 [HZIP_DECOMP_CORE2] = 0x306000, 267 [HZIP_DECOMP_CORE3] = 0x307000, 268 [HZIP_DECOMP_CORE4] = 0x308000, 269 [HZIP_DECOMP_CORE5] = 0x309000, 270 }; 271 272 static const struct debugfs_reg32 hzip_dfx_regs[] = { 273 {"HZIP_GET_BD_NUM ", 0x00ull}, 274 {"HZIP_GET_RIGHT_BD ", 0x04ull}, 275 {"HZIP_GET_ERROR_BD ", 0x08ull}, 276 {"HZIP_DONE_BD_NUM ", 0x0cull}, 277 {"HZIP_WORK_CYCLE ", 0x10ull}, 278 {"HZIP_IDLE_CYCLE ", 0x18ull}, 279 {"HZIP_MAX_DELAY ", 0x20ull}, 280 {"HZIP_MIN_DELAY ", 0x24ull}, 281 {"HZIP_AVG_DELAY ", 0x28ull}, 282 {"HZIP_MEM_VISIBLE_DATA ", 0x30ull}, 283 {"HZIP_MEM_VISIBLE_ADDR ", 0x34ull}, 284 {"HZIP_CONSUMED_BYTE ", 0x38ull}, 285 {"HZIP_PRODUCED_BYTE ", 0x40ull}, 286 {"HZIP_COMP_INF ", 0x70ull}, 287 {"HZIP_PRE_OUT ", 0x78ull}, 288 {"HZIP_BD_RD ", 0x7cull}, 289 {"HZIP_BD_WR ", 0x80ull}, 290 {"HZIP_GET_BD_AXI_ERR_NUM ", 0x84ull}, 291 {"HZIP_GET_BD_PARSE_ERR_NUM ", 0x88ull}, 292 {"HZIP_ADD_BD_AXI_ERR_NUM ", 0x8cull}, 293 {"HZIP_DECOMP_STF_RELOAD_CURR_ST ", 0x94ull}, 294 {"HZIP_DECOMP_LZ77_CURR_ST ", 0x9cull}, 295 }; 296 297 static const struct debugfs_reg32 hzip_com_dfx_regs[] = { 298 {"HZIP_CLOCK_GATE_CTRL ", 0x301004}, 299 {"HZIP_CORE_INT_RAS_CE_ENB ", 0x301160}, 300 {"HZIP_CORE_INT_RAS_NFE_ENB ", 0x301164}, 301 {"HZIP_CORE_INT_RAS_FE_ENB ", 0x301168}, 302 {"HZIP_UNCOM_ERR_RAS_CTRL ", 0x30116C}, 303 }; 304 305 static const struct debugfs_reg32 hzip_dump_dfx_regs[] = { 306 {"HZIP_GET_BD_NUM ", 0x00ull}, 307 {"HZIP_GET_RIGHT_BD ", 0x04ull}, 308 {"HZIP_GET_ERROR_BD ", 0x08ull}, 309 {"HZIP_DONE_BD_NUM ", 0x0cull}, 310 {"HZIP_MAX_DELAY ", 0x20ull}, 311 }; 312 313 /* define the ZIP's dfx regs region and region length */ 314 static struct dfx_diff_registers hzip_diff_regs[] = { 315 { 316 .reg_offset = HZIP_CORE_DFX_BASE, 317 .reg_len = HZIP_CORE_REGS_BASE_LEN, 318 }, { 319 .reg_offset = HZIP_CORE_DFX_COMP_0, 320 .reg_len = HZIP_CORE_REGS_DFX_LEN, 321 }, { 322 .reg_offset = HZIP_CORE_DFX_COMP_1, 323 .reg_len = HZIP_CORE_REGS_DFX_LEN, 324 }, { 325 .reg_offset = HZIP_CORE_DFX_DECOMP_0, 326 .reg_len = HZIP_CORE_REGS_DFX_LEN, 327 }, { 328 .reg_offset = HZIP_CORE_DFX_DECOMP_1, 329 .reg_len = HZIP_CORE_REGS_DFX_LEN, 330 }, { 331 .reg_offset = HZIP_CORE_DFX_DECOMP_2, 332 .reg_len = HZIP_CORE_REGS_DFX_LEN, 333 }, { 334 .reg_offset = HZIP_CORE_DFX_DECOMP_3, 335 .reg_len = HZIP_CORE_REGS_DFX_LEN, 336 }, { 337 .reg_offset = HZIP_CORE_DFX_DECOMP_4, 338 .reg_len = HZIP_CORE_REGS_DFX_LEN, 339 }, { 340 .reg_offset = HZIP_CORE_DFX_DECOMP_5, 341 .reg_len = HZIP_CORE_REGS_DFX_LEN, 342 }, 343 }; 344 345 static int hzip_diff_regs_show(struct seq_file *s, void *unused) 346 { 347 struct hisi_qm *qm = s->private; 348 349 hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.acc_diff_regs, 350 ARRAY_SIZE(hzip_diff_regs)); 351 352 return 0; 353 } 354 DEFINE_SHOW_ATTRIBUTE(hzip_diff_regs); 355 static const struct kernel_param_ops zip_uacce_mode_ops = { 356 .set = uacce_mode_set, 357 .get = param_get_int, 358 }; 359 360 /* 361 * uacce_mode = 0 means zip only register to crypto, 362 * uacce_mode = 1 means zip both register to crypto and uacce. 363 */ 364 static u32 uacce_mode = UACCE_MODE_NOUACCE; 365 module_param_cb(uacce_mode, &zip_uacce_mode_ops, &uacce_mode, 0444); 366 MODULE_PARM_DESC(uacce_mode, UACCE_MODE_DESC); 367 368 static int pf_q_num_set(const char *val, const struct kernel_param *kp) 369 { 370 return q_num_set(val, kp, PCI_DEVICE_ID_HUAWEI_ZIP_PF); 371 } 372 373 static const struct kernel_param_ops pf_q_num_ops = { 374 .set = pf_q_num_set, 375 .get = param_get_int, 376 }; 377 378 static u32 pf_q_num = HZIP_PF_DEF_Q_NUM; 379 module_param_cb(pf_q_num, &pf_q_num_ops, &pf_q_num, 0444); 380 MODULE_PARM_DESC(pf_q_num, "Number of queues in PF(v1 2-4096, v2 2-1024)"); 381 382 static const struct kernel_param_ops vfs_num_ops = { 383 .set = vfs_num_set, 384 .get = param_get_int, 385 }; 386 387 static u32 vfs_num; 388 module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444); 389 MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)"); 390 391 static const struct pci_device_id hisi_zip_dev_ids[] = { 392 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_ZIP_PF) }, 393 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_ZIP_VF) }, 394 { 0, } 395 }; 396 MODULE_DEVICE_TABLE(pci, hisi_zip_dev_ids); 397 398 int zip_create_qps(struct hisi_qp **qps, int qp_num, int node) 399 { 400 if (node == NUMA_NO_NODE) 401 node = cpu_to_node(smp_processor_id()); 402 403 return hisi_qm_alloc_qps_node(&zip_devices, qp_num, 0, node, qps); 404 } 405 406 bool hisi_zip_alg_support(struct hisi_qm *qm, u32 alg) 407 { 408 u32 cap_val; 409 410 cap_val = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_DRV_ALG_BITMAP, qm->cap_ver); 411 if ((alg & cap_val) == alg) 412 return true; 413 414 return false; 415 } 416 417 static int hisi_zip_set_qm_algs(struct hisi_qm *qm) 418 { 419 struct device *dev = &qm->pdev->dev; 420 char *algs, *ptr; 421 u32 alg_mask; 422 int i; 423 424 if (!qm->use_sva) 425 return 0; 426 427 algs = devm_kzalloc(dev, HZIP_DEV_ALG_MAX_LEN * sizeof(char), GFP_KERNEL); 428 if (!algs) 429 return -ENOMEM; 430 431 alg_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_DEV_ALG_BITMAP, qm->cap_ver); 432 433 for (i = 0; i < ARRAY_SIZE(zip_dev_algs); i++) 434 if (alg_mask & zip_dev_algs[i].alg_msk) 435 strcat(algs, zip_dev_algs[i].algs); 436 437 ptr = strrchr(algs, '\n'); 438 if (ptr) 439 *ptr = '\0'; 440 441 qm->uacce->algs = algs; 442 443 return 0; 444 } 445 446 static void hisi_zip_open_sva_prefetch(struct hisi_qm *qm) 447 { 448 u32 val; 449 int ret; 450 451 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) 452 return; 453 454 /* Enable prefetch */ 455 val = readl_relaxed(qm->io_base + HZIP_PREFETCH_CFG); 456 val &= HZIP_PREFETCH_ENABLE; 457 writel(val, qm->io_base + HZIP_PREFETCH_CFG); 458 459 ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_PREFETCH_CFG, 460 val, !(val & HZIP_SVA_PREFETCH_DISABLE), 461 HZIP_DELAY_1_US, HZIP_POLL_TIMEOUT_US); 462 if (ret) 463 pci_err(qm->pdev, "failed to open sva prefetch\n"); 464 } 465 466 static void hisi_zip_close_sva_prefetch(struct hisi_qm *qm) 467 { 468 u32 val; 469 int ret; 470 471 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) 472 return; 473 474 val = readl_relaxed(qm->io_base + HZIP_PREFETCH_CFG); 475 val |= HZIP_SVA_PREFETCH_DISABLE; 476 writel(val, qm->io_base + HZIP_PREFETCH_CFG); 477 478 ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_SVA_TRANS, 479 val, !(val & HZIP_SVA_DISABLE_READY), 480 HZIP_DELAY_1_US, HZIP_POLL_TIMEOUT_US); 481 if (ret) 482 pci_err(qm->pdev, "failed to close sva prefetch\n"); 483 } 484 485 static void hisi_zip_enable_clock_gate(struct hisi_qm *qm) 486 { 487 u32 val; 488 489 if (qm->ver < QM_HW_V3) 490 return; 491 492 val = readl(qm->io_base + HZIP_CLOCK_GATE_CTRL); 493 val |= HZIP_CLOCK_GATED_EN; 494 writel(val, qm->io_base + HZIP_CLOCK_GATE_CTRL); 495 496 val = readl(qm->io_base + HZIP_PEH_CFG_AUTO_GATE); 497 val |= HZIP_PEH_CFG_AUTO_GATE_EN; 498 writel(val, qm->io_base + HZIP_PEH_CFG_AUTO_GATE); 499 } 500 501 static int hisi_zip_set_user_domain_and_cache(struct hisi_qm *qm) 502 { 503 void __iomem *base = qm->io_base; 504 u32 dcomp_bm, comp_bm; 505 506 /* qm user domain */ 507 writel(AXUSER_BASE, base + QM_ARUSER_M_CFG_1); 508 writel(ARUSER_M_CFG_ENABLE, base + QM_ARUSER_M_CFG_ENABLE); 509 writel(AXUSER_BASE, base + QM_AWUSER_M_CFG_1); 510 writel(AWUSER_M_CFG_ENABLE, base + QM_AWUSER_M_CFG_ENABLE); 511 writel(WUSER_M_CFG_ENABLE, base + QM_WUSER_M_CFG_ENABLE); 512 513 /* qm cache */ 514 writel(AXI_M_CFG, base + QM_AXI_M_CFG); 515 writel(AXI_M_CFG_ENABLE, base + QM_AXI_M_CFG_ENABLE); 516 517 /* disable FLR triggered by BME(bus master enable) */ 518 writel(PEH_AXUSER_CFG, base + QM_PEH_AXUSER_CFG); 519 writel(PEH_AXUSER_CFG_ENABLE, base + QM_PEH_AXUSER_CFG_ENABLE); 520 521 /* cache */ 522 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_ARCA_CHE_0); 523 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_ARCA_CHE_1); 524 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_AWCA_CHE_0); 525 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_AWCA_CHE_1); 526 527 /* user domain configurations */ 528 writel(AXUSER_BASE, base + HZIP_BD_RUSER_32_63); 529 writel(AXUSER_BASE, base + HZIP_BD_WUSER_32_63); 530 531 if (qm->use_sva && qm->ver == QM_HW_V2) { 532 writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_DATA_RUSER_32_63); 533 writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_DATA_WUSER_32_63); 534 writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_SGL_RUSER_32_63); 535 } else { 536 writel(AXUSER_BASE, base + HZIP_DATA_RUSER_32_63); 537 writel(AXUSER_BASE, base + HZIP_DATA_WUSER_32_63); 538 writel(AXUSER_BASE, base + HZIP_SGL_RUSER_32_63); 539 } 540 541 /* let's open all compression/decompression cores */ 542 dcomp_bm = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 543 ZIP_DECOMP_ENABLE_BITMAP, qm->cap_ver); 544 comp_bm = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 545 ZIP_COMP_ENABLE_BITMAP, qm->cap_ver); 546 writel(HZIP_DECOMP_CHECK_ENABLE | dcomp_bm | comp_bm, base + HZIP_CLOCK_GATE_CTRL); 547 548 /* enable sqc,cqc writeback */ 549 writel(SQC_CACHE_ENABLE | CQC_CACHE_ENABLE | SQC_CACHE_WB_ENABLE | 550 CQC_CACHE_WB_ENABLE | FIELD_PREP(SQC_CACHE_WB_THRD, 1) | 551 FIELD_PREP(CQC_CACHE_WB_THRD, 1), base + QM_CACHE_CTL); 552 553 hisi_zip_enable_clock_gate(qm); 554 555 return 0; 556 } 557 558 static void hisi_zip_master_ooo_ctrl(struct hisi_qm *qm, bool enable) 559 { 560 u32 val1, val2; 561 562 val1 = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 563 if (enable) { 564 val1 |= HZIP_AXI_SHUTDOWN_ENABLE; 565 val2 = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 566 ZIP_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 567 } else { 568 val1 &= ~HZIP_AXI_SHUTDOWN_ENABLE; 569 val2 = 0x0; 570 } 571 572 if (qm->ver > QM_HW_V2) 573 writel(val2, qm->io_base + HZIP_OOO_SHUTDOWN_SEL); 574 575 writel(val1, qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 576 } 577 578 static void hisi_zip_hw_error_enable(struct hisi_qm *qm) 579 { 580 u32 nfe, ce; 581 582 if (qm->ver == QM_HW_V1) { 583 writel(HZIP_CORE_INT_MASK_ALL, 584 qm->io_base + HZIP_CORE_INT_MASK_REG); 585 dev_info(&qm->pdev->dev, "Does not support hw error handle\n"); 586 return; 587 } 588 589 nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_NFE_MASK_CAP, qm->cap_ver); 590 ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CE_MASK_CAP, qm->cap_ver); 591 592 /* clear ZIP hw error source if having */ 593 writel(ce | nfe | HZIP_CORE_INT_RAS_FE_ENB_MASK, qm->io_base + HZIP_CORE_INT_SOURCE); 594 595 /* configure error type */ 596 writel(ce, qm->io_base + HZIP_CORE_INT_RAS_CE_ENB); 597 writel(HZIP_CORE_INT_RAS_FE_ENB_MASK, qm->io_base + HZIP_CORE_INT_RAS_FE_ENB); 598 writel(nfe, qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 599 600 hisi_zip_master_ooo_ctrl(qm, true); 601 602 /* enable ZIP hw error interrupts */ 603 writel(0, qm->io_base + HZIP_CORE_INT_MASK_REG); 604 } 605 606 static void hisi_zip_hw_error_disable(struct hisi_qm *qm) 607 { 608 u32 nfe, ce; 609 610 /* disable ZIP hw error interrupts */ 611 nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_NFE_MASK_CAP, qm->cap_ver); 612 ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CE_MASK_CAP, qm->cap_ver); 613 writel(ce | nfe | HZIP_CORE_INT_RAS_FE_ENB_MASK, qm->io_base + HZIP_CORE_INT_MASK_REG); 614 615 hisi_zip_master_ooo_ctrl(qm, false); 616 } 617 618 static inline struct hisi_qm *file_to_qm(struct ctrl_debug_file *file) 619 { 620 struct hisi_zip *hisi_zip = file->ctrl->hisi_zip; 621 622 return &hisi_zip->qm; 623 } 624 625 static u32 clear_enable_read(struct hisi_qm *qm) 626 { 627 return readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) & 628 HZIP_SOFT_CTRL_CNT_CLR_CE_BIT; 629 } 630 631 static int clear_enable_write(struct hisi_qm *qm, u32 val) 632 { 633 u32 tmp; 634 635 if (val != 1 && val != 0) 636 return -EINVAL; 637 638 tmp = (readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) & 639 ~HZIP_SOFT_CTRL_CNT_CLR_CE_BIT) | val; 640 writel(tmp, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); 641 642 return 0; 643 } 644 645 static ssize_t hisi_zip_ctrl_debug_read(struct file *filp, char __user *buf, 646 size_t count, loff_t *pos) 647 { 648 struct ctrl_debug_file *file = filp->private_data; 649 struct hisi_qm *qm = file_to_qm(file); 650 char tbuf[HZIP_BUF_SIZE]; 651 u32 val; 652 int ret; 653 654 ret = hisi_qm_get_dfx_access(qm); 655 if (ret) 656 return ret; 657 658 spin_lock_irq(&file->lock); 659 switch (file->index) { 660 case HZIP_CLEAR_ENABLE: 661 val = clear_enable_read(qm); 662 break; 663 default: 664 goto err_input; 665 } 666 spin_unlock_irq(&file->lock); 667 668 hisi_qm_put_dfx_access(qm); 669 ret = scnprintf(tbuf, sizeof(tbuf), "%u\n", val); 670 return simple_read_from_buffer(buf, count, pos, tbuf, ret); 671 672 err_input: 673 spin_unlock_irq(&file->lock); 674 hisi_qm_put_dfx_access(qm); 675 return -EINVAL; 676 } 677 678 static ssize_t hisi_zip_ctrl_debug_write(struct file *filp, 679 const char __user *buf, 680 size_t count, loff_t *pos) 681 { 682 struct ctrl_debug_file *file = filp->private_data; 683 struct hisi_qm *qm = file_to_qm(file); 684 char tbuf[HZIP_BUF_SIZE]; 685 unsigned long val; 686 int len, ret; 687 688 if (*pos != 0) 689 return 0; 690 691 if (count >= HZIP_BUF_SIZE) 692 return -ENOSPC; 693 694 len = simple_write_to_buffer(tbuf, HZIP_BUF_SIZE - 1, pos, buf, count); 695 if (len < 0) 696 return len; 697 698 tbuf[len] = '\0'; 699 ret = kstrtoul(tbuf, 0, &val); 700 if (ret) 701 return ret; 702 703 ret = hisi_qm_get_dfx_access(qm); 704 if (ret) 705 return ret; 706 707 spin_lock_irq(&file->lock); 708 switch (file->index) { 709 case HZIP_CLEAR_ENABLE: 710 ret = clear_enable_write(qm, val); 711 if (ret) 712 goto err_input; 713 break; 714 default: 715 ret = -EINVAL; 716 goto err_input; 717 } 718 719 ret = count; 720 721 err_input: 722 spin_unlock_irq(&file->lock); 723 hisi_qm_put_dfx_access(qm); 724 return ret; 725 } 726 727 static const struct file_operations ctrl_debug_fops = { 728 .owner = THIS_MODULE, 729 .open = simple_open, 730 .read = hisi_zip_ctrl_debug_read, 731 .write = hisi_zip_ctrl_debug_write, 732 }; 733 734 static int zip_debugfs_atomic64_set(void *data, u64 val) 735 { 736 if (val) 737 return -EINVAL; 738 739 atomic64_set((atomic64_t *)data, 0); 740 741 return 0; 742 } 743 744 static int zip_debugfs_atomic64_get(void *data, u64 *val) 745 { 746 *val = atomic64_read((atomic64_t *)data); 747 748 return 0; 749 } 750 751 DEFINE_DEBUGFS_ATTRIBUTE(zip_atomic64_ops, zip_debugfs_atomic64_get, 752 zip_debugfs_atomic64_set, "%llu\n"); 753 754 static int hisi_zip_regs_show(struct seq_file *s, void *unused) 755 { 756 hisi_qm_regs_dump(s, s->private); 757 758 return 0; 759 } 760 761 DEFINE_SHOW_ATTRIBUTE(hisi_zip_regs); 762 763 static int hisi_zip_core_debug_init(struct hisi_qm *qm) 764 { 765 u32 zip_core_num, zip_comp_core_num; 766 struct device *dev = &qm->pdev->dev; 767 struct debugfs_regset32 *regset; 768 struct dentry *tmp_d; 769 char buf[HZIP_BUF_SIZE]; 770 int i; 771 772 zip_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CORE_NUM_CAP, qm->cap_ver); 773 zip_comp_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CLUSTER_COMP_NUM_CAP, 774 qm->cap_ver); 775 776 for (i = 0; i < zip_core_num; i++) { 777 if (i < zip_comp_core_num) 778 scnprintf(buf, sizeof(buf), "comp_core%d", i); 779 else 780 scnprintf(buf, sizeof(buf), "decomp_core%d", 781 i - zip_comp_core_num); 782 783 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 784 if (!regset) 785 return -ENOENT; 786 787 regset->regs = hzip_dfx_regs; 788 regset->nregs = ARRAY_SIZE(hzip_dfx_regs); 789 regset->base = qm->io_base + core_offsets[i]; 790 regset->dev = dev; 791 792 tmp_d = debugfs_create_dir(buf, qm->debug.debug_root); 793 debugfs_create_file("regs", 0444, tmp_d, regset, 794 &hisi_zip_regs_fops); 795 } 796 797 return 0; 798 } 799 800 static void hisi_zip_dfx_debug_init(struct hisi_qm *qm) 801 { 802 struct dfx_diff_registers *hzip_regs = qm->debug.acc_diff_regs; 803 struct hisi_zip *zip = container_of(qm, struct hisi_zip, qm); 804 struct hisi_zip_dfx *dfx = &zip->dfx; 805 struct dentry *tmp_dir; 806 void *data; 807 int i; 808 809 tmp_dir = debugfs_create_dir("zip_dfx", qm->debug.debug_root); 810 for (i = 0; i < ARRAY_SIZE(zip_dfx_files); i++) { 811 data = (atomic64_t *)((uintptr_t)dfx + zip_dfx_files[i].offset); 812 debugfs_create_file(zip_dfx_files[i].name, 813 0644, tmp_dir, data, 814 &zip_atomic64_ops); 815 } 816 817 if (qm->fun_type == QM_HW_PF && hzip_regs) 818 debugfs_create_file("diff_regs", 0444, tmp_dir, 819 qm, &hzip_diff_regs_fops); 820 } 821 822 static int hisi_zip_ctrl_debug_init(struct hisi_qm *qm) 823 { 824 struct hisi_zip *zip = container_of(qm, struct hisi_zip, qm); 825 int i; 826 827 for (i = HZIP_CLEAR_ENABLE; i < HZIP_DEBUG_FILE_NUM; i++) { 828 spin_lock_init(&zip->ctrl->files[i].lock); 829 zip->ctrl->files[i].ctrl = zip->ctrl; 830 zip->ctrl->files[i].index = i; 831 832 debugfs_create_file(ctrl_debug_file_name[i], 0600, 833 qm->debug.debug_root, 834 zip->ctrl->files + i, 835 &ctrl_debug_fops); 836 } 837 838 return hisi_zip_core_debug_init(qm); 839 } 840 841 static int hisi_zip_debugfs_init(struct hisi_qm *qm) 842 { 843 struct device *dev = &qm->pdev->dev; 844 struct dentry *dev_d; 845 int ret; 846 847 dev_d = debugfs_create_dir(dev_name(dev), hzip_debugfs_root); 848 849 qm->debug.sqe_mask_offset = HZIP_SQE_MASK_OFFSET; 850 qm->debug.sqe_mask_len = HZIP_SQE_MASK_LEN; 851 qm->debug.debug_root = dev_d; 852 ret = hisi_qm_diff_regs_init(qm, hzip_diff_regs, 853 ARRAY_SIZE(hzip_diff_regs)); 854 if (ret) { 855 dev_warn(dev, "Failed to init ZIP diff regs!\n"); 856 goto debugfs_remove; 857 } 858 859 hisi_qm_debug_init(qm); 860 861 if (qm->fun_type == QM_HW_PF) { 862 ret = hisi_zip_ctrl_debug_init(qm); 863 if (ret) 864 goto failed_to_create; 865 } 866 867 hisi_zip_dfx_debug_init(qm); 868 869 return 0; 870 871 failed_to_create: 872 hisi_qm_diff_regs_uninit(qm, ARRAY_SIZE(hzip_diff_regs)); 873 debugfs_remove: 874 debugfs_remove_recursive(hzip_debugfs_root); 875 return ret; 876 } 877 878 /* hisi_zip_debug_regs_clear() - clear the zip debug regs */ 879 static void hisi_zip_debug_regs_clear(struct hisi_qm *qm) 880 { 881 int i, j; 882 883 /* enable register read_clear bit */ 884 writel(HZIP_RD_CNT_CLR_CE_EN, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); 885 for (i = 0; i < ARRAY_SIZE(core_offsets); i++) 886 for (j = 0; j < ARRAY_SIZE(hzip_dfx_regs); j++) 887 readl(qm->io_base + core_offsets[i] + 888 hzip_dfx_regs[j].offset); 889 890 /* disable register read_clear bit */ 891 writel(0x0, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); 892 893 hisi_qm_debug_regs_clear(qm); 894 } 895 896 static void hisi_zip_debugfs_exit(struct hisi_qm *qm) 897 { 898 hisi_qm_diff_regs_uninit(qm, ARRAY_SIZE(hzip_diff_regs)); 899 900 debugfs_remove_recursive(qm->debug.debug_root); 901 902 if (qm->fun_type == QM_HW_PF) { 903 hisi_zip_debug_regs_clear(qm); 904 qm->debug.curr_qm_qp_num = 0; 905 } 906 } 907 908 static int hisi_zip_show_last_regs_init(struct hisi_qm *qm) 909 { 910 int core_dfx_regs_num = ARRAY_SIZE(hzip_dump_dfx_regs); 911 int com_dfx_regs_num = ARRAY_SIZE(hzip_com_dfx_regs); 912 struct qm_debug *debug = &qm->debug; 913 void __iomem *io_base; 914 u32 zip_core_num; 915 int i, j, idx; 916 917 zip_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CORE_NUM_CAP, qm->cap_ver); 918 919 debug->last_words = kcalloc(core_dfx_regs_num * zip_core_num + com_dfx_regs_num, 920 sizeof(unsigned int), GFP_KERNEL); 921 if (!debug->last_words) 922 return -ENOMEM; 923 924 for (i = 0; i < com_dfx_regs_num; i++) { 925 io_base = qm->io_base + hzip_com_dfx_regs[i].offset; 926 debug->last_words[i] = readl_relaxed(io_base); 927 } 928 929 for (i = 0; i < zip_core_num; i++) { 930 io_base = qm->io_base + core_offsets[i]; 931 for (j = 0; j < core_dfx_regs_num; j++) { 932 idx = com_dfx_regs_num + i * core_dfx_regs_num + j; 933 debug->last_words[idx] = readl_relaxed( 934 io_base + hzip_dump_dfx_regs[j].offset); 935 } 936 } 937 938 return 0; 939 } 940 941 static void hisi_zip_show_last_regs_uninit(struct hisi_qm *qm) 942 { 943 struct qm_debug *debug = &qm->debug; 944 945 if (qm->fun_type == QM_HW_VF || !debug->last_words) 946 return; 947 948 kfree(debug->last_words); 949 debug->last_words = NULL; 950 } 951 952 static void hisi_zip_show_last_dfx_regs(struct hisi_qm *qm) 953 { 954 int core_dfx_regs_num = ARRAY_SIZE(hzip_dump_dfx_regs); 955 int com_dfx_regs_num = ARRAY_SIZE(hzip_com_dfx_regs); 956 u32 zip_core_num, zip_comp_core_num; 957 struct qm_debug *debug = &qm->debug; 958 char buf[HZIP_BUF_SIZE]; 959 void __iomem *base; 960 int i, j, idx; 961 u32 val; 962 963 if (qm->fun_type == QM_HW_VF || !debug->last_words) 964 return; 965 966 for (i = 0; i < com_dfx_regs_num; i++) { 967 val = readl_relaxed(qm->io_base + hzip_com_dfx_regs[i].offset); 968 if (debug->last_words[i] != val) 969 pci_info(qm->pdev, "com_dfx: %s \t= 0x%08x => 0x%08x\n", 970 hzip_com_dfx_regs[i].name, debug->last_words[i], val); 971 } 972 973 zip_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CORE_NUM_CAP, qm->cap_ver); 974 zip_comp_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CLUSTER_COMP_NUM_CAP, 975 qm->cap_ver); 976 for (i = 0; i < zip_core_num; i++) { 977 if (i < zip_comp_core_num) 978 scnprintf(buf, sizeof(buf), "Comp_core-%d", i); 979 else 980 scnprintf(buf, sizeof(buf), "Decomp_core-%d", 981 i - zip_comp_core_num); 982 base = qm->io_base + core_offsets[i]; 983 984 pci_info(qm->pdev, "==>%s:\n", buf); 985 /* dump last word for dfx regs during control resetting */ 986 for (j = 0; j < core_dfx_regs_num; j++) { 987 idx = com_dfx_regs_num + i * core_dfx_regs_num + j; 988 val = readl_relaxed(base + hzip_dump_dfx_regs[j].offset); 989 if (debug->last_words[idx] != val) 990 pci_info(qm->pdev, "%s \t= 0x%08x => 0x%08x\n", 991 hzip_dump_dfx_regs[j].name, 992 debug->last_words[idx], val); 993 } 994 } 995 } 996 997 static void hisi_zip_log_hw_error(struct hisi_qm *qm, u32 err_sts) 998 { 999 const struct hisi_zip_hw_error *err = zip_hw_error; 1000 struct device *dev = &qm->pdev->dev; 1001 u32 err_val; 1002 1003 while (err->msg) { 1004 if (err->int_msk & err_sts) { 1005 dev_err(dev, "%s [error status=0x%x] found\n", 1006 err->msg, err->int_msk); 1007 1008 if (err->int_msk & HZIP_CORE_INT_STATUS_M_ECC) { 1009 err_val = readl(qm->io_base + 1010 HZIP_CORE_SRAM_ECC_ERR_INFO); 1011 dev_err(dev, "hisi-zip multi ecc sram num=0x%x\n", 1012 ((err_val >> 1013 HZIP_SRAM_ECC_ERR_NUM_SHIFT) & 0xFF)); 1014 } 1015 } 1016 err++; 1017 } 1018 } 1019 1020 static u32 hisi_zip_get_hw_err_status(struct hisi_qm *qm) 1021 { 1022 return readl(qm->io_base + HZIP_CORE_INT_STATUS); 1023 } 1024 1025 static void hisi_zip_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts) 1026 { 1027 u32 nfe; 1028 1029 writel(err_sts, qm->io_base + HZIP_CORE_INT_SOURCE); 1030 nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_NFE_MASK_CAP, qm->cap_ver); 1031 writel(nfe, qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 1032 } 1033 1034 static void hisi_zip_open_axi_master_ooo(struct hisi_qm *qm) 1035 { 1036 u32 val; 1037 1038 val = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 1039 1040 writel(val & ~HZIP_AXI_SHUTDOWN_ENABLE, 1041 qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 1042 1043 writel(val | HZIP_AXI_SHUTDOWN_ENABLE, 1044 qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); 1045 } 1046 1047 static void hisi_zip_close_axi_master_ooo(struct hisi_qm *qm) 1048 { 1049 u32 nfe_enb; 1050 1051 /* Disable ECC Mbit error report. */ 1052 nfe_enb = readl(qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 1053 writel(nfe_enb & ~HZIP_CORE_INT_STATUS_M_ECC, 1054 qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); 1055 1056 /* Inject zip ECC Mbit error to block master ooo. */ 1057 writel(HZIP_CORE_INT_STATUS_M_ECC, 1058 qm->io_base + HZIP_CORE_INT_SET); 1059 } 1060 1061 static void hisi_zip_err_info_init(struct hisi_qm *qm) 1062 { 1063 struct hisi_qm_err_info *err_info = &qm->err_info; 1064 1065 err_info->fe = HZIP_CORE_INT_RAS_FE_ENB_MASK; 1066 err_info->ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_QM_CE_MASK_CAP, qm->cap_ver); 1067 err_info->nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1068 ZIP_QM_NFE_MASK_CAP, qm->cap_ver); 1069 err_info->ecc_2bits_mask = HZIP_CORE_INT_STATUS_M_ECC; 1070 err_info->qm_shutdown_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1071 ZIP_QM_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 1072 err_info->dev_shutdown_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1073 ZIP_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); 1074 err_info->qm_reset_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1075 ZIP_QM_RESET_MASK_CAP, qm->cap_ver); 1076 err_info->dev_reset_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, 1077 ZIP_RESET_MASK_CAP, qm->cap_ver); 1078 err_info->msi_wr_port = HZIP_WR_PORT; 1079 err_info->acpi_rst = "ZRST"; 1080 } 1081 1082 static const struct hisi_qm_err_ini hisi_zip_err_ini = { 1083 .hw_init = hisi_zip_set_user_domain_and_cache, 1084 .hw_err_enable = hisi_zip_hw_error_enable, 1085 .hw_err_disable = hisi_zip_hw_error_disable, 1086 .get_dev_hw_err_status = hisi_zip_get_hw_err_status, 1087 .clear_dev_hw_err_status = hisi_zip_clear_hw_err_status, 1088 .log_dev_hw_err = hisi_zip_log_hw_error, 1089 .open_axi_master_ooo = hisi_zip_open_axi_master_ooo, 1090 .close_axi_master_ooo = hisi_zip_close_axi_master_ooo, 1091 .open_sva_prefetch = hisi_zip_open_sva_prefetch, 1092 .close_sva_prefetch = hisi_zip_close_sva_prefetch, 1093 .show_last_dfx_regs = hisi_zip_show_last_dfx_regs, 1094 .err_info_init = hisi_zip_err_info_init, 1095 }; 1096 1097 static int hisi_zip_pf_probe_init(struct hisi_zip *hisi_zip) 1098 { 1099 struct hisi_qm *qm = &hisi_zip->qm; 1100 struct hisi_zip_ctrl *ctrl; 1101 int ret; 1102 1103 ctrl = devm_kzalloc(&qm->pdev->dev, sizeof(*ctrl), GFP_KERNEL); 1104 if (!ctrl) 1105 return -ENOMEM; 1106 1107 hisi_zip->ctrl = ctrl; 1108 ctrl->hisi_zip = hisi_zip; 1109 qm->err_ini = &hisi_zip_err_ini; 1110 qm->err_ini->err_info_init(qm); 1111 1112 ret = hisi_zip_set_user_domain_and_cache(qm); 1113 if (ret) 1114 return ret; 1115 1116 hisi_zip_open_sva_prefetch(qm); 1117 hisi_qm_dev_err_init(qm); 1118 hisi_zip_debug_regs_clear(qm); 1119 1120 ret = hisi_zip_show_last_regs_init(qm); 1121 if (ret) 1122 pci_err(qm->pdev, "Failed to init last word regs!\n"); 1123 1124 return ret; 1125 } 1126 1127 static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) 1128 { 1129 int ret; 1130 1131 qm->pdev = pdev; 1132 qm->ver = pdev->revision; 1133 qm->mode = uacce_mode; 1134 qm->sqe_size = HZIP_SQE_SIZE; 1135 qm->dev_name = hisi_zip_name; 1136 1137 qm->fun_type = (pdev->device == PCI_DEVICE_ID_HUAWEI_ZIP_PF) ? 1138 QM_HW_PF : QM_HW_VF; 1139 if (qm->fun_type == QM_HW_PF) { 1140 qm->qp_base = HZIP_PF_DEF_Q_BASE; 1141 qm->qp_num = pf_q_num; 1142 qm->debug.curr_qm_qp_num = pf_q_num; 1143 qm->qm_list = &zip_devices; 1144 } else if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V1) { 1145 /* 1146 * have no way to get qm configure in VM in v1 hardware, 1147 * so currently force PF to uses HZIP_PF_DEF_Q_NUM, and force 1148 * to trigger only one VF in v1 hardware. 1149 * 1150 * v2 hardware has no such problem. 1151 */ 1152 qm->qp_base = HZIP_PF_DEF_Q_NUM; 1153 qm->qp_num = HZIP_QUEUE_NUM_V1 - HZIP_PF_DEF_Q_NUM; 1154 } 1155 1156 ret = hisi_qm_init(qm); 1157 if (ret) { 1158 pci_err(qm->pdev, "Failed to init zip qm configures!\n"); 1159 return ret; 1160 } 1161 1162 ret = hisi_zip_set_qm_algs(qm); 1163 if (ret) { 1164 pci_err(qm->pdev, "Failed to set zip algs!\n"); 1165 hisi_qm_uninit(qm); 1166 } 1167 1168 return ret; 1169 } 1170 1171 static void hisi_zip_qm_uninit(struct hisi_qm *qm) 1172 { 1173 hisi_qm_uninit(qm); 1174 } 1175 1176 static int hisi_zip_probe_init(struct hisi_zip *hisi_zip) 1177 { 1178 u32 type_rate = HZIP_SHAPER_RATE_COMPRESS; 1179 struct hisi_qm *qm = &hisi_zip->qm; 1180 int ret; 1181 1182 if (qm->fun_type == QM_HW_PF) { 1183 ret = hisi_zip_pf_probe_init(hisi_zip); 1184 if (ret) 1185 return ret; 1186 /* enable shaper type 0 */ 1187 if (qm->ver >= QM_HW_V3) { 1188 type_rate |= QM_SHAPER_ENABLE; 1189 1190 /* ZIP need to enable shaper type 1 */ 1191 type_rate |= HZIP_SHAPER_RATE_DECOMPRESS << QM_SHAPER_TYPE1_OFFSET; 1192 qm->type_rate = type_rate; 1193 } 1194 } 1195 1196 return 0; 1197 } 1198 1199 static int hisi_zip_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1200 { 1201 struct hisi_zip *hisi_zip; 1202 struct hisi_qm *qm; 1203 int ret; 1204 1205 hisi_zip = devm_kzalloc(&pdev->dev, sizeof(*hisi_zip), GFP_KERNEL); 1206 if (!hisi_zip) 1207 return -ENOMEM; 1208 1209 qm = &hisi_zip->qm; 1210 1211 ret = hisi_zip_qm_init(qm, pdev); 1212 if (ret) { 1213 pci_err(pdev, "Failed to init ZIP QM (%d)!\n", ret); 1214 return ret; 1215 } 1216 1217 ret = hisi_zip_probe_init(hisi_zip); 1218 if (ret) { 1219 pci_err(pdev, "Failed to probe (%d)!\n", ret); 1220 goto err_qm_uninit; 1221 } 1222 1223 ret = hisi_qm_start(qm); 1224 if (ret) 1225 goto err_dev_err_uninit; 1226 1227 ret = hisi_zip_debugfs_init(qm); 1228 if (ret) 1229 pci_err(pdev, "failed to init debugfs (%d)!\n", ret); 1230 1231 ret = hisi_qm_alg_register(qm, &zip_devices); 1232 if (ret < 0) { 1233 pci_err(pdev, "failed to register driver to crypto!\n"); 1234 goto err_qm_stop; 1235 } 1236 1237 if (qm->uacce) { 1238 ret = uacce_register(qm->uacce); 1239 if (ret) { 1240 pci_err(pdev, "failed to register uacce (%d)!\n", ret); 1241 goto err_qm_alg_unregister; 1242 } 1243 } 1244 1245 if (qm->fun_type == QM_HW_PF && vfs_num > 0) { 1246 ret = hisi_qm_sriov_enable(pdev, vfs_num); 1247 if (ret < 0) 1248 goto err_qm_alg_unregister; 1249 } 1250 1251 hisi_qm_pm_init(qm); 1252 1253 return 0; 1254 1255 err_qm_alg_unregister: 1256 hisi_qm_alg_unregister(qm, &zip_devices); 1257 1258 err_qm_stop: 1259 hisi_zip_debugfs_exit(qm); 1260 hisi_qm_stop(qm, QM_NORMAL); 1261 1262 err_dev_err_uninit: 1263 hisi_zip_show_last_regs_uninit(qm); 1264 hisi_qm_dev_err_uninit(qm); 1265 1266 err_qm_uninit: 1267 hisi_zip_qm_uninit(qm); 1268 1269 return ret; 1270 } 1271 1272 static void hisi_zip_remove(struct pci_dev *pdev) 1273 { 1274 struct hisi_qm *qm = pci_get_drvdata(pdev); 1275 1276 hisi_qm_pm_uninit(qm); 1277 hisi_qm_wait_task_finish(qm, &zip_devices); 1278 hisi_qm_alg_unregister(qm, &zip_devices); 1279 1280 if (qm->fun_type == QM_HW_PF && qm->vfs_num) 1281 hisi_qm_sriov_disable(pdev, true); 1282 1283 hisi_zip_debugfs_exit(qm); 1284 hisi_qm_stop(qm, QM_NORMAL); 1285 hisi_zip_show_last_regs_uninit(qm); 1286 hisi_qm_dev_err_uninit(qm); 1287 hisi_zip_qm_uninit(qm); 1288 } 1289 1290 static const struct dev_pm_ops hisi_zip_pm_ops = { 1291 SET_RUNTIME_PM_OPS(hisi_qm_suspend, hisi_qm_resume, NULL) 1292 }; 1293 1294 static const struct pci_error_handlers hisi_zip_err_handler = { 1295 .error_detected = hisi_qm_dev_err_detected, 1296 .slot_reset = hisi_qm_dev_slot_reset, 1297 .reset_prepare = hisi_qm_reset_prepare, 1298 .reset_done = hisi_qm_reset_done, 1299 }; 1300 1301 static struct pci_driver hisi_zip_pci_driver = { 1302 .name = "hisi_zip", 1303 .id_table = hisi_zip_dev_ids, 1304 .probe = hisi_zip_probe, 1305 .remove = hisi_zip_remove, 1306 .sriov_configure = IS_ENABLED(CONFIG_PCI_IOV) ? 1307 hisi_qm_sriov_configure : NULL, 1308 .err_handler = &hisi_zip_err_handler, 1309 .shutdown = hisi_qm_dev_shutdown, 1310 .driver.pm = &hisi_zip_pm_ops, 1311 }; 1312 1313 struct pci_driver *hisi_zip_get_pf_driver(void) 1314 { 1315 return &hisi_zip_pci_driver; 1316 } 1317 EXPORT_SYMBOL_GPL(hisi_zip_get_pf_driver); 1318 1319 static void hisi_zip_register_debugfs(void) 1320 { 1321 if (!debugfs_initialized()) 1322 return; 1323 1324 hzip_debugfs_root = debugfs_create_dir("hisi_zip", NULL); 1325 } 1326 1327 static void hisi_zip_unregister_debugfs(void) 1328 { 1329 debugfs_remove_recursive(hzip_debugfs_root); 1330 } 1331 1332 static int __init hisi_zip_init(void) 1333 { 1334 int ret; 1335 1336 hisi_qm_init_list(&zip_devices); 1337 hisi_zip_register_debugfs(); 1338 1339 ret = pci_register_driver(&hisi_zip_pci_driver); 1340 if (ret < 0) { 1341 hisi_zip_unregister_debugfs(); 1342 pr_err("Failed to register pci driver.\n"); 1343 } 1344 1345 return ret; 1346 } 1347 1348 static void __exit hisi_zip_exit(void) 1349 { 1350 pci_unregister_driver(&hisi_zip_pci_driver); 1351 hisi_zip_unregister_debugfs(); 1352 } 1353 1354 module_init(hisi_zip_init); 1355 module_exit(hisi_zip_exit); 1356 1357 MODULE_LICENSE("GPL v2"); 1358 MODULE_AUTHOR("Zhou Wang <wangzhou1@hisilicon.com>"); 1359 MODULE_DESCRIPTION("Driver for HiSilicon ZIP accelerator"); 1360