1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Samsung's ExynosAuto v9 SoC device tree source 4 * 5 * Copyright (c) 2021 Samsung Electronics Co., Ltd. 6 * 7 */ 8 9#include <dt-bindings/clock/samsung,exynosautov9.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/soc/samsung,boot-mode.h> 12#include <dt-bindings/soc/samsung,exynos-usi.h> 13 14/ { 15 compatible = "samsung,exynosautov9"; 16 #address-cells = <2>; 17 #size-cells = <1>; 18 19 interrupt-parent = <&gic>; 20 21 aliases { 22 pinctrl0 = &pinctrl_alive; 23 pinctrl1 = &pinctrl_aud; 24 pinctrl2 = &pinctrl_fsys0; 25 pinctrl3 = &pinctrl_fsys1; 26 pinctrl4 = &pinctrl_fsys2; 27 pinctrl5 = &pinctrl_peric0; 28 pinctrl6 = &pinctrl_peric1; 29 }; 30 31 arm-pmu { 32 compatible = "arm,cortex-a76-pmu"; 33 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 35 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 36 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 41 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, 42 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 43 }; 44 45 cpus { 46 #address-cells = <1>; 47 #size-cells = <0>; 48 49 cpu-map { 50 cluster0 { 51 core0 { 52 cpu = <&cpu0>; 53 }; 54 core1 { 55 cpu = <&cpu1>; 56 }; 57 core2 { 58 cpu = <&cpu2>; 59 }; 60 core3 { 61 cpu = <&cpu3>; 62 }; 63 }; 64 65 cluster1 { 66 core0 { 67 cpu = <&cpu4>; 68 }; 69 core1 { 70 cpu = <&cpu5>; 71 }; 72 core2 { 73 cpu = <&cpu6>; 74 }; 75 core3 { 76 cpu = <&cpu7>; 77 }; 78 }; 79 }; 80 81 cpu0: cpu@0 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a76"; 84 reg = <0x0>; 85 enable-method = "psci"; 86 }; 87 88 cpu1: cpu@100 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a76"; 91 reg = <0x100>; 92 enable-method = "psci"; 93 }; 94 95 cpu2: cpu@200 { 96 device_type = "cpu"; 97 compatible = "arm,cortex-a76"; 98 reg = <0x200>; 99 enable-method = "psci"; 100 }; 101 102 cpu3: cpu@300 { 103 device_type = "cpu"; 104 compatible = "arm,cortex-a76"; 105 reg = <0x300>; 106 enable-method = "psci"; 107 }; 108 109 cpu4: cpu@10000 { 110 device_type = "cpu"; 111 compatible = "arm,cortex-a76"; 112 reg = <0x10000>; 113 enable-method = "psci"; 114 }; 115 116 cpu5: cpu@10100 { 117 device_type = "cpu"; 118 compatible = "arm,cortex-a76"; 119 reg = <0x10100>; 120 enable-method = "psci"; 121 }; 122 123 cpu6: cpu@10200 { 124 device_type = "cpu"; 125 compatible = "arm,cortex-a76"; 126 reg = <0x10200>; 127 enable-method = "psci"; 128 }; 129 130 cpu7: cpu@10300 { 131 device_type = "cpu"; 132 compatible = "arm,cortex-a76"; 133 reg = <0x10300>; 134 enable-method = "psci"; 135 }; 136 }; 137 138 psci { 139 compatible = "arm,psci-1.0"; 140 method = "smc"; 141 cpu_suspend = <0xc4000001>; 142 cpu_off = <0x84000002>; 143 cpu_on = <0xc4000003>; 144 }; 145 146 timer { 147 compatible = "arm,armv8-timer"; 148 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 149 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 150 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 151 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 152 }; 153 154 fixed-rate-clocks { 155 xtcxo: clock { 156 compatible = "fixed-clock"; 157 #clock-cells = <0>; 158 clock-output-names = "oscclk"; 159 }; 160 }; 161 162 soc: soc@0 { 163 compatible = "simple-bus"; 164 #address-cells = <1>; 165 #size-cells = <1>; 166 ranges = <0x0 0x0 0x0 0x20000000>; 167 168 chipid@10000000 { 169 compatible = "samsung,exynos850-chipid"; 170 reg = <0x10000000 0x24>; 171 }; 172 173 cmu_peris: clock-controller@10020000 { 174 compatible = "samsung,exynosautov9-cmu-peris"; 175 reg = <0x10020000 0x8000>; 176 #clock-cells = <1>; 177 178 clocks = <&xtcxo>, 179 <&cmu_top DOUT_CLKCMU_PERIS_BUS>; 180 clock-names = "oscclk", 181 "dout_clkcmu_peris_bus"; 182 }; 183 184 cmu_peric0: clock-controller@10200000 { 185 compatible = "samsung,exynosautov9-cmu-peric0"; 186 reg = <0x10200000 0x8000>; 187 #clock-cells = <1>; 188 189 clocks = <&xtcxo>, 190 <&cmu_top DOUT_CLKCMU_PERIC0_BUS>, 191 <&cmu_top DOUT_CLKCMU_PERIC0_IP>; 192 clock-names = "oscclk", 193 "dout_clkcmu_peric0_bus", 194 "dout_clkcmu_peric0_ip"; 195 }; 196 197 cmu_peric1: clock-controller@10800000 { 198 compatible = "samsung,exynosautov9-cmu-peric1"; 199 reg = <0x10800000 0x8000>; 200 #clock-cells = <1>; 201 202 clocks = <&xtcxo>, 203 <&cmu_top DOUT_CLKCMU_PERIC1_BUS>, 204 <&cmu_top DOUT_CLKCMU_PERIC1_IP>; 205 clock-names = "oscclk", 206 "dout_clkcmu_peric1_bus", 207 "dout_clkcmu_peric1_ip"; 208 }; 209 210 cmu_fsys1: clock-controller@17040000 { 211 compatible = "samsung,exynosautov9-cmu-fsys1"; 212 reg = <0x17040000 0x8000>; 213 #clock-cells = <1>; 214 215 clocks = <&xtcxo>, 216 <&cmu_top DOUT_CLKCMU_FSYS1_BUS>, 217 <&cmu_top GOUT_CLKCMU_FSYS1_MMC_CARD>, 218 <&cmu_top DOUT_CLKCMU_FSYS1_USBDRD>; 219 clock-names = "oscclk", 220 "dout_clkcmu_fsys1_bus", 221 "gout_clkcmu_fsys1_mmc_card", 222 "dout_clkcmu_fsys1_usbdrd"; 223 }; 224 225 cmu_fsys0: clock-controller@17700000 { 226 compatible = "samsung,exynosautov9-cmu-fsys0"; 227 reg = <0x17700000 0x8000>; 228 #clock-cells = <1>; 229 230 clocks = <&xtcxo>, 231 <&cmu_top DOUT_CLKCMU_FSYS0_BUS>, 232 <&cmu_top DOUT_CLKCMU_FSYS0_PCIE>; 233 clock-names = "oscclk", 234 "dout_clkcmu_fsys0_bus", 235 "dout_clkcmu_fsys0_pcie"; 236 }; 237 238 cmu_fsys2: clock-controller@17c00000 { 239 compatible = "samsung,exynosautov9-cmu-fsys2"; 240 reg = <0x17c00000 0x8000>; 241 #clock-cells = <1>; 242 243 clocks = <&xtcxo>, 244 <&cmu_top DOUT_CLKCMU_FSYS2_BUS>, 245 <&cmu_top DOUT_CLKCMU_FSYS2_UFS_EMBD>, 246 <&cmu_top DOUT_CLKCMU_FSYS2_ETHERNET>; 247 clock-names = "oscclk", 248 "dout_clkcmu_fsys2_bus", 249 "dout_fsys2_clkcmu_ufs_embd", 250 "dout_fsys2_clkcmu_ethernet"; 251 }; 252 253 cmu_core: clock-controller@1b030000 { 254 compatible = "samsung,exynosautov9-cmu-core"; 255 reg = <0x1b030000 0x8000>; 256 #clock-cells = <1>; 257 258 clocks = <&xtcxo>, 259 <&cmu_top DOUT_CLKCMU_CORE_BUS>; 260 clock-names = "oscclk", 261 "dout_clkcmu_core_bus"; 262 }; 263 264 cmu_busmc: clock-controller@1b200000 { 265 compatible = "samsung,exynosautov9-cmu-busmc"; 266 reg = <0x1b200000 0x8000>; 267 #clock-cells = <1>; 268 269 clocks = <&xtcxo>, 270 <&cmu_top DOUT_CLKCMU_BUSMC_BUS>; 271 clock-names = "oscclk", 272 "dout_clkcmu_busmc_bus"; 273 }; 274 275 cmu_top: clock-controller@1b240000 { 276 compatible = "samsung,exynosautov9-cmu-top"; 277 reg = <0x1b240000 0x8000>; 278 #clock-cells = <1>; 279 280 clocks = <&xtcxo>; 281 clock-names = "oscclk"; 282 }; 283 284 gic: interrupt-controller@10101000 { 285 compatible = "arm,gic-400"; 286 #interrupt-cells = <3>; 287 #address-cells = <0>; 288 interrupt-controller; 289 reg = <0x10101000 0x1000>, 290 <0x10102000 0x2000>, 291 <0x10104000 0x2000>, 292 <0x10106000 0x2000>; 293 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 294 IRQ_TYPE_LEVEL_HIGH)>; 295 }; 296 297 pdma0: dma-controller@1b2e0000 { 298 compatible = "arm,pl330", "arm,primecell"; 299 reg = <0x1b2e0000 0x1000>; 300 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 301 clocks = <&cmu_busmc CLK_GOUT_BUSMC_PDMA0_PCLK>; 302 clock-names = "apb_pclk"; 303 arm,pl330-broken-no-flushp; 304 #dma-cells = <1>; 305 }; 306 307 pinctrl_alive: pinctrl@10450000 { 308 compatible = "samsung,exynosautov9-pinctrl"; 309 reg = <0x10450000 0x1000>; 310 311 wakeup-interrupt-controller { 312 compatible = "samsung,exynosautov9-wakeup-eint"; 313 }; 314 }; 315 316 pinctrl_aud: pinctrl@19c60000{ 317 compatible = "samsung,exynosautov9-pinctrl"; 318 reg = <0x19c60000 0x1000>; 319 }; 320 321 pinctrl_fsys0: pinctrl@17740000 { 322 compatible = "samsung,exynosautov9-pinctrl"; 323 reg = <0x17740000 0x1000>; 324 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 325 }; 326 327 pinctrl_fsys1: pinctrl@17060000 { 328 compatible = "samsung,exynosautov9-pinctrl"; 329 reg = <0x17060000 0x1000>; 330 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 331 }; 332 333 pinctrl_fsys2: pinctrl@17c30000 { 334 compatible = "samsung,exynosautov9-pinctrl"; 335 reg = <0x17c30000 0x1000>; 336 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>; 337 }; 338 339 pinctrl_peric0: pinctrl@10230000 { 340 compatible = "samsung,exynosautov9-pinctrl"; 341 reg = <0x10230000 0x1000>; 342 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>; 343 }; 344 345 pinctrl_peric1: pinctrl@10830000 { 346 compatible = "samsung,exynosautov9-pinctrl"; 347 reg = <0x10830000 0x1000>; 348 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 349 }; 350 351 pmu_system_controller: system-controller@10460000 { 352 compatible = "samsung,exynos7-pmu", "syscon"; 353 reg = <0x10460000 0x10000>; 354 355 reboot: syscon-reboot { 356 compatible = "syscon-reboot"; 357 regmap = <&pmu_system_controller>; 358 offset = <0x3a00>; /* SYSTEM_CONFIGURATION */ 359 value = <0x2>; 360 mask = <0x2>; 361 }; 362 363 reboot-mode { 364 compatible = "syscon-reboot-mode"; 365 offset = <0x810>; /* SYSIP_DAT0 */ 366 mode-bootloader = <EXYNOSAUTOV9_BOOT_BOOTLOADER>; 367 mode-fastboot = <EXYNOSAUTOV9_BOOT_FASTBOOT>; 368 mode-recovery = <EXYNOSAUTOV9_BOOT_RECOVERY>; 369 }; 370 }; 371 372 syscon_fsys2: syscon@17c20000 { 373 compatible = "samsung,exynosautov9-sysreg", "syscon"; 374 reg = <0x17c20000 0x1000>; 375 }; 376 377 syscon_peric0: syscon@10220000 { 378 compatible = "samsung,exynosautov9-sysreg", "syscon"; 379 reg = <0x10220000 0x2000>; 380 }; 381 382 syscon_peric1: syscon@10820000 { 383 compatible = "samsung,exynosautov9-sysreg", "syscon"; 384 reg = <0x10820000 0x2000>; 385 }; 386 387 usi_0: usi@103000c0 { 388 compatible = "samsung,exynosautov9-usi", 389 "samsung,exynos850-usi"; 390 reg = <0x103000c0 0x20>; 391 samsung,sysreg = <&syscon_peric0 0x1000>; 392 samsung,mode = <USI_V2_UART>; 393 #address-cells = <1>; 394 #size-cells = <1>; 395 ranges; 396 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>, 397 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>; 398 clock-names = "pclk", "ipclk"; 399 status = "disabled"; 400 401 serial_0: serial@10300000 { 402 compatible = "samsung,exynosautov9-uart", 403 "samsung,exynos850-uart"; 404 reg = <0x10300000 0xc0>; 405 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; 406 pinctrl-names = "default"; 407 pinctrl-0 = <&uart0_bus>; 408 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>, 409 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>; 410 clock-names = "uart", "clk_uart_baud0"; 411 samsung,uart-fifosize = <256>; 412 status = "disabled"; 413 }; 414 415 spi_0: spi@10300000 { 416 compatible = "samsung,exynosautov9-spi"; 417 reg = <0x10300000 0x30>; 418 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; 419 pinctrl-names = "default"; 420 pinctrl-0 = <&spi0_bus &spi0_cs_func>; 421 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>, 422 <&cmu_peric0 CLK_DOUT_PERIC0_USI00_USI>, 423 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>; 424 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 425 samsung,spi-src-clk = <0>; 426 dmas = <&pdma0 1>, <&pdma0 0>; 427 dma-names = "tx", "rx"; 428 num-cs = <1>; 429 #address-cells = <1>; 430 #size-cells = <0>; 431 status = "disabled"; 432 }; 433 434 hsi2c_0: i2c@10300000 { 435 compatible = "samsung,exynosautov9-hsi2c"; 436 reg = <0x10300000 0xc0>; 437 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; 438 pinctrl-names = "default"; 439 pinctrl-0 = <&hsi2c0_bus>; 440 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>, 441 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>; 442 clock-names = "hsi2c", "hsi2c_pclk"; 443 #address-cells = <1>; 444 #size-cells = <0>; 445 status = "disabled"; 446 }; 447 }; 448 449 usi_i2c_0: usi@103100c0 { 450 compatible = "samsung,exynosautov9-usi", 451 "samsung,exynos850-usi"; 452 reg = <0x103100c0 0x20>; 453 samsung,sysreg = <&syscon_peric0 0x1004>; 454 samsung,mode = <USI_V2_I2C>; 455 #address-cells = <1>; 456 #size-cells = <1>; 457 ranges; 458 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_1>, 459 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_1>; 460 clock-names = "pclk", "ipclk"; 461 status = "disabled"; 462 463 hsi2c_1: i2c@10310000 { 464 compatible = "samsung,exynosautov9-hsi2c"; 465 reg = <0x10310000 0xc0>; 466 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 467 pinctrl-names = "default"; 468 pinctrl-0 = <&hsi2c1_bus>; 469 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_1>, 470 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_1>; 471 clock-names = "hsi2c", "hsi2c_pclk"; 472 #address-cells = <1>; 473 #size-cells = <0>; 474 status = "disabled"; 475 }; 476 }; 477 478 usi_1: usi@103200c0 { 479 compatible = "samsung,exynosautov9-usi", 480 "samsung,exynos850-usi"; 481 reg = <0x103200c0 0x20>; 482 samsung,sysreg = <&syscon_peric0 0x1008>; 483 samsung,mode = <USI_V2_UART>; 484 #address-cells = <1>; 485 #size-cells = <1>; 486 ranges; 487 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_2>, 488 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_2>; 489 clock-names = "pclk", "ipclk"; 490 status = "disabled"; 491 492 serial_1: serial@10320000 { 493 compatible = "samsung,exynosautov9-uart", 494 "samsung,exynos850-uart"; 495 reg = <0x10320000 0xc0>; 496 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; 497 pinctrl-names = "default"; 498 pinctrl-0 = <&uart1_bus>; 499 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_2>, 500 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_2>; 501 clock-names = "uart", "clk_uart_baud0"; 502 samsung,uart-fifosize = <256>; 503 status = "disabled"; 504 }; 505 506 spi_1: spi@10320000 { 507 compatible = "samsung,exynosautov9-spi"; 508 reg = <0x10320000 0x30>; 509 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; 510 pinctrl-names = "default"; 511 pinctrl-0 = <&spi1_bus &spi1_cs_func>; 512 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_2>, 513 <&cmu_peric0 CLK_DOUT_PERIC0_USI01_USI>, 514 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_2>; 515 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 516 samsung,spi-src-clk = <0>; 517 dmas = <&pdma0 3>, <&pdma0 2>; 518 dma-names = "tx", "rx"; 519 num-cs = <1>; 520 #address-cells = <1>; 521 #size-cells = <0>; 522 status = "disabled"; 523 }; 524 525 hsi2c_2: i2c@10320000 { 526 compatible = "samsung,exynosautov9-hsi2c"; 527 reg = <0x10320000 0xc0>; 528 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; 529 pinctrl-names = "default"; 530 pinctrl-0 = <&hsi2c2_bus>; 531 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_2>, 532 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_2>; 533 clock-names = "hsi2c", "hsi2c_pclk"; 534 #address-cells = <1>; 535 #size-cells = <0>; 536 status = "disabled"; 537 }; 538 }; 539 540 usi_i2c_1: usi@103300c0 { 541 compatible = "samsung,exynosautov9-usi", 542 "samsung,exynos850-usi"; 543 reg = <0x103300c0 0x20>; 544 samsung,sysreg = <&syscon_peric0 0x100c>; 545 samsung,mode = <USI_V2_I2C>; 546 #address-cells = <1>; 547 #size-cells = <1>; 548 ranges; 549 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_3>, 550 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_3>; 551 clock-names = "pclk", "ipclk"; 552 status = "disabled"; 553 554 hsi2c_3: i2c@10330000 { 555 compatible = "samsung,exynosautov9-hsi2c"; 556 reg = <0x10330000 0xc0>; 557 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; 558 pinctrl-names = "default"; 559 pinctrl-0 = <&hsi2c3_bus>; 560 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_3>, 561 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_3>; 562 clock-names = "hsi2c", "hsi2c_pclk"; 563 #address-cells = <1>; 564 #size-cells = <0>; 565 status = "disabled"; 566 }; 567 }; 568 569 usi_2: usi@103400c0 { 570 compatible = "samsung,exynosautov9-usi", 571 "samsung,exynos850-usi"; 572 reg = <0x103400c0 0x20>; 573 samsung,sysreg = <&syscon_peric0 0x1010>; 574 samsung,mode = <USI_V2_UART>; 575 #address-cells = <1>; 576 #size-cells = <1>; 577 ranges; 578 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_4>, 579 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_4>; 580 clock-names = "pclk", "ipclk"; 581 status = "disabled"; 582 583 serial_2: serial@10340000 { 584 compatible = "samsung,exynosautov9-uart", 585 "samsung,exynos850-uart"; 586 reg = <0x10340000 0xc0>; 587 interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; 588 pinctrl-names = "default"; 589 pinctrl-0 = <&uart2_bus>; 590 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_4>, 591 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_4>; 592 clock-names = "uart", "clk_uart_baud0"; 593 samsung,uart-fifosize = <64>; 594 status = "disabled"; 595 }; 596 597 spi_2: spi@10340000 { 598 compatible = "samsung,exynosautov9-spi"; 599 reg = <0x10340000 0x30>; 600 interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; 601 pinctrl-names = "default"; 602 pinctrl-0 = <&spi2_bus &spi2_cs_func>; 603 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_4>, 604 <&cmu_peric0 CLK_DOUT_PERIC0_USI02_USI>, 605 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_4>; 606 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 607 samsung,spi-src-clk = <0>; 608 dmas = <&pdma0 5>, <&pdma0 4>; 609 dma-names = "tx", "rx"; 610 num-cs = <1>; 611 #address-cells = <1>; 612 #size-cells = <0>; 613 status = "disabled"; 614 }; 615 616 hsi2c_4: i2c@10340000 { 617 compatible = "samsung,exynosautov9-hsi2c"; 618 reg = <0x10340000 0xc0>; 619 interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; 620 pinctrl-names = "default"; 621 pinctrl-0 = <&hsi2c4_bus>; 622 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_4>, 623 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_4>; 624 clock-names = "hsi2c", "hsi2c_pclk"; 625 #address-cells = <1>; 626 #size-cells = <0>; 627 status = "disabled"; 628 }; 629 }; 630 631 usi_i2c_2: usi@103500c0 { 632 compatible = "samsung,exynosautov9-usi", 633 "samsung,exynos850-usi"; 634 reg = <0x103500c0 0x20>; 635 samsung,sysreg = <&syscon_peric0 0x1014>; 636 samsung,mode = <USI_V2_I2C>; 637 #address-cells = <1>; 638 #size-cells = <1>; 639 ranges; 640 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_5>, 641 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_5>; 642 clock-names = "pclk", "ipclk"; 643 status = "disabled"; 644 645 hsi2c_5: i2c@10350000 { 646 compatible = "samsung,exynosautov9-hsi2c"; 647 reg = <0x10350000 0xc0>; 648 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>; 649 pinctrl-names = "default"; 650 pinctrl-0 = <&hsi2c5_bus>; 651 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_5>, 652 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_5>; 653 clock-names = "hsi2c", "hsi2c_pclk"; 654 #address-cells = <1>; 655 #size-cells = <0>; 656 status = "disabled"; 657 }; 658 }; 659 660 usi_3: usi@103600c0 { 661 compatible = "samsung,exynosautov9-usi", 662 "samsung,exynos850-usi"; 663 reg = <0x103600c0 0x20>; 664 samsung,sysreg = <&syscon_peric0 0x1018>; 665 samsung,mode = <USI_V2_UART>; 666 #address-cells = <1>; 667 #size-cells = <1>; 668 ranges; 669 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_6>, 670 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_6>; 671 clock-names = "pclk", "ipclk"; 672 status = "disabled"; 673 674 serial_3: serial@10360000 { 675 compatible = "samsung,exynosautov9-uart", 676 "samsung,exynos850-uart"; 677 reg = <0x10360000 0xc0>; 678 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>; 679 pinctrl-names = "default"; 680 pinctrl-0 = <&uart3_bus>; 681 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_6>, 682 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_6>; 683 clock-names = "uart", "clk_uart_baud0"; 684 samsung,uart-fifosize = <64>; 685 status = "disabled"; 686 }; 687 688 spi_3: spi@10360000 { 689 compatible = "samsung,exynosautov9-spi"; 690 reg = <0x10360000 0x30>; 691 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>; 692 pinctrl-names = "default"; 693 pinctrl-0 = <&spi3_bus &spi3_cs_func>; 694 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_6>, 695 <&cmu_peric0 CLK_DOUT_PERIC0_USI03_USI>, 696 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_6>; 697 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 698 samsung,spi-src-clk = <0>; 699 dmas = <&pdma0 7>, <&pdma0 6>; 700 dma-names = "tx", "rx"; 701 num-cs = <1>; 702 #address-cells = <1>; 703 #size-cells = <0>; 704 status = "disabled"; 705 }; 706 707 hsi2c_6: i2c@10360000 { 708 compatible = "samsung,exynosautov9-hsi2c"; 709 reg = <0x10360000 0xc0>; 710 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>; 711 pinctrl-names = "default"; 712 pinctrl-0 = <&hsi2c6_bus>; 713 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_6>, 714 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_6>; 715 clock-names = "hsi2c", "hsi2c_pclk"; 716 #address-cells = <1>; 717 #size-cells = <0>; 718 status = "disabled"; 719 }; 720 }; 721 722 usi_i2c_3: usi@103700c0 { 723 compatible = "samsung,exynosautov9-usi", 724 "samsung,exynos850-usi"; 725 reg = <0x103700c0 0x20>; 726 samsung,sysreg = <&syscon_peric0 0x101c>; 727 samsung,mode = <USI_V2_I2C>; 728 #address-cells = <1>; 729 #size-cells = <1>; 730 ranges; 731 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_7>, 732 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_7>; 733 clock-names = "pclk", "ipclk"; 734 status = "disabled"; 735 736 hsi2c_7: i2c@10370000 { 737 compatible = "samsung,exynosautov9-hsi2c"; 738 reg = <0x10370000 0xc0>; 739 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>; 740 pinctrl-names = "default"; 741 pinctrl-0 = <&hsi2c7_bus>; 742 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_7>, 743 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_7>; 744 clock-names = "hsi2c", "hsi2c_pclk"; 745 #address-cells = <1>; 746 #size-cells = <0>; 747 status = "disabled"; 748 }; 749 }; 750 751 usi_4: usi@103800c0 { 752 compatible = "samsung,exynosautov9-usi", 753 "samsung,exynos850-usi"; 754 reg = <0x103800c0 0x20>; 755 samsung,sysreg = <&syscon_peric0 0x1020>; 756 samsung,mode = <USI_V2_UART>; 757 #address-cells = <1>; 758 #size-cells = <1>; 759 ranges; 760 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_8>, 761 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_8>; 762 clock-names = "pclk", "ipclk"; 763 status = "disabled"; 764 765 serial_4: serial@10380000 { 766 compatible = "samsung,exynosautov9-uart", 767 "samsung,exynos850-uart"; 768 reg = <0x10380000 0xc0>; 769 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 770 pinctrl-names = "default"; 771 pinctrl-0 = <&uart4_bus>; 772 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_8>, 773 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_8>; 774 clock-names = "uart", "clk_uart_baud0"; 775 samsung,uart-fifosize = <64>; 776 status = "disabled"; 777 }; 778 779 spi_4: spi@10380000 { 780 compatible = "samsung,exynosautov9-spi"; 781 reg = <0x10380000 0x30>; 782 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 783 pinctrl-names = "default"; 784 pinctrl-0 = <&spi4_bus &spi4_cs_func>; 785 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_8>, 786 <&cmu_peric0 CLK_DOUT_PERIC0_USI04_USI>, 787 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_8>; 788 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 789 samsung,spi-src-clk = <0>; 790 dmas = <&pdma0 9>, <&pdma0 8>; 791 dma-names = "tx", "rx"; 792 num-cs = <1>; 793 #address-cells = <1>; 794 #size-cells = <0>; 795 status = "disabled"; 796 }; 797 798 hsi2c_8: i2c@10380000 { 799 compatible = "samsung,exynosautov9-hsi2c"; 800 reg = <0x10380000 0xc0>; 801 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 802 pinctrl-names = "default"; 803 pinctrl-0 = <&hsi2c8_bus>; 804 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_8>, 805 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_8>; 806 clock-names = "hsi2c", "hsi2c_pclk"; 807 #address-cells = <1>; 808 #size-cells = <0>; 809 status = "disabled"; 810 }; 811 }; 812 813 usi_i2c_4: usi@103900c0 { 814 compatible = "samsung,exynosautov9-usi", 815 "samsung,exynos850-usi"; 816 reg = <0x103900c0 0x20>; 817 samsung,sysreg = <&syscon_peric0 0x1024>; 818 samsung,mode = <USI_V2_I2C>; 819 #address-cells = <1>; 820 #size-cells = <1>; 821 ranges; 822 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_9>, 823 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_9>; 824 clock-names = "pclk", "ipclk"; 825 status = "disabled"; 826 827 hsi2c_9: i2c@10390000 { 828 compatible = "samsung,exynosautov9-hsi2c"; 829 reg = <0x10390000 0xc0>; 830 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 831 pinctrl-names = "default"; 832 pinctrl-0 = <&hsi2c9_bus>; 833 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_9>, 834 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_9>; 835 clock-names = "hsi2c", "hsi2c_pclk"; 836 #address-cells = <1>; 837 #size-cells = <0>; 838 status = "disabled"; 839 }; 840 }; 841 842 usi_5: usi@103a00c0 { 843 compatible = "samsung,exynosautov9-usi", 844 "samsung,exynos850-usi"; 845 reg = <0x103a00c0 0x20>; 846 samsung,sysreg = <&syscon_peric0 0x1028>; 847 samsung,mode = <USI_V2_UART>; 848 #address-cells = <1>; 849 #size-cells = <1>; 850 ranges; 851 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_10>, 852 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_10>; 853 clock-names = "pclk", "ipclk"; 854 status = "disabled"; 855 856 serial_5: serial@103a0000 { 857 compatible = "samsung,exynosautov9-uart", 858 "samsung,exynos850-uart"; 859 reg = <0x103a0000 0xc0>; 860 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 861 pinctrl-names = "default"; 862 pinctrl-0 = <&uart5_bus>; 863 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_10>, 864 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_10>; 865 clock-names = "uart", "clk_uart_baud0"; 866 samsung,uart-fifosize = <64>; 867 status = "disabled"; 868 }; 869 870 spi_5: spi@103a0000 { 871 compatible = "samsung,exynosautov9-spi"; 872 reg = <0x103a0000 0x30>; 873 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 874 pinctrl-names = "default"; 875 pinctrl-0 = <&spi5_bus &spi5_cs_func>; 876 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_10>, 877 <&cmu_peric0 CLK_DOUT_PERIC0_USI05_USI>, 878 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_10>; 879 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 880 samsung,spi-src-clk = <0>; 881 dmas = <&pdma0 11>, <&pdma0 10>; 882 dma-names = "tx", "rx"; 883 num-cs = <1>; 884 #address-cells = <1>; 885 #size-cells = <0>; 886 status = "disabled"; 887 }; 888 889 hsi2c_10: i2c@103a0000 { 890 compatible = "samsung,exynosautov9-hsi2c"; 891 reg = <0x103a0000 0xc0>; 892 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 893 pinctrl-names = "default"; 894 pinctrl-0 = <&hsi2c10_bus>; 895 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_10>, 896 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_10>; 897 clock-names = "hsi2c", "hsi2c_pclk"; 898 #address-cells = <1>; 899 #size-cells = <0>; 900 status = "disabled"; 901 }; 902 }; 903 904 usi_i2c_5: usi@103b00c0 { 905 compatible = "samsung,exynosautov9-usi", 906 "samsung,exynos850-usi"; 907 reg = <0x103b00c0 0x20>; 908 samsung,sysreg = <&syscon_peric0 0x102c>; 909 samsung,mode = <USI_V2_I2C>; 910 #address-cells = <1>; 911 #size-cells = <1>; 912 ranges; 913 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_11>, 914 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_11>; 915 clock-names = "pclk", "ipclk"; 916 status = "disabled"; 917 918 hsi2c_11: i2c@103b0000 { 919 compatible = "samsung,exynosautov9-hsi2c"; 920 reg = <0x103b0000 0xc0>; 921 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 922 pinctrl-names = "default"; 923 pinctrl-0 = <&hsi2c11_bus>; 924 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_11>, 925 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_11>; 926 clock-names = "hsi2c", "hsi2c_pclk"; 927 #address-cells = <1>; 928 #size-cells = <0>; 929 status = "disabled"; 930 }; 931 }; 932 933 usi_6: usi@109000c0 { 934 compatible = "samsung,exynosautov9-usi", 935 "samsung,exynos850-usi"; 936 reg = <0x109000c0 0x20>; 937 samsung,sysreg = <&syscon_peric1 0x1000>; 938 samsung,mode = <USI_V2_UART>; 939 #address-cells = <1>; 940 #size-cells = <1>; 941 ranges; 942 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_0>, 943 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_0>; 944 clock-names = "pclk", "ipclk"; 945 status = "disabled"; 946 947 serial_6: serial@10900000 { 948 compatible = "samsung,exynosautov9-uart", 949 "samsung,exynos850-uart"; 950 reg = <0x10900000 0xc0>; 951 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 952 pinctrl-names = "default"; 953 pinctrl-0 = <&uart6_bus>; 954 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_0>, 955 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_0>; 956 clock-names = "uart", "clk_uart_baud0"; 957 samsung,uart-fifosize = <256>; 958 status = "disabled"; 959 }; 960 961 spi_6: spi@10900000 { 962 compatible = "samsung,exynosautov9-spi"; 963 reg = <0x10900000 0x30>; 964 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 965 pinctrl-names = "default"; 966 pinctrl-0 = <&spi6_bus &spi6_cs_func>; 967 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_0>, 968 <&cmu_peric1 CLK_DOUT_PERIC1_USI06_USI>, 969 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_0>; 970 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 971 samsung,spi-src-clk = <0>; 972 dmas = <&pdma0 13>, <&pdma0 12>; 973 dma-names = "tx", "rx"; 974 num-cs = <1>; 975 #address-cells = <1>; 976 #size-cells = <0>; 977 status = "disabled"; 978 }; 979 980 hsi2c_12: i2c@10900000 { 981 compatible = "samsung,exynosautov9-hsi2c"; 982 reg = <0x10900000 0xc0>; 983 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 984 pinctrl-names = "default"; 985 pinctrl-0 = <&hsi2c12_bus>; 986 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_0>, 987 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_0>; 988 clock-names = "hsi2c", "hsi2c_pclk"; 989 #address-cells = <1>; 990 #size-cells = <0>; 991 status = "disabled"; 992 }; 993 }; 994 995 usi_i2c_6: usi@109100c0 { 996 compatible = "samsung,exynosautov9-usi", 997 "samsung,exynos850-usi"; 998 reg = <0x109100c0 0x20>; 999 samsung,sysreg = <&syscon_peric1 0x1004>; 1000 samsung,mode = <USI_V2_I2C>; 1001 #address-cells = <1>; 1002 #size-cells = <1>; 1003 ranges; 1004 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_1>, 1005 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_1>; 1006 clock-names = "pclk", "ipclk"; 1007 status = "disabled"; 1008 1009 hsi2c_13: i2c@10910000 { 1010 compatible = "samsung,exynosautov9-hsi2c"; 1011 reg = <0x10910000 0xc0>; 1012 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1013 pinctrl-names = "default"; 1014 pinctrl-0 = <&hsi2c13_bus>; 1015 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_1>, 1016 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_1>; 1017 clock-names = "hsi2c", "hsi2c_pclk"; 1018 #address-cells = <1>; 1019 #size-cells = <0>; 1020 status = "disabled"; 1021 }; 1022 }; 1023 1024 usi_7: usi@109200c0 { 1025 compatible = "samsung,exynosautov9-usi", 1026 "samsung,exynos850-usi"; 1027 reg = <0x109200c0 0x20>; 1028 samsung,sysreg = <&syscon_peric1 0x1008>; 1029 samsung,mode = <USI_V2_UART>; 1030 #address-cells = <1>; 1031 #size-cells = <1>; 1032 ranges; 1033 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_2>, 1034 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_2>; 1035 clock-names = "pclk", "ipclk"; 1036 status = "disabled"; 1037 1038 serial_7: serial@10920000 { 1039 compatible = "samsung,exynosautov9-uart", 1040 "samsung,exynos850-uart"; 1041 reg = <0x10920000 0xc0>; 1042 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1043 pinctrl-names = "default"; 1044 pinctrl-0 = <&uart7_bus>; 1045 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_2>, 1046 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_2>; 1047 clock-names = "uart", "clk_uart_baud0"; 1048 samsung,uart-fifosize = <64>; 1049 status = "disabled"; 1050 }; 1051 1052 spi_7: spi@10920000 { 1053 compatible = "samsung,exynosautov9-spi"; 1054 reg = <0x10920000 0x30>; 1055 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1056 pinctrl-names = "default"; 1057 pinctrl-0 = <&spi7_bus &spi7_cs_func>; 1058 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_2>, 1059 <&cmu_peric1 CLK_DOUT_PERIC1_USI07_USI>, 1060 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_2>; 1061 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 1062 samsung,spi-src-clk = <0>; 1063 dmas = <&pdma0 15>, <&pdma0 14>; 1064 dma-names = "tx", "rx"; 1065 num-cs = <1>; 1066 #address-cells = <1>; 1067 #size-cells = <0>; 1068 status = "disabled"; 1069 }; 1070 1071 hsi2c_14: i2c@10920000 { 1072 compatible = "samsung,exynosautov9-hsi2c"; 1073 reg = <0x10920000 0xc0>; 1074 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1075 pinctrl-names = "default"; 1076 pinctrl-0 = <&hsi2c14_bus>; 1077 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_2>, 1078 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_2>; 1079 clock-names = "hsi2c", "hsi2c_pclk"; 1080 #address-cells = <1>; 1081 #size-cells = <0>; 1082 status = "disabled"; 1083 }; 1084 }; 1085 1086 usi_i2c_7: usi@109300c0 { 1087 compatible = "samsung,exynosautov9-usi", 1088 "samsung,exynos850-usi"; 1089 reg = <0x109300c0 0x20>; 1090 samsung,sysreg = <&syscon_peric1 0x100c>; 1091 samsung,mode = <USI_V2_I2C>; 1092 #address-cells = <1>; 1093 #size-cells = <1>; 1094 ranges; 1095 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_3>, 1096 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_3>; 1097 clock-names = "pclk", "ipclk"; 1098 status = "disabled"; 1099 1100 hsi2c_15: i2c@10930000 { 1101 compatible = "samsung,exynosautov9-hsi2c"; 1102 reg = <0x10930000 0xc0>; 1103 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1104 pinctrl-names = "default"; 1105 pinctrl-0 = <&hsi2c15_bus>; 1106 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_3>, 1107 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_3>; 1108 clock-names = "hsi2c", "hsi2c_pclk"; 1109 #address-cells = <1>; 1110 #size-cells = <0>; 1111 status = "disabled"; 1112 }; 1113 }; 1114 1115 usi_8: usi@109400c0 { 1116 compatible = "samsung,exynosautov9-usi", 1117 "samsung,exynos850-usi"; 1118 reg = <0x109400c0 0x20>; 1119 samsung,sysreg = <&syscon_peric1 0x1010>; 1120 samsung,mode = <USI_V2_UART>; 1121 #address-cells = <1>; 1122 #size-cells = <1>; 1123 ranges; 1124 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_4>, 1125 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_4>; 1126 clock-names = "pclk", "ipclk"; 1127 status = "disabled"; 1128 1129 serial_8: serial@10940000 { 1130 compatible = "samsung,exynosautov9-uart", 1131 "samsung,exynos850-uart"; 1132 reg = <0x10940000 0xc0>; 1133 interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>; 1134 pinctrl-names = "default"; 1135 pinctrl-0 = <&uart8_bus>; 1136 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_4>, 1137 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_4>; 1138 clock-names = "uart", "clk_uart_baud0"; 1139 samsung,uart-fifosize = <64>; 1140 status = "disabled"; 1141 }; 1142 1143 spi_8: spi@10940000 { 1144 compatible = "samsung,exynosautov9-spi"; 1145 reg = <0x10940000 0x30>; 1146 interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>; 1147 pinctrl-names = "default"; 1148 pinctrl-0 = <&spi8_bus &spi8_cs_func>; 1149 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_4>, 1150 <&cmu_peric1 CLK_DOUT_PERIC1_USI08_USI>, 1151 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_4>; 1152 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 1153 samsung,spi-src-clk = <0>; 1154 dmas = <&pdma0 17>, <&pdma0 16>; 1155 dma-names = "tx", "rx"; 1156 num-cs = <1>; 1157 #address-cells = <1>; 1158 #size-cells = <0>; 1159 status = "disabled"; 1160 }; 1161 1162 hsi2c_16: i2c@10940000 { 1163 compatible = "samsung,exynosautov9-hsi2c"; 1164 reg = <0x10940000 0xc0>; 1165 interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>; 1166 pinctrl-names = "default"; 1167 pinctrl-0 = <&hsi2c16_bus>; 1168 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_4>, 1169 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_4>; 1170 clock-names = "hsi2c", "hsi2c_pclk"; 1171 #address-cells = <1>; 1172 #size-cells = <0>; 1173 status = "disabled"; 1174 }; 1175 }; 1176 1177 usi_i2c_8: usi@109500c0 { 1178 compatible = "samsung,exynosautov9-usi", 1179 "samsung,exynos850-usi"; 1180 reg = <0x109500c0 0x20>; 1181 samsung,sysreg = <&syscon_peric1 0x1014>; 1182 samsung,mode = <USI_V2_I2C>; 1183 #address-cells = <1>; 1184 #size-cells = <1>; 1185 ranges; 1186 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_5>, 1187 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_5>; 1188 clock-names = "pclk", "ipclk"; 1189 status = "disabled"; 1190 1191 hsi2c_17: i2c@10950000 { 1192 compatible = "samsung,exynosautov9-hsi2c"; 1193 reg = <0x10950000 0xc0>; 1194 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1195 pinctrl-names = "default"; 1196 pinctrl-0 = <&hsi2c17_bus>; 1197 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_5>, 1198 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_5>; 1199 clock-names = "hsi2c", "hsi2c_pclk"; 1200 #address-cells = <1>; 1201 #size-cells = <0>; 1202 status = "disabled"; 1203 }; 1204 }; 1205 1206 usi_9: usi@109600c0 { 1207 compatible = "samsung,exynosautov9-usi", 1208 "samsung,exynos850-usi"; 1209 reg = <0x109600c0 0x20>; 1210 samsung,sysreg = <&syscon_peric1 0x1018>; 1211 samsung,mode = <USI_V2_UART>; 1212 #address-cells = <1>; 1213 #size-cells = <1>; 1214 ranges; 1215 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_6>, 1216 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_6>; 1217 clock-names = "pclk", "ipclk"; 1218 status = "disabled"; 1219 1220 serial_9: serial@10960000 { 1221 compatible = "samsung,exynosautov9-uart", 1222 "samsung,exynos850-uart"; 1223 reg = <0x10960000 0xc0>; 1224 interrupts = <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>; 1225 pinctrl-names = "default"; 1226 pinctrl-0 = <&uart9_bus>; 1227 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_6>, 1228 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_6>; 1229 clock-names = "uart", "clk_uart_baud0"; 1230 samsung,uart-fifosize = <64>; 1231 status = "disabled"; 1232 }; 1233 1234 spi_9: spi@10960000 { 1235 compatible = "samsung,exynosautov9-spi"; 1236 reg = <0x10960000 0x30>; 1237 interrupts = <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>; 1238 pinctrl-names = "default"; 1239 pinctrl-0 = <&spi9_bus &spi9_cs_func>; 1240 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_6>, 1241 <&cmu_peric1 CLK_DOUT_PERIC1_USI09_USI>, 1242 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_6>; 1243 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 1244 samsung,spi-src-clk = <0>; 1245 dmas = <&pdma0 19>, <&pdma0 18>; 1246 dma-names = "tx", "rx"; 1247 num-cs = <1>; 1248 #address-cells = <1>; 1249 #size-cells = <0>; 1250 status = "disabled"; 1251 }; 1252 1253 hsi2c_18: i2c@10960000 { 1254 compatible = "samsung,exynosautov9-hsi2c"; 1255 reg = <0x10960000 0xc0>; 1256 interrupts = <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>; 1257 pinctrl-names = "default"; 1258 pinctrl-0 = <&hsi2c18_bus>; 1259 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_6>, 1260 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_6>; 1261 clock-names = "hsi2c", "hsi2c_pclk"; 1262 #address-cells = <1>; 1263 #size-cells = <0>; 1264 status = "disabled"; 1265 }; 1266 }; 1267 1268 usi_i2c_9: usi@109700c0 { 1269 compatible = "samsung,exynosautov9-usi", 1270 "samsung,exynos850-usi"; 1271 reg = <0x109700c0 0x20>; 1272 samsung,sysreg = <&syscon_peric1 0x101c>; 1273 samsung,mode = <USI_V2_I2C>; 1274 #address-cells = <1>; 1275 #size-cells = <1>; 1276 ranges; 1277 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_7>, 1278 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_7>; 1279 clock-names = "pclk", "ipclk"; 1280 status = "disabled"; 1281 1282 hsi2c_19: i2c@10970000 { 1283 compatible = "samsung,exynosautov9-hsi2c"; 1284 reg = <0x10970000 0xc0>; 1285 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1286 pinctrl-names = "default"; 1287 pinctrl-0 = <&hsi2c19_bus>; 1288 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_7>, 1289 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_7>; 1290 clock-names = "hsi2c", "hsi2c_pclk"; 1291 #address-cells = <1>; 1292 #size-cells = <0>; 1293 status = "disabled"; 1294 }; 1295 }; 1296 1297 usi_10: usi@109800c0 { 1298 compatible = "samsung,exynosautov9-usi", 1299 "samsung,exynos850-usi"; 1300 reg = <0x109800c0 0x20>; 1301 samsung,sysreg = <&syscon_peric1 0x1020>; 1302 samsung,mode = <USI_V2_UART>; 1303 #address-cells = <1>; 1304 #size-cells = <1>; 1305 ranges; 1306 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_8>, 1307 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_8>; 1308 clock-names = "pclk", "ipclk"; 1309 status = "disabled"; 1310 1311 serial_10: serial@10980000 { 1312 compatible = "samsung,exynosautov9-uart", 1313 "samsung,exynos850-uart"; 1314 reg = <0x10980000 0xc0>; 1315 interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>; 1316 pinctrl-names = "default"; 1317 pinctrl-0 = <&uart10_bus>; 1318 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_8>, 1319 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_8>; 1320 clock-names = "uart", "clk_uart_baud0"; 1321 samsung,uart-fifosize = <64>; 1322 status = "disabled"; 1323 }; 1324 1325 spi_10: spi@10980000 { 1326 compatible = "samsung,exynosautov9-spi"; 1327 reg = <0x10980000 0x30>; 1328 interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>; 1329 pinctrl-names = "default"; 1330 pinctrl-0 = <&spi10_bus &spi10_cs_func>; 1331 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_8>, 1332 <&cmu_peric1 CLK_DOUT_PERIC1_USI10_USI>, 1333 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_8>; 1334 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 1335 samsung,spi-src-clk = <0>; 1336 dmas = <&pdma0 21>, <&pdma0 20>; 1337 dma-names = "tx", "rx"; 1338 num-cs = <1>; 1339 #address-cells = <1>; 1340 #size-cells = <0>; 1341 status = "disabled"; 1342 }; 1343 1344 hsi2c_20: i2c@10980000 { 1345 compatible = "samsung,exynosautov9-hsi2c"; 1346 reg = <0x10980000 0xc0>; 1347 interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>; 1348 pinctrl-names = "default"; 1349 pinctrl-0 = <&hsi2c20_bus>; 1350 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_8>, 1351 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_8>; 1352 clock-names = "hsi2c", "hsi2c_pclk"; 1353 #address-cells = <1>; 1354 #size-cells = <0>; 1355 status = "disabled"; 1356 }; 1357 }; 1358 1359 usi_i2c_10: usi@109900c0 { 1360 compatible = "samsung,exynosautov9-usi", 1361 "samsung,exynos850-usi"; 1362 reg = <0x109900c0 0x20>; 1363 samsung,sysreg = <&syscon_peric1 0x1024>; 1364 samsung,mode = <USI_V2_I2C>; 1365 #address-cells = <1>; 1366 #size-cells = <1>; 1367 ranges; 1368 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_9>, 1369 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_9>; 1370 clock-names = "pclk", "ipclk"; 1371 status = "disabled"; 1372 1373 hsi2c_21: i2c@10990000 { 1374 compatible = "samsung,exynosautov9-hsi2c"; 1375 reg = <0x10990000 0xc0>; 1376 interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>; 1377 pinctrl-names = "default"; 1378 pinctrl-0 = <&hsi2c21_bus>; 1379 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_9>, 1380 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_9>; 1381 clock-names = "hsi2c", "hsi2c_pclk"; 1382 #address-cells = <1>; 1383 #size-cells = <0>; 1384 status = "disabled"; 1385 }; 1386 }; 1387 1388 usi_11: usi@109a00c0 { 1389 compatible = "samsung,exynosautov9-usi", 1390 "samsung,exynos850-usi"; 1391 reg = <0x109a00c0 0x20>; 1392 samsung,sysreg = <&syscon_peric1 0x1028>; 1393 samsung,mode = <USI_V2_UART>; 1394 #address-cells = <1>; 1395 #size-cells = <1>; 1396 ranges; 1397 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_10>, 1398 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_10>; 1399 clock-names = "pclk", "ipclk"; 1400 status = "disabled"; 1401 1402 serial_11: serial@109a0000 { 1403 compatible = "samsung,exynosautov9-uart", 1404 "samsung,exynos850-uart"; 1405 reg = <0x109a0000 0xc0>; 1406 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1407 pinctrl-names = "default"; 1408 pinctrl-0 = <&uart11_bus>; 1409 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_10>, 1410 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_10>; 1411 clock-names = "uart", "clk_uart_baud0"; 1412 samsung,uart-fifosize = <64>; 1413 status = "disabled"; 1414 }; 1415 1416 spi_11: spi@109a0000 { 1417 compatible = "samsung,exynosautov9-spi"; 1418 reg = <0x109a0000 0x30>; 1419 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1420 pinctrl-names = "default"; 1421 pinctrl-0 = <&spi11_bus &spi11_cs_func>; 1422 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_10>, 1423 <&cmu_peric1 CLK_DOUT_PERIC1_USI11_USI>, 1424 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_10>; 1425 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 1426 samsung,spi-src-clk = <0>; 1427 num-cs = <1>; 1428 #address-cells = <1>; 1429 #size-cells = <0>; 1430 status = "disabled"; 1431 }; 1432 1433 hsi2c_22: i2c@109a0000 { 1434 compatible = "samsung,exynosautov9-hsi2c"; 1435 reg = <0x109a0000 0xc0>; 1436 pinctrl-names = "default"; 1437 pinctrl-0 = <&hsi2c22_bus>; 1438 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1439 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_10>, 1440 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_10>; 1441 clock-names = "hsi2c", "hsi2c_pclk"; 1442 #address-cells = <1>; 1443 #size-cells = <0>; 1444 status = "disabled"; 1445 }; 1446 }; 1447 1448 usi_i2c_11: usi@109b00c0 { 1449 compatible = "samsung,exynosautov9-usi", 1450 "samsung,exynos850-usi"; 1451 reg = <0x109b00c0 0x20>; 1452 samsung,sysreg = <&syscon_peric1 0x102c>; 1453 samsung,mode = <USI_V2_I2C>; 1454 #address-cells = <1>; 1455 #size-cells = <1>; 1456 ranges; 1457 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_11>, 1458 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_11>; 1459 clock-names = "pclk", "ipclk"; 1460 status = "disabled"; 1461 1462 hsi2c_23: i2c@109b0000 { 1463 compatible = "samsung,exynosautov9-hsi2c"; 1464 reg = <0x109b0000 0xc0>; 1465 interrupts = <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>; 1466 pinctrl-names = "default"; 1467 pinctrl-0 = <&hsi2c23_bus>; 1468 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_11>, 1469 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_11>; 1470 clock-names = "hsi2c", "hsi2c_pclk"; 1471 #address-cells = <1>; 1472 #size-cells = <0>; 1473 status = "disabled"; 1474 }; 1475 }; 1476 1477 ufs_0_phy: phy@17e04000 { 1478 compatible = "samsung,exynosautov9-ufs-phy"; 1479 reg = <0x17e04000 0xc00>; 1480 reg-names = "phy-pma"; 1481 samsung,pmu-syscon = <&pmu_system_controller>; 1482 #phy-cells = <0>; 1483 clocks = <&xtcxo>; 1484 clock-names = "ref_clk"; 1485 status = "disabled"; 1486 }; 1487 1488 ufs_0: ufs@17e00000 { 1489 compatible = "samsung,exynosautov9-ufs"; 1490 1491 reg = <0x17e00000 0x100>, 1492 <0x17e01100 0x410>, 1493 <0x17e80000 0x8000>, 1494 <0x17dc0000 0x2200>; 1495 reg-names = "hci", "vs_hci", "unipro", "ufsp"; 1496 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 1497 clocks = <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD0_ACLK>, 1498 <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD0_UNIPRO>; 1499 clock-names = "core_clk", "sclk_unipro_main"; 1500 freq-table-hz = <0 0>, <0 0>; 1501 pinctrl-names = "default"; 1502 pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>; 1503 phys = <&ufs_0_phy>; 1504 phy-names = "ufs-phy"; 1505 samsung,sysreg = <&syscon_fsys2 0x710>; 1506 status = "disabled"; 1507 }; 1508 1509 ufs_1_phy: phy@17f04000 { 1510 compatible = "samsung,exynosautov9-ufs-phy"; 1511 reg = <0x17f04000 0xc00>; 1512 reg-names = "phy-pma"; 1513 samsung,pmu-syscon = <&pmu_system_controller 0x72c>; 1514 #phy-cells = <0>; 1515 clocks = <&xtcxo>; 1516 clock-names = "ref_clk"; 1517 status = "disabled"; 1518 }; 1519 1520 ufs_1: ufs@17f00000 { 1521 compatible = "samsung,exynosautov9-ufs"; 1522 1523 reg = <0x17f00000 0x100>, 1524 <0x17f01100 0x410>, 1525 <0x17f80000 0x8000>, 1526 <0x17de0000 0x2200>; 1527 reg-names = "hci", "vs_hci", "unipro", "ufsp"; 1528 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 1529 clocks = <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD1_ACLK>, 1530 <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO>; 1531 clock-names = "core_clk", "sclk_unipro_main"; 1532 freq-table-hz = <0 0>, <0 0>; 1533 pinctrl-names = "default"; 1534 pinctrl-0 = <&ufs_rst_n_1 &ufs_refclk_out_1>; 1535 phys = <&ufs_1_phy>; 1536 phy-names = "ufs-phy"; 1537 samsung,sysreg = <&syscon_fsys2 0x714>; 1538 status = "disabled"; 1539 }; 1540 1541 watchdog_cl0: watchdog@10050000 { 1542 compatible = "samsung,exynosautov9-wdt"; 1543 reg = <0x10050000 0x100>; 1544 interrupts = <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>; 1545 clocks = <&cmu_peris CLK_GOUT_WDT_CLUSTER0>, <&xtcxo>; 1546 clock-names = "watchdog", "watchdog_src"; 1547 samsung,syscon-phandle = <&pmu_system_controller>; 1548 samsung,cluster-index = <0>; 1549 }; 1550 1551 watchdog_cl1: watchdog@10060000 { 1552 compatible = "samsung,exynosautov9-wdt"; 1553 reg = <0x10060000 0x100>; 1554 interrupts = <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>; 1555 clocks = <&cmu_peris CLK_GOUT_WDT_CLUSTER1>, <&xtcxo>; 1556 clock-names = "watchdog", "watchdog_src"; 1557 samsung,syscon-phandle = <&pmu_system_controller>; 1558 samsung,cluster-index = <1>; 1559 }; 1560 }; 1561}; 1562 1563#include "exynosautov9-pinctrl.dtsi" 1564