1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/V2L SoC 4 * 5 * Copyright (C) 2021 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/r9a07g054-cpg.h> 10 11/ { 12 compatible = "renesas,r9a07g054"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 audio_clk1: audio1-clk { 17 compatible = "fixed-clock"; 18 #clock-cells = <0>; 19 /* This value must be overridden by boards that provide it */ 20 clock-frequency = <0>; 21 }; 22 23 audio_clk2: audio2-clk { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 /* This value must be overridden by boards that provide it */ 27 clock-frequency = <0>; 28 }; 29 30 /* External CAN clock - to be overridden by boards that provide it */ 31 can_clk: can-clk { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <0>; 35 }; 36 37 /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ 38 extal_clk: extal-clk { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 /* This value must be overridden by the board */ 42 clock-frequency = <0>; 43 }; 44 45 cluster0_opp: opp-table-0 { 46 compatible = "operating-points-v2"; 47 opp-shared; 48 49 opp-150000000 { 50 opp-hz = /bits/ 64 <150000000>; 51 opp-microvolt = <1100000>; 52 clock-latency-ns = <300000>; 53 }; 54 opp-300000000 { 55 opp-hz = /bits/ 64 <300000000>; 56 opp-microvolt = <1100000>; 57 clock-latency-ns = <300000>; 58 }; 59 opp-600000000 { 60 opp-hz = /bits/ 64 <600000000>; 61 opp-microvolt = <1100000>; 62 clock-latency-ns = <300000>; 63 }; 64 opp-1200000000 { 65 opp-hz = /bits/ 64 <1200000000>; 66 opp-microvolt = <1100000>; 67 clock-latency-ns = <300000>; 68 opp-suspend; 69 }; 70 }; 71 72 cpus { 73 #address-cells = <1>; 74 #size-cells = <0>; 75 76 cpu-map { 77 cluster0 { 78 core0 { 79 cpu = <&cpu0>; 80 }; 81 core1 { 82 cpu = <&cpu1>; 83 }; 84 }; 85 }; 86 87 cpu0: cpu@0 { 88 compatible = "arm,cortex-a55"; 89 reg = <0>; 90 device_type = "cpu"; 91 #cooling-cells = <2>; 92 next-level-cache = <&L3_CA55>; 93 enable-method = "psci"; 94 clocks = <&cpg CPG_CORE R9A07G054_CLK_I>; 95 operating-points-v2 = <&cluster0_opp>; 96 }; 97 98 cpu1: cpu@100 { 99 compatible = "arm,cortex-a55"; 100 reg = <0x100>; 101 device_type = "cpu"; 102 next-level-cache = <&L3_CA55>; 103 enable-method = "psci"; 104 clocks = <&cpg CPG_CORE R9A07G054_CLK_I>; 105 operating-points-v2 = <&cluster0_opp>; 106 }; 107 108 L3_CA55: cache-controller-0 { 109 compatible = "cache"; 110 cache-unified; 111 cache-size = <0x40000>; 112 }; 113 }; 114 115 gpu_opp_table: opp-table-1 { 116 compatible = "operating-points-v2"; 117 118 opp-500000000 { 119 opp-hz = /bits/ 64 <500000000>; 120 opp-microvolt = <1100000>; 121 }; 122 123 opp-400000000 { 124 opp-hz = /bits/ 64 <400000000>; 125 opp-microvolt = <1100000>; 126 }; 127 128 opp-250000000 { 129 opp-hz = /bits/ 64 <250000000>; 130 opp-microvolt = <1100000>; 131 }; 132 133 opp-200000000 { 134 opp-hz = /bits/ 64 <200000000>; 135 opp-microvolt = <1100000>; 136 }; 137 138 opp-125000000 { 139 opp-hz = /bits/ 64 <125000000>; 140 opp-microvolt = <1100000>; 141 }; 142 143 opp-100000000 { 144 opp-hz = /bits/ 64 <100000000>; 145 opp-microvolt = <1100000>; 146 }; 147 148 opp-62500000 { 149 opp-hz = /bits/ 64 <62500000>; 150 opp-microvolt = <1100000>; 151 }; 152 153 opp-50000000 { 154 opp-hz = /bits/ 64 <50000000>; 155 opp-microvolt = <1100000>; 156 }; 157 }; 158 159 psci { 160 compatible = "arm,psci-1.0", "arm,psci-0.2"; 161 method = "smc"; 162 }; 163 164 soc: soc { 165 compatible = "simple-bus"; 166 interrupt-parent = <&gic>; 167 #address-cells = <2>; 168 #size-cells = <2>; 169 ranges; 170 171 ssi0: ssi@10049c00 { 172 compatible = "renesas,r9a07g054-ssi", 173 "renesas,rz-ssi"; 174 reg = <0 0x10049c00 0 0x400>; 175 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>, 177 <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>, 178 <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>; 179 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 180 clocks = <&cpg CPG_MOD R9A07G054_SSI0_PCLK2>, 181 <&cpg CPG_MOD R9A07G054_SSI0_PCLK_SFR>, 182 <&audio_clk1>, <&audio_clk2>; 183 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 184 resets = <&cpg R9A07G054_SSI0_RST_M2_REG>; 185 dmas = <&dmac 0x2655>, <&dmac 0x2656>; 186 dma-names = "tx", "rx"; 187 power-domains = <&cpg>; 188 #sound-dai-cells = <0>; 189 status = "disabled"; 190 }; 191 192 ssi1: ssi@1004a000 { 193 compatible = "renesas,r9a07g054-ssi", 194 "renesas,rz-ssi"; 195 reg = <0 0x1004a000 0 0x400>; 196 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>, 198 <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>, 199 <GIC_SPI 333 IRQ_TYPE_EDGE_RISING>; 200 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 201 clocks = <&cpg CPG_MOD R9A07G054_SSI1_PCLK2>, 202 <&cpg CPG_MOD R9A07G054_SSI1_PCLK_SFR>, 203 <&audio_clk1>, <&audio_clk2>; 204 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 205 resets = <&cpg R9A07G054_SSI1_RST_M2_REG>; 206 dmas = <&dmac 0x2659>, <&dmac 0x265a>; 207 dma-names = "tx", "rx"; 208 power-domains = <&cpg>; 209 #sound-dai-cells = <0>; 210 status = "disabled"; 211 }; 212 213 ssi2: ssi@1004a400 { 214 compatible = "renesas,r9a07g054-ssi", 215 "renesas,rz-ssi"; 216 reg = <0 0x1004a400 0 0x400>; 217 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 335 IRQ_TYPE_EDGE_RISING>, 219 <GIC_SPI 336 IRQ_TYPE_EDGE_RISING>, 220 <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>; 221 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 222 clocks = <&cpg CPG_MOD R9A07G054_SSI2_PCLK2>, 223 <&cpg CPG_MOD R9A07G054_SSI2_PCLK_SFR>, 224 <&audio_clk1>, <&audio_clk2>; 225 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 226 resets = <&cpg R9A07G054_SSI2_RST_M2_REG>; 227 dmas = <&dmac 0x265f>; 228 dma-names = "rt"; 229 power-domains = <&cpg>; 230 #sound-dai-cells = <0>; 231 status = "disabled"; 232 }; 233 234 ssi3: ssi@1004a800 { 235 compatible = "renesas,r9a07g054-ssi", 236 "renesas,rz-ssi"; 237 reg = <0 0x1004a800 0 0x400>; 238 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 239 <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>, 240 <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>, 241 <GIC_SPI 341 IRQ_TYPE_EDGE_RISING>; 242 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 243 clocks = <&cpg CPG_MOD R9A07G054_SSI3_PCLK2>, 244 <&cpg CPG_MOD R9A07G054_SSI3_PCLK_SFR>, 245 <&audio_clk1>, <&audio_clk2>; 246 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 247 resets = <&cpg R9A07G054_SSI3_RST_M2_REG>; 248 dmas = <&dmac 0x2661>, <&dmac 0x2662>; 249 dma-names = "tx", "rx"; 250 power-domains = <&cpg>; 251 #sound-dai-cells = <0>; 252 status = "disabled"; 253 }; 254 255 spi0: spi@1004ac00 { 256 compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz"; 257 reg = <0 0x1004ac00 0 0x400>; 258 interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 259 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 260 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>; 261 interrupt-names = "error", "rx", "tx"; 262 clocks = <&cpg CPG_MOD R9A07G054_RSPI0_CLKB>; 263 resets = <&cpg R9A07G054_RSPI0_RST>; 264 dmas = <&dmac 0x2e95>, <&dmac 0x2e96>; 265 dma-names = "tx", "rx"; 266 power-domains = <&cpg>; 267 num-cs = <1>; 268 #address-cells = <1>; 269 #size-cells = <0>; 270 status = "disabled"; 271 }; 272 273 spi1: spi@1004b000 { 274 compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz"; 275 reg = <0 0x1004b000 0 0x400>; 276 interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 277 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 278 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>; 279 interrupt-names = "error", "rx", "tx"; 280 clocks = <&cpg CPG_MOD R9A07G054_RSPI1_CLKB>; 281 resets = <&cpg R9A07G054_RSPI1_RST>; 282 dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>; 283 dma-names = "tx", "rx"; 284 power-domains = <&cpg>; 285 num-cs = <1>; 286 #address-cells = <1>; 287 #size-cells = <0>; 288 status = "disabled"; 289 }; 290 291 spi2: spi@1004b400 { 292 compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz"; 293 reg = <0 0x1004b400 0 0x400>; 294 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 295 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 296 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>; 297 interrupt-names = "error", "rx", "tx"; 298 clocks = <&cpg CPG_MOD R9A07G054_RSPI2_CLKB>; 299 resets = <&cpg R9A07G054_RSPI2_RST>; 300 dmas = <&dmac 0x2e9d>, <&dmac 0x2e9e>; 301 dma-names = "tx", "rx"; 302 power-domains = <&cpg>; 303 num-cs = <1>; 304 #address-cells = <1>; 305 #size-cells = <0>; 306 status = "disabled"; 307 }; 308 309 scif0: serial@1004b800 { 310 compatible = "renesas,scif-r9a07g054", 311 "renesas,scif-r9a07g044"; 312 reg = <0 0x1004b800 0 0x400>; 313 interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, 314 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, 315 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 316 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, 317 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 318 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 319 interrupt-names = "eri", "rxi", "txi", 320 "bri", "dri", "tei"; 321 clocks = <&cpg CPG_MOD R9A07G054_SCIF0_CLK_PCK>; 322 clock-names = "fck"; 323 power-domains = <&cpg>; 324 resets = <&cpg R9A07G054_SCIF0_RST_SYSTEM_N>; 325 status = "disabled"; 326 }; 327 328 scif1: serial@1004bc00 { 329 compatible = "renesas,scif-r9a07g054", 330 "renesas,scif-r9a07g044"; 331 reg = <0 0x1004bc00 0 0x400>; 332 interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 333 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 334 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 335 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 336 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 337 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; 338 interrupt-names = "eri", "rxi", "txi", 339 "bri", "dri", "tei"; 340 clocks = <&cpg CPG_MOD R9A07G054_SCIF1_CLK_PCK>; 341 clock-names = "fck"; 342 power-domains = <&cpg>; 343 resets = <&cpg R9A07G054_SCIF1_RST_SYSTEM_N>; 344 status = "disabled"; 345 }; 346 347 scif2: serial@1004c000 { 348 compatible = "renesas,scif-r9a07g054", 349 "renesas,scif-r9a07g044"; 350 reg = <0 0x1004c000 0 0x400>; 351 interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 352 <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>, 353 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 354 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, 355 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 356 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>; 357 interrupt-names = "eri", "rxi", "txi", 358 "bri", "dri", "tei"; 359 clocks = <&cpg CPG_MOD R9A07G054_SCIF2_CLK_PCK>; 360 clock-names = "fck"; 361 power-domains = <&cpg>; 362 resets = <&cpg R9A07G054_SCIF2_RST_SYSTEM_N>; 363 status = "disabled"; 364 }; 365 366 scif3: serial@1004c400 { 367 compatible = "renesas,scif-r9a07g054", 368 "renesas,scif-r9a07g044"; 369 reg = <0 0x1004c400 0 0x400>; 370 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 371 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 372 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 373 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 374 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 375 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>; 376 interrupt-names = "eri", "rxi", "txi", 377 "bri", "dri", "tei"; 378 clocks = <&cpg CPG_MOD R9A07G054_SCIF3_CLK_PCK>; 379 clock-names = "fck"; 380 power-domains = <&cpg>; 381 resets = <&cpg R9A07G054_SCIF3_RST_SYSTEM_N>; 382 status = "disabled"; 383 }; 384 385 scif4: serial@1004c800 { 386 compatible = "renesas,scif-r9a07g054", 387 "renesas,scif-r9a07g044"; 388 reg = <0 0x1004c800 0 0x400>; 389 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 390 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 391 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 392 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 393 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 394 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; 395 interrupt-names = "eri", "rxi", "txi", 396 "bri", "dri", "tei"; 397 clocks = <&cpg CPG_MOD R9A07G054_SCIF4_CLK_PCK>; 398 clock-names = "fck"; 399 power-domains = <&cpg>; 400 resets = <&cpg R9A07G054_SCIF4_RST_SYSTEM_N>; 401 status = "disabled"; 402 }; 403 404 sci0: serial@1004d000 { 405 compatible = "renesas,r9a07g054-sci", "renesas,sci"; 406 reg = <0 0x1004d000 0 0x400>; 407 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 408 <GIC_SPI 406 IRQ_TYPE_EDGE_RISING>, 409 <GIC_SPI 407 IRQ_TYPE_EDGE_RISING>, 410 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 411 interrupt-names = "eri", "rxi", "txi", "tei"; 412 clocks = <&cpg CPG_MOD R9A07G054_SCI0_CLKP>; 413 clock-names = "fck"; 414 power-domains = <&cpg>; 415 resets = <&cpg R9A07G054_SCI0_RST>; 416 status = "disabled"; 417 }; 418 419 sci1: serial@1004d400 { 420 compatible = "renesas,r9a07g054-sci", "renesas,sci"; 421 reg = <0 0x1004d400 0 0x400>; 422 interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 423 <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>, 424 <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>, 425 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; 426 interrupt-names = "eri", "rxi", "txi", "tei"; 427 clocks = <&cpg CPG_MOD R9A07G054_SCI1_CLKP>; 428 clock-names = "fck"; 429 power-domains = <&cpg>; 430 resets = <&cpg R9A07G054_SCI1_RST>; 431 status = "disabled"; 432 }; 433 434 canfd: can@10050000 { 435 compatible = "renesas,r9a07g054-canfd", "renesas,rzg2l-canfd"; 436 reg = <0 0x10050000 0 0x8000>; 437 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 442 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 443 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>; 445 interrupt-names = "g_err", "g_recc", 446 "ch0_err", "ch0_rec", "ch0_trx", 447 "ch1_err", "ch1_rec", "ch1_trx"; 448 clocks = <&cpg CPG_MOD R9A07G054_CANFD_PCLK>, 449 <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>, 450 <&can_clk>; 451 clock-names = "fck", "canfd", "can_clk"; 452 assigned-clocks = <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>; 453 assigned-clock-rates = <50000000>; 454 resets = <&cpg R9A07G054_CANFD_RSTP_N>, 455 <&cpg R9A07G054_CANFD_RSTC_N>; 456 reset-names = "rstp_n", "rstc_n"; 457 power-domains = <&cpg>; 458 status = "disabled"; 459 460 channel0 { 461 status = "disabled"; 462 }; 463 channel1 { 464 status = "disabled"; 465 }; 466 }; 467 468 i2c0: i2c@10058000 { 469 #address-cells = <1>; 470 #size-cells = <0>; 471 compatible = "renesas,riic-r9a07g054", "renesas,riic-rz"; 472 reg = <0 0x10058000 0 0x400>; 473 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>, 475 <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>, 476 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 479 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 481 interrupt-names = "tei", "ri", "ti", "spi", "sti", 482 "naki", "ali", "tmoi"; 483 clocks = <&cpg CPG_MOD R9A07G054_I2C0_PCLK>; 484 clock-frequency = <100000>; 485 resets = <&cpg R9A07G054_I2C0_MRST>; 486 power-domains = <&cpg>; 487 status = "disabled"; 488 }; 489 490 i2c1: i2c@10058400 { 491 #address-cells = <1>; 492 #size-cells = <0>; 493 compatible = "renesas,riic-r9a07g054", "renesas,riic-rz"; 494 reg = <0 0x10058400 0 0x400>; 495 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>, 497 <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>, 498 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 499 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 500 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 503 interrupt-names = "tei", "ri", "ti", "spi", "sti", 504 "naki", "ali", "tmoi"; 505 clocks = <&cpg CPG_MOD R9A07G054_I2C1_PCLK>; 506 clock-frequency = <100000>; 507 resets = <&cpg R9A07G054_I2C1_MRST>; 508 power-domains = <&cpg>; 509 status = "disabled"; 510 }; 511 512 i2c2: i2c@10058800 { 513 #address-cells = <1>; 514 #size-cells = <0>; 515 compatible = "renesas,riic-r9a07g054", "renesas,riic-rz"; 516 reg = <0 0x10058800 0 0x400>; 517 interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 519 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 520 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 525 interrupt-names = "tei", "ri", "ti", "spi", "sti", 526 "naki", "ali", "tmoi"; 527 clocks = <&cpg CPG_MOD R9A07G054_I2C2_PCLK>; 528 clock-frequency = <100000>; 529 resets = <&cpg R9A07G054_I2C2_MRST>; 530 power-domains = <&cpg>; 531 status = "disabled"; 532 }; 533 534 i2c3: i2c@10058c00 { 535 #address-cells = <1>; 536 #size-cells = <0>; 537 compatible = "renesas,riic-r9a07g054", "renesas,riic-rz"; 538 reg = <0 0x10058c00 0 0x400>; 539 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 540 <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>, 541 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>, 542 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, 543 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 545 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 547 interrupt-names = "tei", "ri", "ti", "spi", "sti", 548 "naki", "ali", "tmoi"; 549 clocks = <&cpg CPG_MOD R9A07G054_I2C3_PCLK>; 550 clock-frequency = <100000>; 551 resets = <&cpg R9A07G054_I2C3_MRST>; 552 power-domains = <&cpg>; 553 status = "disabled"; 554 }; 555 556 adc: adc@10059000 { 557 compatible = "renesas,r9a07g054-adc", "renesas,rzg2l-adc"; 558 reg = <0 0x10059000 0 0x400>; 559 interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>; 560 clocks = <&cpg CPG_MOD R9A07G054_ADC_ADCLK>, 561 <&cpg CPG_MOD R9A07G054_ADC_PCLK>; 562 clock-names = "adclk", "pclk"; 563 resets = <&cpg R9A07G054_ADC_PRESETN>, 564 <&cpg R9A07G054_ADC_ADRST_N>; 565 reset-names = "presetn", "adrst-n"; 566 power-domains = <&cpg>; 567 status = "disabled"; 568 569 #address-cells = <1>; 570 #size-cells = <0>; 571 572 channel@0 { 573 reg = <0>; 574 }; 575 channel@1 { 576 reg = <1>; 577 }; 578 channel@2 { 579 reg = <2>; 580 }; 581 channel@3 { 582 reg = <3>; 583 }; 584 channel@4 { 585 reg = <4>; 586 }; 587 channel@5 { 588 reg = <5>; 589 }; 590 channel@6 { 591 reg = <6>; 592 }; 593 channel@7 { 594 reg = <7>; 595 }; 596 }; 597 598 tsu: thermal@10059400 { 599 compatible = "renesas,r9a07g054-tsu", 600 "renesas,rzg2l-tsu"; 601 reg = <0 0x10059400 0 0x400>; 602 clocks = <&cpg CPG_MOD R9A07G054_TSU_PCLK>; 603 resets = <&cpg R9A07G054_TSU_PRESETN>; 604 power-domains = <&cpg>; 605 #thermal-sensor-cells = <1>; 606 }; 607 608 sbc: spi@10060000 { 609 compatible = "renesas,r9a07g054-rpc-if", 610 "renesas,rzg2l-rpc-if"; 611 reg = <0 0x10060000 0 0x10000>, 612 <0 0x20000000 0 0x10000000>, 613 <0 0x10070000 0 0x10000>; 614 reg-names = "regs", "dirmap", "wbuf"; 615 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 616 clocks = <&cpg CPG_MOD R9A07G054_SPI_CLK2>, 617 <&cpg CPG_MOD R9A07G054_SPI_CLK>; 618 resets = <&cpg R9A07G054_SPI_RST>; 619 power-domains = <&cpg>; 620 #address-cells = <1>; 621 #size-cells = <0>; 622 status = "disabled"; 623 }; 624 625 cpg: clock-controller@11010000 { 626 compatible = "renesas,r9a07g054-cpg"; 627 reg = <0 0x11010000 0 0x10000>; 628 clocks = <&extal_clk>; 629 clock-names = "extal"; 630 #clock-cells = <2>; 631 #reset-cells = <1>; 632 #power-domain-cells = <0>; 633 }; 634 635 sysc: system-controller@11020000 { 636 compatible = "renesas,r9a07g054-sysc"; 637 reg = <0 0x11020000 0 0x10000>; 638 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 639 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 642 interrupt-names = "lpm_int", "ca55stbydone_int", 643 "cm33stbyr_int", "ca55_deny"; 644 status = "disabled"; 645 }; 646 647 pinctrl: pinctrl@11030000 { 648 compatible = "renesas,r9a07g054-pinctrl", 649 "renesas,r9a07g044-pinctrl"; 650 reg = <0 0x11030000 0 0x10000>; 651 gpio-controller; 652 #gpio-cells = <2>; 653 #address-cells = <2>; 654 #interrupt-cells = <2>; 655 interrupt-parent = <&irqc>; 656 interrupt-controller; 657 gpio-ranges = <&pinctrl 0 0 392>; 658 clocks = <&cpg CPG_MOD R9A07G054_GPIO_HCLK>; 659 power-domains = <&cpg>; 660 resets = <&cpg R9A07G054_GPIO_RSTN>, 661 <&cpg R9A07G054_GPIO_PORT_RESETN>, 662 <&cpg R9A07G054_GPIO_SPARE_RESETN>; 663 }; 664 665 irqc: interrupt-controller@110a0000 { 666 compatible = "renesas,r9a07g054-irqc", 667 "renesas,rzg2l-irqc"; 668 #interrupt-cells = <2>; 669 #address-cells = <0>; 670 interrupt-controller; 671 reg = <0 0x110a0000 0 0x10000>; 672 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 673 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 674 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 675 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 676 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 677 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 678 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 679 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 680 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 681 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 682 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>, 683 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 684 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 685 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 686 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 689 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 690 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 691 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, 692 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 693 <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, 694 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, 695 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 696 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, 697 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, 698 <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, 699 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 700 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 704 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 705 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 706 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 708 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 709 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 710 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 711 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 712 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>; 713 clocks = <&cpg CPG_MOD R9A07G054_IA55_CLK>, 714 <&cpg CPG_MOD R9A07G054_IA55_PCLK>; 715 clock-names = "clk", "pclk"; 716 power-domains = <&cpg>; 717 resets = <&cpg R9A07G054_IA55_RESETN>; 718 }; 719 720 dmac: dma-controller@11820000 { 721 compatible = "renesas,r9a07g054-dmac", 722 "renesas,rz-dmac"; 723 reg = <0 0x11820000 0 0x10000>, 724 <0 0x11830000 0 0x10000>; 725 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>, 726 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>, 727 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>, 728 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>, 729 <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>, 730 <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>, 731 <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>, 732 <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>, 733 <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>, 734 <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>, 735 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, 736 <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>, 737 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, 738 <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>, 739 <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>, 740 <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>, 741 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>; 742 interrupt-names = "error", 743 "ch0", "ch1", "ch2", "ch3", 744 "ch4", "ch5", "ch6", "ch7", 745 "ch8", "ch9", "ch10", "ch11", 746 "ch12", "ch13", "ch14", "ch15"; 747 clocks = <&cpg CPG_MOD R9A07G054_DMAC_ACLK>, 748 <&cpg CPG_MOD R9A07G054_DMAC_PCLK>; 749 power-domains = <&cpg>; 750 resets = <&cpg R9A07G054_DMAC_ARESETN>, 751 <&cpg R9A07G054_DMAC_RST_ASYNC>; 752 #dma-cells = <1>; 753 dma-channels = <16>; 754 }; 755 756 gpu: gpu@11840000 { 757 compatible = "renesas,r9a07g054-mali", 758 "arm,mali-bifrost"; 759 reg = <0x0 0x11840000 0x0 0x10000>; 760 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 761 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 762 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 763 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 764 interrupt-names = "job", "mmu", "gpu", "event"; 765 clocks = <&cpg CPG_MOD R9A07G054_GPU_CLK>, 766 <&cpg CPG_MOD R9A07G054_GPU_AXI_CLK>, 767 <&cpg CPG_MOD R9A07G054_GPU_ACE_CLK>; 768 clock-names = "gpu", "bus", "bus_ace"; 769 power-domains = <&cpg>; 770 resets = <&cpg R9A07G054_GPU_RESETN>, 771 <&cpg R9A07G054_GPU_AXI_RESETN>, 772 <&cpg R9A07G054_GPU_ACE_RESETN>; 773 reset-names = "rst", "axi_rst", "ace_rst"; 774 operating-points-v2 = <&gpu_opp_table>; 775 }; 776 777 gic: interrupt-controller@11900000 { 778 compatible = "arm,gic-v3"; 779 #interrupt-cells = <3>; 780 #address-cells = <0>; 781 interrupt-controller; 782 reg = <0x0 0x11900000 0 0x40000>, 783 <0x0 0x11940000 0 0x60000>; 784 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 785 }; 786 787 sdhi0: mmc@11c00000 { 788 compatible = "renesas,sdhi-r9a07g054", 789 "renesas,rcar-gen3-sdhi"; 790 reg = <0x0 0x11c00000 0 0x10000>; 791 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 792 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 793 clocks = <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK>, 794 <&cpg CPG_MOD R9A07G054_SDHI0_CLK_HS>, 795 <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK2>, 796 <&cpg CPG_MOD R9A07G054_SDHI0_ACLK>; 797 clock-names = "core", "clkh", "cd", "aclk"; 798 resets = <&cpg R9A07G054_SDHI0_IXRST>; 799 power-domains = <&cpg>; 800 status = "disabled"; 801 }; 802 803 sdhi1: mmc@11c10000 { 804 compatible = "renesas,sdhi-r9a07g054", 805 "renesas,rcar-gen3-sdhi"; 806 reg = <0x0 0x11c10000 0 0x10000>; 807 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 808 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 809 clocks = <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK>, 810 <&cpg CPG_MOD R9A07G054_SDHI1_CLK_HS>, 811 <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK2>, 812 <&cpg CPG_MOD R9A07G054_SDHI1_ACLK>; 813 clock-names = "core", "clkh", "cd", "aclk"; 814 resets = <&cpg R9A07G054_SDHI1_IXRST>; 815 power-domains = <&cpg>; 816 status = "disabled"; 817 }; 818 819 eth0: ethernet@11c20000 { 820 compatible = "renesas,r9a07g054-gbeth", 821 "renesas,rzg2l-gbeth"; 822 reg = <0 0x11c20000 0 0x10000>; 823 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 824 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 825 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 826 interrupt-names = "mux", "fil", "arp_ns"; 827 phy-mode = "rgmii"; 828 clocks = <&cpg CPG_MOD R9A07G054_ETH0_CLK_AXI>, 829 <&cpg CPG_MOD R9A07G054_ETH0_CLK_CHI>, 830 <&cpg CPG_CORE R9A07G054_CLK_HP>; 831 clock-names = "axi", "chi", "refclk"; 832 resets = <&cpg R9A07G054_ETH0_RST_HW_N>; 833 power-domains = <&cpg>; 834 #address-cells = <1>; 835 #size-cells = <0>; 836 status = "disabled"; 837 }; 838 839 eth1: ethernet@11c30000 { 840 compatible = "renesas,r9a07g054-gbeth", 841 "renesas,rzg2l-gbeth"; 842 reg = <0 0x11c30000 0 0x10000>; 843 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 844 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 845 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 846 interrupt-names = "mux", "fil", "arp_ns"; 847 phy-mode = "rgmii"; 848 clocks = <&cpg CPG_MOD R9A07G054_ETH1_CLK_AXI>, 849 <&cpg CPG_MOD R9A07G054_ETH1_CLK_CHI>, 850 <&cpg CPG_CORE R9A07G054_CLK_HP>; 851 clock-names = "axi", "chi", "refclk"; 852 resets = <&cpg R9A07G054_ETH1_RST_HW_N>; 853 power-domains = <&cpg>; 854 #address-cells = <1>; 855 #size-cells = <0>; 856 status = "disabled"; 857 }; 858 859 phyrst: usbphy-ctrl@11c40000 { 860 compatible = "renesas,r9a07g054-usbphy-ctrl", 861 "renesas,rzg2l-usbphy-ctrl"; 862 reg = <0 0x11c40000 0 0x10000>; 863 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>; 864 resets = <&cpg R9A07G054_USB_PRESETN>; 865 power-domains = <&cpg>; 866 #reset-cells = <1>; 867 status = "disabled"; 868 }; 869 870 ohci0: usb@11c50000 { 871 compatible = "generic-ohci"; 872 reg = <0 0x11c50000 0 0x100>; 873 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 874 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, 875 <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>; 876 resets = <&phyrst 0>, 877 <&cpg R9A07G054_USB_U2H0_HRESETN>; 878 phys = <&usb2_phy0 1>; 879 phy-names = "usb"; 880 power-domains = <&cpg>; 881 status = "disabled"; 882 }; 883 884 ohci1: usb@11c70000 { 885 compatible = "generic-ohci"; 886 reg = <0 0x11c70000 0 0x100>; 887 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 888 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, 889 <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>; 890 resets = <&phyrst 1>, 891 <&cpg R9A07G054_USB_U2H1_HRESETN>; 892 phys = <&usb2_phy1 1>; 893 phy-names = "usb"; 894 power-domains = <&cpg>; 895 status = "disabled"; 896 }; 897 898 ehci0: usb@11c50100 { 899 compatible = "generic-ehci"; 900 reg = <0 0x11c50100 0 0x100>; 901 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 902 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, 903 <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>; 904 resets = <&phyrst 0>, 905 <&cpg R9A07G054_USB_U2H0_HRESETN>; 906 phys = <&usb2_phy0 2>; 907 phy-names = "usb"; 908 companion = <&ohci0>; 909 power-domains = <&cpg>; 910 status = "disabled"; 911 }; 912 913 ehci1: usb@11c70100 { 914 compatible = "generic-ehci"; 915 reg = <0 0x11c70100 0 0x100>; 916 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 917 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, 918 <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>; 919 resets = <&phyrst 1>, 920 <&cpg R9A07G054_USB_U2H1_HRESETN>; 921 phys = <&usb2_phy1 2>; 922 phy-names = "usb"; 923 companion = <&ohci1>; 924 power-domains = <&cpg>; 925 status = "disabled"; 926 }; 927 928 usb2_phy0: usb-phy@11c50200 { 929 compatible = "renesas,usb2-phy-r9a07g054", 930 "renesas,rzg2l-usb2-phy"; 931 reg = <0 0x11c50200 0 0x700>; 932 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 933 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, 934 <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>; 935 resets = <&phyrst 0>; 936 #phy-cells = <1>; 937 power-domains = <&cpg>; 938 status = "disabled"; 939 }; 940 941 usb2_phy1: usb-phy@11c70200 { 942 compatible = "renesas,usb2-phy-r9a07g054", 943 "renesas,rzg2l-usb2-phy"; 944 reg = <0 0x11c70200 0 0x700>; 945 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 946 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, 947 <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>; 948 resets = <&phyrst 1>; 949 #phy-cells = <1>; 950 power-domains = <&cpg>; 951 status = "disabled"; 952 }; 953 954 hsusb: usb@11c60000 { 955 compatible = "renesas,usbhs-r9a07g054", 956 "renesas,rza2-usbhs"; 957 reg = <0 0x11c60000 0 0x10000>; 958 interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>, 959 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 960 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 961 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 962 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, 963 <&cpg CPG_MOD R9A07G054_USB_U2P_EXR_CPUCLK>; 964 resets = <&phyrst 0>, 965 <&cpg R9A07G054_USB_U2P_EXL_SYSRST>; 966 renesas,buswait = <7>; 967 phys = <&usb2_phy0 3>; 968 phy-names = "usb"; 969 power-domains = <&cpg>; 970 status = "disabled"; 971 }; 972 973 wdt0: watchdog@12800800 { 974 compatible = "renesas,r9a07g054-wdt", 975 "renesas,rzg2l-wdt"; 976 reg = <0 0x12800800 0 0x400>; 977 clocks = <&cpg CPG_MOD R9A07G054_WDT0_PCLK>, 978 <&cpg CPG_MOD R9A07G054_WDT0_CLK>; 979 clock-names = "pclk", "oscclk"; 980 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 981 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 982 interrupt-names = "wdt", "perrout"; 983 resets = <&cpg R9A07G054_WDT0_PRESETN>; 984 power-domains = <&cpg>; 985 status = "disabled"; 986 }; 987 988 wdt1: watchdog@12800c00 { 989 compatible = "renesas,r9a07g054-wdt", 990 "renesas,rzg2l-wdt"; 991 reg = <0 0x12800C00 0 0x400>; 992 clocks = <&cpg CPG_MOD R9A07G054_WDT1_PCLK>, 993 <&cpg CPG_MOD R9A07G054_WDT1_CLK>; 994 clock-names = "pclk", "oscclk"; 995 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 996 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 997 interrupt-names = "wdt", "perrout"; 998 resets = <&cpg R9A07G054_WDT1_PRESETN>; 999 power-domains = <&cpg>; 1000 status = "disabled"; 1001 }; 1002 1003 wdt2: watchdog@12800400 { 1004 compatible = "renesas,r9a07g054-wdt", 1005 "renesas,rzg2l-wdt"; 1006 reg = <0 0x12800400 0 0x400>; 1007 clocks = <&cpg CPG_MOD R9A07G054_WDT2_PCLK>, 1008 <&cpg CPG_MOD R9A07G054_WDT2_CLK>; 1009 clock-names = "pclk", "oscclk"; 1010 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 1011 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1012 interrupt-names = "wdt", "perrout"; 1013 resets = <&cpg R9A07G054_WDT2_PRESETN>; 1014 power-domains = <&cpg>; 1015 status = "disabled"; 1016 }; 1017 1018 ostm0: timer@12801000 { 1019 compatible = "renesas,r9a07g054-ostm", 1020 "renesas,ostm"; 1021 reg = <0x0 0x12801000 0x0 0x400>; 1022 interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>; 1023 clocks = <&cpg CPG_MOD R9A07G054_OSTM0_PCLK>; 1024 resets = <&cpg R9A07G054_OSTM0_PRESETZ>; 1025 power-domains = <&cpg>; 1026 status = "disabled"; 1027 }; 1028 1029 ostm1: timer@12801400 { 1030 compatible = "renesas,r9a07g054-ostm", 1031 "renesas,ostm"; 1032 reg = <0x0 0x12801400 0x0 0x400>; 1033 interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>; 1034 clocks = <&cpg CPG_MOD R9A07G054_OSTM1_PCLK>; 1035 resets = <&cpg R9A07G054_OSTM1_PRESETZ>; 1036 power-domains = <&cpg>; 1037 status = "disabled"; 1038 }; 1039 1040 ostm2: timer@12801800 { 1041 compatible = "renesas,r9a07g054-ostm", 1042 "renesas,ostm"; 1043 reg = <0x0 0x12801800 0x0 0x400>; 1044 interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>; 1045 clocks = <&cpg CPG_MOD R9A07G054_OSTM2_PCLK>; 1046 resets = <&cpg R9A07G054_OSTM2_PRESETZ>; 1047 power-domains = <&cpg>; 1048 status = "disabled"; 1049 }; 1050 }; 1051 1052 thermal-zones { 1053 cpu-thermal { 1054 polling-delay-passive = <250>; 1055 polling-delay = <1000>; 1056 thermal-sensors = <&tsu 0>; 1057 sustainable-power = <717>; 1058 1059 cooling-maps { 1060 map0 { 1061 trip = <&target>; 1062 cooling-device = <&cpu0 0 2>; 1063 contribution = <1024>; 1064 }; 1065 }; 1066 1067 trips { 1068 sensor_crit: sensor-crit { 1069 temperature = <125000>; 1070 hysteresis = <1000>; 1071 type = "critical"; 1072 }; 1073 1074 target: trip-point { 1075 temperature = <100000>; 1076 hysteresis = <1000>; 1077 type = "passive"; 1078 }; 1079 }; 1080 }; 1081 }; 1082 1083 timer { 1084 compatible = "arm,armv8-timer"; 1085 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1086 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1087 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1088 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 1089 }; 1090}; 1091