1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2021 Linaro Ltd.
4  * Author: Sam Protsenko <semen.protsenko@linaro.org>
5  *
6  * Common Clock Framework support for Exynos850 SoC.
7  */
8 
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/of.h>
12 #include <linux/of_device.h>
13 #include <linux/platform_device.h>
14 
15 #include <dt-bindings/clock/exynos850.h>
16 
17 #include "clk.h"
18 #include "clk-exynos-arm64.h"
19 
20 /* ---- CMU_TOP ------------------------------------------------------------- */
21 
22 /* Register Offset definitions for CMU_TOP (0x120e0000) */
23 #define PLL_LOCKTIME_PLL_MMC			0x0000
24 #define PLL_LOCKTIME_PLL_SHARED0		0x0004
25 #define PLL_LOCKTIME_PLL_SHARED1		0x0008
26 #define PLL_CON0_PLL_MMC			0x0100
27 #define PLL_CON3_PLL_MMC			0x010c
28 #define PLL_CON0_PLL_SHARED0			0x0140
29 #define PLL_CON3_PLL_SHARED0			0x014c
30 #define PLL_CON0_PLL_SHARED1			0x0180
31 #define PLL_CON3_PLL_SHARED1			0x018c
32 #define CLK_CON_MUX_MUX_CLKCMU_APM_BUS		0x1000
33 #define CLK_CON_MUX_MUX_CLKCMU_AUD		0x1004
34 #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS		0x1014
35 #define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI		0x1018
36 #define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD	0x101c
37 #define CLK_CON_MUX_MUX_CLKCMU_CORE_SSS		0x1020
38 #define CLK_CON_MUX_MUX_CLKCMU_DPU		0x1034
39 #define CLK_CON_MUX_MUX_CLKCMU_HSI_BUS		0x103c
40 #define CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD	0x1040
41 #define CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD	0x1044
42 #define CLK_CON_MUX_MUX_CLKCMU_IS_BUS		0x1048
43 #define CLK_CON_MUX_MUX_CLKCMU_IS_GDC		0x104c
44 #define CLK_CON_MUX_MUX_CLKCMU_IS_ITP		0x1050
45 #define CLK_CON_MUX_MUX_CLKCMU_IS_VRA		0x1054
46 #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_JPEG	0x1058
47 #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_M2M	0x105c
48 #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MCSC	0x1060
49 #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC	0x1064
50 #define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS		0x1070
51 #define CLK_CON_MUX_MUX_CLKCMU_PERI_IP		0x1074
52 #define CLK_CON_MUX_MUX_CLKCMU_PERI_UART	0x1078
53 #define CLK_CON_DIV_CLKCMU_APM_BUS		0x180c
54 #define CLK_CON_DIV_CLKCMU_AUD			0x1810
55 #define CLK_CON_DIV_CLKCMU_CORE_BUS		0x1820
56 #define CLK_CON_DIV_CLKCMU_CORE_CCI		0x1824
57 #define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD	0x1828
58 #define CLK_CON_DIV_CLKCMU_CORE_SSS		0x182c
59 #define CLK_CON_DIV_CLKCMU_DPU			0x1840
60 #define CLK_CON_DIV_CLKCMU_HSI_BUS		0x1848
61 #define CLK_CON_DIV_CLKCMU_HSI_MMC_CARD		0x184c
62 #define CLK_CON_DIV_CLKCMU_HSI_USB20DRD		0x1850
63 #define CLK_CON_DIV_CLKCMU_IS_BUS		0x1854
64 #define CLK_CON_DIV_CLKCMU_IS_GDC		0x1858
65 #define CLK_CON_DIV_CLKCMU_IS_ITP		0x185c
66 #define CLK_CON_DIV_CLKCMU_IS_VRA		0x1860
67 #define CLK_CON_DIV_CLKCMU_MFCMSCL_JPEG		0x1864
68 #define CLK_CON_DIV_CLKCMU_MFCMSCL_M2M		0x1868
69 #define CLK_CON_DIV_CLKCMU_MFCMSCL_MCSC		0x186c
70 #define CLK_CON_DIV_CLKCMU_MFCMSCL_MFC		0x1870
71 #define CLK_CON_DIV_CLKCMU_PERI_BUS		0x187c
72 #define CLK_CON_DIV_CLKCMU_PERI_IP		0x1880
73 #define CLK_CON_DIV_CLKCMU_PERI_UART		0x1884
74 #define CLK_CON_DIV_PLL_SHARED0_DIV2		0x188c
75 #define CLK_CON_DIV_PLL_SHARED0_DIV3		0x1890
76 #define CLK_CON_DIV_PLL_SHARED0_DIV4		0x1894
77 #define CLK_CON_DIV_PLL_SHARED1_DIV2		0x1898
78 #define CLK_CON_DIV_PLL_SHARED1_DIV3		0x189c
79 #define CLK_CON_DIV_PLL_SHARED1_DIV4		0x18a0
80 #define CLK_CON_GAT_GATE_CLKCMU_APM_BUS		0x2008
81 #define CLK_CON_GAT_GATE_CLKCMU_AUD		0x200c
82 #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS	0x201c
83 #define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI	0x2020
84 #define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD	0x2024
85 #define CLK_CON_GAT_GATE_CLKCMU_CORE_SSS	0x2028
86 #define CLK_CON_GAT_GATE_CLKCMU_DPU		0x203c
87 #define CLK_CON_GAT_GATE_CLKCMU_HSI_BUS		0x2044
88 #define CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD	0x2048
89 #define CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD	0x204c
90 #define CLK_CON_GAT_GATE_CLKCMU_IS_BUS		0x2050
91 #define CLK_CON_GAT_GATE_CLKCMU_IS_GDC		0x2054
92 #define CLK_CON_GAT_GATE_CLKCMU_IS_ITP		0x2058
93 #define CLK_CON_GAT_GATE_CLKCMU_IS_VRA		0x205c
94 #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_JPEG	0x2060
95 #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_M2M	0x2064
96 #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MCSC	0x2068
97 #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC	0x206c
98 #define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS	0x2080
99 #define CLK_CON_GAT_GATE_CLKCMU_PERI_IP		0x2084
100 #define CLK_CON_GAT_GATE_CLKCMU_PERI_UART	0x2088
101 
102 static const unsigned long top_clk_regs[] __initconst = {
103 	PLL_LOCKTIME_PLL_MMC,
104 	PLL_LOCKTIME_PLL_SHARED0,
105 	PLL_LOCKTIME_PLL_SHARED1,
106 	PLL_CON0_PLL_MMC,
107 	PLL_CON3_PLL_MMC,
108 	PLL_CON0_PLL_SHARED0,
109 	PLL_CON3_PLL_SHARED0,
110 	PLL_CON0_PLL_SHARED1,
111 	PLL_CON3_PLL_SHARED1,
112 	CLK_CON_MUX_MUX_CLKCMU_APM_BUS,
113 	CLK_CON_MUX_MUX_CLKCMU_AUD,
114 	CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,
115 	CLK_CON_MUX_MUX_CLKCMU_CORE_CCI,
116 	CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD,
117 	CLK_CON_MUX_MUX_CLKCMU_CORE_SSS,
118 	CLK_CON_MUX_MUX_CLKCMU_DPU,
119 	CLK_CON_MUX_MUX_CLKCMU_HSI_BUS,
120 	CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD,
121 	CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD,
122 	CLK_CON_MUX_MUX_CLKCMU_IS_BUS,
123 	CLK_CON_MUX_MUX_CLKCMU_IS_GDC,
124 	CLK_CON_MUX_MUX_CLKCMU_IS_ITP,
125 	CLK_CON_MUX_MUX_CLKCMU_IS_VRA,
126 	CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_JPEG,
127 	CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_M2M,
128 	CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MCSC,
129 	CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC,
130 	CLK_CON_MUX_MUX_CLKCMU_PERI_BUS,
131 	CLK_CON_MUX_MUX_CLKCMU_PERI_IP,
132 	CLK_CON_MUX_MUX_CLKCMU_PERI_UART,
133 	CLK_CON_DIV_CLKCMU_APM_BUS,
134 	CLK_CON_DIV_CLKCMU_AUD,
135 	CLK_CON_DIV_CLKCMU_CORE_BUS,
136 	CLK_CON_DIV_CLKCMU_CORE_CCI,
137 	CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD,
138 	CLK_CON_DIV_CLKCMU_CORE_SSS,
139 	CLK_CON_DIV_CLKCMU_DPU,
140 	CLK_CON_DIV_CLKCMU_HSI_BUS,
141 	CLK_CON_DIV_CLKCMU_HSI_MMC_CARD,
142 	CLK_CON_DIV_CLKCMU_HSI_USB20DRD,
143 	CLK_CON_DIV_CLKCMU_IS_BUS,
144 	CLK_CON_DIV_CLKCMU_IS_GDC,
145 	CLK_CON_DIV_CLKCMU_IS_ITP,
146 	CLK_CON_DIV_CLKCMU_IS_VRA,
147 	CLK_CON_DIV_CLKCMU_MFCMSCL_JPEG,
148 	CLK_CON_DIV_CLKCMU_MFCMSCL_M2M,
149 	CLK_CON_DIV_CLKCMU_MFCMSCL_MCSC,
150 	CLK_CON_DIV_CLKCMU_MFCMSCL_MFC,
151 	CLK_CON_DIV_CLKCMU_PERI_BUS,
152 	CLK_CON_DIV_CLKCMU_PERI_IP,
153 	CLK_CON_DIV_CLKCMU_PERI_UART,
154 	CLK_CON_DIV_PLL_SHARED0_DIV2,
155 	CLK_CON_DIV_PLL_SHARED0_DIV3,
156 	CLK_CON_DIV_PLL_SHARED0_DIV4,
157 	CLK_CON_DIV_PLL_SHARED1_DIV2,
158 	CLK_CON_DIV_PLL_SHARED1_DIV3,
159 	CLK_CON_DIV_PLL_SHARED1_DIV4,
160 	CLK_CON_GAT_GATE_CLKCMU_APM_BUS,
161 	CLK_CON_GAT_GATE_CLKCMU_AUD,
162 	CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
163 	CLK_CON_GAT_GATE_CLKCMU_CORE_CCI,
164 	CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD,
165 	CLK_CON_GAT_GATE_CLKCMU_CORE_SSS,
166 	CLK_CON_GAT_GATE_CLKCMU_DPU,
167 	CLK_CON_GAT_GATE_CLKCMU_HSI_BUS,
168 	CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD,
169 	CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD,
170 	CLK_CON_GAT_GATE_CLKCMU_IS_BUS,
171 	CLK_CON_GAT_GATE_CLKCMU_IS_GDC,
172 	CLK_CON_GAT_GATE_CLKCMU_IS_ITP,
173 	CLK_CON_GAT_GATE_CLKCMU_IS_VRA,
174 	CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_JPEG,
175 	CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_M2M,
176 	CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MCSC,
177 	CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC,
178 	CLK_CON_GAT_GATE_CLKCMU_PERI_BUS,
179 	CLK_CON_GAT_GATE_CLKCMU_PERI_IP,
180 	CLK_CON_GAT_GATE_CLKCMU_PERI_UART,
181 };
182 
183 /*
184  * Do not provide PLL tables to core PLLs, as MANUAL_PLL_CTRL bit is not set
185  * for those PLLs by default, so set_rate operation would fail.
186  */
187 static const struct samsung_pll_clock top_pll_clks[] __initconst = {
188 	/* CMU_TOP_PURECLKCOMP */
189 	PLL(pll_0822x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
190 	    PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0,
191 	    NULL),
192 	PLL(pll_0822x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
193 	    PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1,
194 	    NULL),
195 	PLL(pll_0831x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "oscclk",
196 	    PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL),
197 };
198 
199 /* List of parent clocks for Muxes in CMU_TOP */
200 PNAME(mout_shared0_pll_p)	= { "oscclk", "fout_shared0_pll" };
201 PNAME(mout_shared1_pll_p)	= { "oscclk", "fout_shared1_pll" };
202 PNAME(mout_mmc_pll_p)		= { "oscclk", "fout_mmc_pll" };
203 /* List of parent clocks for Muxes in CMU_TOP: for CMU_APM */
204 PNAME(mout_clkcmu_apm_bus_p)	= { "dout_shared0_div4", "pll_shared1_div4" };
205 /* List of parent clocks for Muxes in CMU_TOP: for CMU_AUD */
206 PNAME(mout_aud_p)		= { "fout_shared1_pll", "dout_shared0_div2",
207 				    "dout_shared1_div2", "dout_shared0_div3" };
208 /* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */
209 PNAME(mout_core_bus_p)		= { "dout_shared1_div2", "dout_shared0_div3",
210 				    "dout_shared1_div3", "dout_shared0_div4" };
211 PNAME(mout_core_cci_p)		= { "dout_shared0_div2", "dout_shared1_div2",
212 				    "dout_shared0_div3", "dout_shared1_div3" };
213 PNAME(mout_core_mmc_embd_p)	= { "oscclk", "dout_shared0_div2",
214 				    "dout_shared1_div2", "dout_shared0_div3",
215 				    "dout_shared1_div3", "mout_mmc_pll",
216 				    "oscclk", "oscclk" };
217 PNAME(mout_core_sss_p)		= { "dout_shared0_div3", "dout_shared1_div3",
218 				    "dout_shared0_div4", "dout_shared1_div4" };
219 /* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI */
220 PNAME(mout_hsi_bus_p)		= { "dout_shared0_div2", "dout_shared1_div2" };
221 PNAME(mout_hsi_mmc_card_p)	= { "oscclk", "dout_shared0_div2",
222 				    "dout_shared1_div2", "dout_shared0_div3",
223 				    "dout_shared1_div3", "mout_mmc_pll",
224 				    "oscclk", "oscclk" };
225 PNAME(mout_hsi_usb20drd_p)	= { "oscclk", "dout_shared0_div4",
226 				    "dout_shared1_div4", "oscclk" };
227 /* List of parent clocks for Muxes in CMU_TOP: for CMU_IS */
228 PNAME(mout_is_bus_p)		= { "dout_shared0_div2", "dout_shared1_div2",
229 				    "dout_shared0_div3", "dout_shared1_div3" };
230 PNAME(mout_is_itp_p)		= { "dout_shared0_div2", "dout_shared1_div2",
231 				    "dout_shared0_div3", "dout_shared1_div3" };
232 PNAME(mout_is_vra_p)		= { "dout_shared0_div2", "dout_shared1_div2",
233 				    "dout_shared0_div3", "dout_shared1_div3" };
234 PNAME(mout_is_gdc_p)		= { "dout_shared0_div2", "dout_shared1_div2",
235 				    "dout_shared0_div3", "dout_shared1_div3" };
236 /* List of parent clocks for Muxes in CMU_TOP: for CMU_MFCMSCL */
237 PNAME(mout_mfcmscl_mfc_p)	= { "dout_shared1_div2", "dout_shared0_div3",
238 				    "dout_shared1_div3", "dout_shared0_div4" };
239 PNAME(mout_mfcmscl_m2m_p)	= { "dout_shared1_div2", "dout_shared0_div3",
240 				    "dout_shared1_div3", "dout_shared0_div4" };
241 PNAME(mout_mfcmscl_mcsc_p)	= { "dout_shared1_div2", "dout_shared0_div3",
242 				    "dout_shared1_div3", "dout_shared0_div4" };
243 PNAME(mout_mfcmscl_jpeg_p)	= { "dout_shared0_div3", "dout_shared1_div3",
244 				    "dout_shared0_div4", "dout_shared1_div4" };
245 /* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */
246 PNAME(mout_peri_bus_p)		= { "dout_shared0_div4", "dout_shared1_div4" };
247 PNAME(mout_peri_uart_p)		= { "oscclk", "dout_shared0_div4",
248 				    "dout_shared1_div4", "oscclk" };
249 PNAME(mout_peri_ip_p)		= { "oscclk", "dout_shared0_div4",
250 				    "dout_shared1_div4", "oscclk" };
251 /* List of parent clocks for Muxes in CMU_TOP: for CMU_DPU */
252 PNAME(mout_dpu_p)		= { "dout_shared0_div3", "dout_shared1_div3",
253 				    "dout_shared0_div4", "dout_shared1_div4" };
254 
255 static const struct samsung_mux_clock top_mux_clks[] __initconst = {
256 	/* CMU_TOP_PURECLKCOMP */
257 	MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p,
258 	    PLL_CON0_PLL_SHARED0, 4, 1),
259 	MUX(CLK_MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p,
260 	    PLL_CON0_PLL_SHARED1, 4, 1),
261 	MUX(CLK_MOUT_MMC_PLL, "mout_mmc_pll", mout_mmc_pll_p,
262 	    PLL_CON0_PLL_MMC, 4, 1),
263 
264 	/* APM */
265 	MUX(CLK_MOUT_CLKCMU_APM_BUS, "mout_clkcmu_apm_bus",
266 	    mout_clkcmu_apm_bus_p, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 1),
267 
268 	/* AUD */
269 	MUX(CLK_MOUT_AUD, "mout_aud", mout_aud_p,
270 	    CLK_CON_MUX_MUX_CLKCMU_AUD, 0, 2),
271 
272 	/* CORE */
273 	MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p,
274 	    CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
275 	MUX(CLK_MOUT_CORE_CCI, "mout_core_cci", mout_core_cci_p,
276 	    CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 0, 2),
277 	MUX(CLK_MOUT_CORE_MMC_EMBD, "mout_core_mmc_embd", mout_core_mmc_embd_p,
278 	    CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD, 0, 3),
279 	MUX(CLK_MOUT_CORE_SSS, "mout_core_sss", mout_core_sss_p,
280 	    CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, 0, 2),
281 
282 	/* DPU */
283 	MUX(CLK_MOUT_DPU, "mout_dpu", mout_dpu_p,
284 	    CLK_CON_MUX_MUX_CLKCMU_DPU, 0, 2),
285 
286 	/* HSI */
287 	MUX(CLK_MOUT_HSI_BUS, "mout_hsi_bus", mout_hsi_bus_p,
288 	    CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, 0, 1),
289 	MUX(CLK_MOUT_HSI_MMC_CARD, "mout_hsi_mmc_card", mout_hsi_mmc_card_p,
290 	    CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD, 0, 3),
291 	MUX(CLK_MOUT_HSI_USB20DRD, "mout_hsi_usb20drd", mout_hsi_usb20drd_p,
292 	    CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD, 0, 2),
293 
294 	/* IS */
295 	MUX(CLK_MOUT_IS_BUS, "mout_is_bus", mout_is_bus_p,
296 	    CLK_CON_MUX_MUX_CLKCMU_IS_BUS, 0, 2),
297 	MUX(CLK_MOUT_IS_ITP, "mout_is_itp", mout_is_itp_p,
298 	    CLK_CON_MUX_MUX_CLKCMU_IS_ITP, 0, 2),
299 	MUX(CLK_MOUT_IS_VRA, "mout_is_vra", mout_is_vra_p,
300 	    CLK_CON_MUX_MUX_CLKCMU_IS_VRA, 0, 2),
301 	MUX(CLK_MOUT_IS_GDC, "mout_is_gdc", mout_is_gdc_p,
302 	    CLK_CON_MUX_MUX_CLKCMU_IS_GDC, 0, 2),
303 
304 	/* MFCMSCL */
305 	MUX(CLK_MOUT_MFCMSCL_MFC, "mout_mfcmscl_mfc", mout_mfcmscl_mfc_p,
306 	    CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC, 0, 2),
307 	MUX(CLK_MOUT_MFCMSCL_M2M, "mout_mfcmscl_m2m", mout_mfcmscl_m2m_p,
308 	    CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_M2M, 0, 2),
309 	MUX(CLK_MOUT_MFCMSCL_MCSC, "mout_mfcmscl_mcsc", mout_mfcmscl_mcsc_p,
310 	    CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MCSC, 0, 2),
311 	MUX(CLK_MOUT_MFCMSCL_JPEG, "mout_mfcmscl_jpeg", mout_mfcmscl_jpeg_p,
312 	    CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_JPEG, 0, 2),
313 
314 	/* PERI */
315 	MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p,
316 	    CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1),
317 	MUX(CLK_MOUT_PERI_UART, "mout_peri_uart", mout_peri_uart_p,
318 	    CLK_CON_MUX_MUX_CLKCMU_PERI_UART, 0, 2),
319 	MUX(CLK_MOUT_PERI_IP, "mout_peri_ip", mout_peri_ip_p,
320 	    CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 0, 2),
321 };
322 
323 static const struct samsung_div_clock top_div_clks[] __initconst = {
324 	/* CMU_TOP_PURECLKCOMP */
325 	DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll",
326 	    CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
327 	DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "mout_shared0_pll",
328 	    CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
329 	DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "mout_shared1_pll",
330 	    CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
331 	DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "mout_shared1_pll",
332 	    CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
333 	DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2",
334 	    CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
335 	DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2",
336 	    CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
337 
338 	/* APM */
339 	DIV(CLK_DOUT_CLKCMU_APM_BUS, "dout_clkcmu_apm_bus",
340 	    "gout_clkcmu_apm_bus", CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3),
341 
342 	/* AUD */
343 	DIV(CLK_DOUT_AUD, "dout_aud", "gout_aud",
344 	    CLK_CON_DIV_CLKCMU_AUD, 0, 4),
345 
346 	/* CORE */
347 	DIV(CLK_DOUT_CORE_BUS, "dout_core_bus", "gout_core_bus",
348 	    CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
349 	DIV(CLK_DOUT_CORE_CCI, "dout_core_cci", "gout_core_cci",
350 	    CLK_CON_DIV_CLKCMU_CORE_CCI, 0, 4),
351 	DIV(CLK_DOUT_CORE_MMC_EMBD, "dout_core_mmc_embd", "gout_core_mmc_embd",
352 	    CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD, 0, 9),
353 	DIV(CLK_DOUT_CORE_SSS, "dout_core_sss", "gout_core_sss",
354 	    CLK_CON_DIV_CLKCMU_CORE_SSS, 0, 4),
355 
356 	/* DPU */
357 	DIV(CLK_DOUT_DPU, "dout_dpu", "gout_dpu",
358 	    CLK_CON_DIV_CLKCMU_DPU, 0, 4),
359 
360 	/* HSI */
361 	DIV(CLK_DOUT_HSI_BUS, "dout_hsi_bus", "gout_hsi_bus",
362 	    CLK_CON_DIV_CLKCMU_HSI_BUS, 0, 4),
363 	DIV(CLK_DOUT_HSI_MMC_CARD, "dout_hsi_mmc_card", "gout_hsi_mmc_card",
364 	    CLK_CON_DIV_CLKCMU_HSI_MMC_CARD, 0, 9),
365 	DIV(CLK_DOUT_HSI_USB20DRD, "dout_hsi_usb20drd", "gout_hsi_usb20drd",
366 	    CLK_CON_DIV_CLKCMU_HSI_USB20DRD, 0, 4),
367 
368 	/* IS */
369 	DIV(CLK_DOUT_IS_BUS, "dout_is_bus", "gout_is_bus",
370 	    CLK_CON_DIV_CLKCMU_IS_BUS, 0, 4),
371 	DIV(CLK_DOUT_IS_ITP, "dout_is_itp", "gout_is_itp",
372 	    CLK_CON_DIV_CLKCMU_IS_ITP, 0, 4),
373 	DIV(CLK_DOUT_IS_VRA, "dout_is_vra", "gout_is_vra",
374 	    CLK_CON_DIV_CLKCMU_IS_VRA, 0, 4),
375 	DIV(CLK_DOUT_IS_GDC, "dout_is_gdc", "gout_is_gdc",
376 	    CLK_CON_DIV_CLKCMU_IS_GDC, 0, 4),
377 
378 	/* MFCMSCL */
379 	DIV(CLK_DOUT_MFCMSCL_MFC, "dout_mfcmscl_mfc", "gout_mfcmscl_mfc",
380 	    CLK_CON_DIV_CLKCMU_MFCMSCL_MFC, 0, 4),
381 	DIV(CLK_DOUT_MFCMSCL_M2M, "dout_mfcmscl_m2m", "gout_mfcmscl_m2m",
382 	    CLK_CON_DIV_CLKCMU_MFCMSCL_M2M, 0, 4),
383 	DIV(CLK_DOUT_MFCMSCL_MCSC, "dout_mfcmscl_mcsc", "gout_mfcmscl_mcsc",
384 	    CLK_CON_DIV_CLKCMU_MFCMSCL_MCSC, 0, 4),
385 	DIV(CLK_DOUT_MFCMSCL_JPEG, "dout_mfcmscl_jpeg", "gout_mfcmscl_jpeg",
386 	    CLK_CON_DIV_CLKCMU_MFCMSCL_JPEG, 0, 4),
387 
388 	/* PERI */
389 	DIV(CLK_DOUT_PERI_BUS, "dout_peri_bus", "gout_peri_bus",
390 	    CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4),
391 	DIV(CLK_DOUT_PERI_UART, "dout_peri_uart", "gout_peri_uart",
392 	    CLK_CON_DIV_CLKCMU_PERI_UART, 0, 4),
393 	DIV(CLK_DOUT_PERI_IP, "dout_peri_ip", "gout_peri_ip",
394 	    CLK_CON_DIV_CLKCMU_PERI_IP, 0, 4),
395 };
396 
397 static const struct samsung_gate_clock top_gate_clks[] __initconst = {
398 	/* CORE */
399 	GATE(CLK_GOUT_CORE_BUS, "gout_core_bus", "mout_core_bus",
400 	     CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0),
401 	GATE(CLK_GOUT_CORE_CCI, "gout_core_cci", "mout_core_cci",
402 	     CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 21, 0, 0),
403 	GATE(CLK_GOUT_CORE_MMC_EMBD, "gout_core_mmc_embd", "mout_core_mmc_embd",
404 	     CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD, 21, 0, 0),
405 	GATE(CLK_GOUT_CORE_SSS, "gout_core_sss", "mout_core_sss",
406 	     CLK_CON_GAT_GATE_CLKCMU_CORE_SSS, 21, 0, 0),
407 
408 	/* APM */
409 	GATE(CLK_GOUT_CLKCMU_APM_BUS, "gout_clkcmu_apm_bus",
410 	     "mout_clkcmu_apm_bus", CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 21, 0, 0),
411 
412 	/* AUD */
413 	GATE(CLK_GOUT_AUD, "gout_aud", "mout_aud",
414 	     CLK_CON_GAT_GATE_CLKCMU_AUD, 21, 0, 0),
415 
416 	/* DPU */
417 	GATE(CLK_GOUT_DPU, "gout_dpu", "mout_dpu",
418 	     CLK_CON_GAT_GATE_CLKCMU_DPU, 21, 0, 0),
419 
420 	/* HSI */
421 	GATE(CLK_GOUT_HSI_BUS, "gout_hsi_bus", "mout_hsi_bus",
422 	     CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, 21, 0, 0),
423 	GATE(CLK_GOUT_HSI_MMC_CARD, "gout_hsi_mmc_card", "mout_hsi_mmc_card",
424 	     CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD, 21, 0, 0),
425 	GATE(CLK_GOUT_HSI_USB20DRD, "gout_hsi_usb20drd", "mout_hsi_usb20drd",
426 	     CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD, 21, 0, 0),
427 
428 	/* IS */
429 	/* TODO: These clocks have to be always enabled to access CMU_IS regs */
430 	GATE(CLK_GOUT_IS_BUS, "gout_is_bus", "mout_is_bus",
431 	     CLK_CON_GAT_GATE_CLKCMU_IS_BUS, 21, CLK_IS_CRITICAL, 0),
432 	GATE(CLK_GOUT_IS_ITP, "gout_is_itp", "mout_is_itp",
433 	     CLK_CON_GAT_GATE_CLKCMU_IS_ITP, 21, CLK_IS_CRITICAL, 0),
434 	GATE(CLK_GOUT_IS_VRA, "gout_is_vra", "mout_is_vra",
435 	     CLK_CON_GAT_GATE_CLKCMU_IS_VRA, 21, CLK_IS_CRITICAL, 0),
436 	GATE(CLK_GOUT_IS_GDC, "gout_is_gdc", "mout_is_gdc",
437 	     CLK_CON_GAT_GATE_CLKCMU_IS_GDC, 21, CLK_IS_CRITICAL, 0),
438 
439 	/* MFCMSCL */
440 	/* TODO: These have to be always enabled to access CMU_MFCMSCL regs */
441 	GATE(CLK_GOUT_MFCMSCL_MFC, "gout_mfcmscl_mfc", "mout_mfcmscl_mfc",
442 	     CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC, 21, CLK_IS_CRITICAL, 0),
443 	GATE(CLK_GOUT_MFCMSCL_M2M, "gout_mfcmscl_m2m", "mout_mfcmscl_m2m",
444 	     CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_M2M, 21, CLK_IS_CRITICAL, 0),
445 	GATE(CLK_GOUT_MFCMSCL_MCSC, "gout_mfcmscl_mcsc", "mout_mfcmscl_mcsc",
446 	     CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MCSC, 21, CLK_IS_CRITICAL, 0),
447 	GATE(CLK_GOUT_MFCMSCL_JPEG, "gout_mfcmscl_jpeg", "mout_mfcmscl_jpeg",
448 	     CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_JPEG, 21, CLK_IS_CRITICAL, 0),
449 
450 	/* PERI */
451 	GATE(CLK_GOUT_PERI_BUS, "gout_peri_bus", "mout_peri_bus",
452 	     CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 21, 0, 0),
453 	GATE(CLK_GOUT_PERI_UART, "gout_peri_uart", "mout_peri_uart",
454 	     CLK_CON_GAT_GATE_CLKCMU_PERI_UART, 21, 0, 0),
455 	GATE(CLK_GOUT_PERI_IP, "gout_peri_ip", "mout_peri_ip",
456 	     CLK_CON_GAT_GATE_CLKCMU_PERI_IP, 21, 0, 0),
457 };
458 
459 static const struct samsung_cmu_info top_cmu_info __initconst = {
460 	.pll_clks		= top_pll_clks,
461 	.nr_pll_clks		= ARRAY_SIZE(top_pll_clks),
462 	.mux_clks		= top_mux_clks,
463 	.nr_mux_clks		= ARRAY_SIZE(top_mux_clks),
464 	.div_clks		= top_div_clks,
465 	.nr_div_clks		= ARRAY_SIZE(top_div_clks),
466 	.gate_clks		= top_gate_clks,
467 	.nr_gate_clks		= ARRAY_SIZE(top_gate_clks),
468 	.nr_clk_ids		= TOP_NR_CLK,
469 	.clk_regs		= top_clk_regs,
470 	.nr_clk_regs		= ARRAY_SIZE(top_clk_regs),
471 };
472 
473 static void __init exynos850_cmu_top_init(struct device_node *np)
474 {
475 	exynos_arm64_register_cmu(NULL, np, &top_cmu_info);
476 }
477 
478 /* Register CMU_TOP early, as it's a dependency for other early domains */
479 CLK_OF_DECLARE(exynos850_cmu_top, "samsung,exynos850-cmu-top",
480 	       exynos850_cmu_top_init);
481 
482 /* ---- CMU_APM ------------------------------------------------------------- */
483 
484 /* Register Offset definitions for CMU_APM (0x11800000) */
485 #define PLL_CON0_MUX_CLKCMU_APM_BUS_USER		0x0600
486 #define PLL_CON0_MUX_CLK_RCO_APM_I3C_USER		0x0610
487 #define PLL_CON0_MUX_CLK_RCO_APM_USER			0x0620
488 #define PLL_CON0_MUX_DLL_USER				0x0630
489 #define CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS			0x1000
490 #define CLK_CON_MUX_MUX_CLK_APM_BUS			0x1004
491 #define CLK_CON_MUX_MUX_CLK_APM_I3C			0x1008
492 #define CLK_CON_DIV_CLKCMU_CHUB_BUS			0x1800
493 #define CLK_CON_DIV_DIV_CLK_APM_BUS			0x1804
494 #define CLK_CON_DIV_DIV_CLK_APM_I3C			0x1808
495 #define CLK_CON_GAT_CLKCMU_CMGP_BUS			0x2000
496 #define CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS		0x2014
497 #define CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK	0x2018
498 #define CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK	0x2020
499 #define CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK		0x2024
500 #define CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK		0x2028
501 #define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK	0x2034
502 #define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK	0x2038
503 #define CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK		0x20bc
504 #define CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK		0x20c0
505 
506 static const unsigned long apm_clk_regs[] __initconst = {
507 	PLL_CON0_MUX_CLKCMU_APM_BUS_USER,
508 	PLL_CON0_MUX_CLK_RCO_APM_I3C_USER,
509 	PLL_CON0_MUX_CLK_RCO_APM_USER,
510 	PLL_CON0_MUX_DLL_USER,
511 	CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS,
512 	CLK_CON_MUX_MUX_CLK_APM_BUS,
513 	CLK_CON_MUX_MUX_CLK_APM_I3C,
514 	CLK_CON_DIV_CLKCMU_CHUB_BUS,
515 	CLK_CON_DIV_DIV_CLK_APM_BUS,
516 	CLK_CON_DIV_DIV_CLK_APM_I3C,
517 	CLK_CON_GAT_CLKCMU_CMGP_BUS,
518 	CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS,
519 	CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK,
520 	CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK,
521 	CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK,
522 	CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK,
523 	CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK,
524 	CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK,
525 	CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK,
526 	CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK,
527 };
528 
529 /* List of parent clocks for Muxes in CMU_APM */
530 PNAME(mout_apm_bus_user_p)	= { "oscclk_rco_apm", "dout_clkcmu_apm_bus" };
531 PNAME(mout_rco_apm_i3c_user_p)	= { "oscclk_rco_apm", "clk_rco_i3c_pmic" };
532 PNAME(mout_rco_apm_user_p)	= { "oscclk_rco_apm", "clk_rco_apm__alv" };
533 PNAME(mout_dll_user_p)		= { "oscclk_rco_apm", "clk_dll_dco" };
534 PNAME(mout_clkcmu_chub_bus_p)	= { "mout_apm_bus_user", "mout_dll_user" };
535 PNAME(mout_apm_bus_p)		= { "mout_rco_apm_user", "mout_apm_bus_user",
536 				    "mout_dll_user", "oscclk_rco_apm" };
537 PNAME(mout_apm_i3c_p)		= { "dout_apm_i3c", "mout_rco_apm_i3c_user" };
538 
539 static const struct samsung_fixed_rate_clock apm_fixed_clks[] __initconst = {
540 	FRATE(CLK_RCO_I3C_PMIC, "clk_rco_i3c_pmic", NULL, 0, 491520000),
541 	FRATE(OSCCLK_RCO_APM, "oscclk_rco_apm", NULL, 0, 24576000),
542 	FRATE(CLK_RCO_APM__ALV, "clk_rco_apm__alv", NULL, 0, 49152000),
543 	FRATE(CLK_DLL_DCO, "clk_dll_dco", NULL, 0, 360000000),
544 };
545 
546 static const struct samsung_mux_clock apm_mux_clks[] __initconst = {
547 	MUX(CLK_MOUT_APM_BUS_USER, "mout_apm_bus_user", mout_apm_bus_user_p,
548 	    PLL_CON0_MUX_CLKCMU_APM_BUS_USER, 4, 1),
549 	MUX(CLK_MOUT_RCO_APM_I3C_USER, "mout_rco_apm_i3c_user",
550 	    mout_rco_apm_i3c_user_p, PLL_CON0_MUX_CLK_RCO_APM_I3C_USER, 4, 1),
551 	MUX(CLK_MOUT_RCO_APM_USER, "mout_rco_apm_user", mout_rco_apm_user_p,
552 	    PLL_CON0_MUX_CLK_RCO_APM_USER, 4, 1),
553 	MUX(CLK_MOUT_DLL_USER, "mout_dll_user", mout_dll_user_p,
554 	    PLL_CON0_MUX_DLL_USER, 4, 1),
555 	MUX(CLK_MOUT_CLKCMU_CHUB_BUS, "mout_clkcmu_chub_bus",
556 	    mout_clkcmu_chub_bus_p, CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS, 0, 1),
557 	MUX(CLK_MOUT_APM_BUS, "mout_apm_bus", mout_apm_bus_p,
558 	    CLK_CON_MUX_MUX_CLK_APM_BUS, 0, 2),
559 	MUX(CLK_MOUT_APM_I3C, "mout_apm_i3c", mout_apm_i3c_p,
560 	    CLK_CON_MUX_MUX_CLK_APM_I3C, 0, 1),
561 };
562 
563 static const struct samsung_div_clock apm_div_clks[] __initconst = {
564 	DIV(CLK_DOUT_CLKCMU_CHUB_BUS, "dout_clkcmu_chub_bus",
565 	    "gout_clkcmu_chub_bus",
566 	    CLK_CON_DIV_CLKCMU_CHUB_BUS, 0, 3),
567 	DIV(CLK_DOUT_APM_BUS, "dout_apm_bus", "mout_apm_bus",
568 	    CLK_CON_DIV_DIV_CLK_APM_BUS, 0, 3),
569 	DIV(CLK_DOUT_APM_I3C, "dout_apm_i3c", "mout_apm_bus",
570 	    CLK_CON_DIV_DIV_CLK_APM_I3C, 0, 3),
571 };
572 
573 static const struct samsung_gate_clock apm_gate_clks[] __initconst = {
574 	GATE(CLK_GOUT_CLKCMU_CMGP_BUS, "gout_clkcmu_cmgp_bus", "dout_apm_bus",
575 	     CLK_CON_GAT_CLKCMU_CMGP_BUS, 21, 0, 0),
576 	GATE(CLK_GOUT_CLKCMU_CHUB_BUS, "gout_clkcmu_chub_bus",
577 	     "mout_clkcmu_chub_bus",
578 	     CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS, 21, 0, 0),
579 	GATE(CLK_GOUT_RTC_PCLK, "gout_rtc_pclk", "dout_apm_bus",
580 	     CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK, 21, 0, 0),
581 	GATE(CLK_GOUT_TOP_RTC_PCLK, "gout_top_rtc_pclk", "dout_apm_bus",
582 	     CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK, 21, 0, 0),
583 	GATE(CLK_GOUT_I3C_PCLK, "gout_i3c_pclk", "dout_apm_bus",
584 	     CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK, 21, 0, 0),
585 	GATE(CLK_GOUT_I3C_SCLK, "gout_i3c_sclk", "mout_apm_i3c",
586 	     CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK, 21, 0, 0),
587 	GATE(CLK_GOUT_SPEEDY_PCLK, "gout_speedy_pclk", "dout_apm_bus",
588 	     CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK, 21, 0, 0),
589 	/* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
590 	GATE(CLK_GOUT_GPIO_ALIVE_PCLK, "gout_gpio_alive_pclk", "dout_apm_bus",
591 	     CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK, 21, CLK_IGNORE_UNUSED,
592 	     0),
593 	GATE(CLK_GOUT_PMU_ALIVE_PCLK, "gout_pmu_alive_pclk", "dout_apm_bus",
594 	     CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK, 21, 0, 0),
595 	GATE(CLK_GOUT_SYSREG_APM_PCLK, "gout_sysreg_apm_pclk", "dout_apm_bus",
596 	     CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK, 21, 0, 0),
597 };
598 
599 static const struct samsung_cmu_info apm_cmu_info __initconst = {
600 	.mux_clks		= apm_mux_clks,
601 	.nr_mux_clks		= ARRAY_SIZE(apm_mux_clks),
602 	.div_clks		= apm_div_clks,
603 	.nr_div_clks		= ARRAY_SIZE(apm_div_clks),
604 	.gate_clks		= apm_gate_clks,
605 	.nr_gate_clks		= ARRAY_SIZE(apm_gate_clks),
606 	.fixed_clks		= apm_fixed_clks,
607 	.nr_fixed_clks		= ARRAY_SIZE(apm_fixed_clks),
608 	.nr_clk_ids		= APM_NR_CLK,
609 	.clk_regs		= apm_clk_regs,
610 	.nr_clk_regs		= ARRAY_SIZE(apm_clk_regs),
611 	.clk_name		= "dout_clkcmu_apm_bus",
612 };
613 
614 /* ---- CMU_AUD ------------------------------------------------------------- */
615 
616 #define PLL_LOCKTIME_PLL_AUD			0x0000
617 #define PLL_CON0_PLL_AUD			0x0100
618 #define PLL_CON3_PLL_AUD			0x010c
619 #define PLL_CON0_MUX_CLKCMU_AUD_CPU_USER	0x0600
620 #define PLL_CON0_MUX_TICK_USB_USER		0x0610
621 #define CLK_CON_MUX_MUX_CLK_AUD_CPU		0x1000
622 #define CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH		0x1004
623 #define CLK_CON_MUX_MUX_CLK_AUD_FM		0x1008
624 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF0		0x100c
625 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF1		0x1010
626 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF2		0x1014
627 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF3		0x1018
628 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF4		0x101c
629 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF5		0x1020
630 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF6		0x1024
631 #define CLK_CON_DIV_DIV_CLK_AUD_MCLK		0x1800
632 #define CLK_CON_DIV_DIV_CLK_AUD_AUDIF		0x1804
633 #define CLK_CON_DIV_DIV_CLK_AUD_BUSD		0x1808
634 #define CLK_CON_DIV_DIV_CLK_AUD_BUSP		0x180c
635 #define CLK_CON_DIV_DIV_CLK_AUD_CNT		0x1810
636 #define CLK_CON_DIV_DIV_CLK_AUD_CPU		0x1814
637 #define CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK	0x1818
638 #define CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG	0x181c
639 #define CLK_CON_DIV_DIV_CLK_AUD_FM		0x1820
640 #define CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY		0x1824
641 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF0		0x1828
642 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF1		0x182c
643 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF2		0x1830
644 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF3		0x1834
645 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF4		0x1838
646 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF5		0x183c
647 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF6		0x1840
648 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT	0x2000
649 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0	0x2004
650 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1	0x2008
651 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2	0x200c
652 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3	0x2010
653 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4	0x2014
654 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5	0x2018
655 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6	0x201c
656 #define CLK_CON_GAT_GOUT_AUD_ABOX_ACLK		0x2048
657 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY	0x204c
658 #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB	0x2050
659 #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32	0x2054
660 #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP	0x2058
661 #define CLK_CON_GAT_GOUT_AUD_CODEC_MCLK		0x206c
662 #define CLK_CON_GAT_GOUT_AUD_TZPC_PCLK		0x2070
663 #define CLK_CON_GAT_GOUT_AUD_GPIO_PCLK		0x2074
664 #define CLK_CON_GAT_GOUT_AUD_PPMU_ACLK		0x2088
665 #define CLK_CON_GAT_GOUT_AUD_PPMU_PCLK		0x208c
666 #define CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1	0x20b4
667 #define CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK	0x20b8
668 #define CLK_CON_GAT_GOUT_AUD_WDT_PCLK		0x20bc
669 
670 static const unsigned long aud_clk_regs[] __initconst = {
671 	PLL_LOCKTIME_PLL_AUD,
672 	PLL_CON0_PLL_AUD,
673 	PLL_CON3_PLL_AUD,
674 	PLL_CON0_MUX_CLKCMU_AUD_CPU_USER,
675 	PLL_CON0_MUX_TICK_USB_USER,
676 	CLK_CON_MUX_MUX_CLK_AUD_CPU,
677 	CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH,
678 	CLK_CON_MUX_MUX_CLK_AUD_FM,
679 	CLK_CON_MUX_MUX_CLK_AUD_UAIF0,
680 	CLK_CON_MUX_MUX_CLK_AUD_UAIF1,
681 	CLK_CON_MUX_MUX_CLK_AUD_UAIF2,
682 	CLK_CON_MUX_MUX_CLK_AUD_UAIF3,
683 	CLK_CON_MUX_MUX_CLK_AUD_UAIF4,
684 	CLK_CON_MUX_MUX_CLK_AUD_UAIF5,
685 	CLK_CON_MUX_MUX_CLK_AUD_UAIF6,
686 	CLK_CON_DIV_DIV_CLK_AUD_MCLK,
687 	CLK_CON_DIV_DIV_CLK_AUD_AUDIF,
688 	CLK_CON_DIV_DIV_CLK_AUD_BUSD,
689 	CLK_CON_DIV_DIV_CLK_AUD_BUSP,
690 	CLK_CON_DIV_DIV_CLK_AUD_CNT,
691 	CLK_CON_DIV_DIV_CLK_AUD_CPU,
692 	CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK,
693 	CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG,
694 	CLK_CON_DIV_DIV_CLK_AUD_FM,
695 	CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY,
696 	CLK_CON_DIV_DIV_CLK_AUD_UAIF0,
697 	CLK_CON_DIV_DIV_CLK_AUD_UAIF1,
698 	CLK_CON_DIV_DIV_CLK_AUD_UAIF2,
699 	CLK_CON_DIV_DIV_CLK_AUD_UAIF3,
700 	CLK_CON_DIV_DIV_CLK_AUD_UAIF4,
701 	CLK_CON_DIV_DIV_CLK_AUD_UAIF5,
702 	CLK_CON_DIV_DIV_CLK_AUD_UAIF6,
703 	CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT,
704 	CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0,
705 	CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1,
706 	CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2,
707 	CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3,
708 	CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4,
709 	CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5,
710 	CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6,
711 	CLK_CON_GAT_GOUT_AUD_ABOX_ACLK,
712 	CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY,
713 	CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB,
714 	CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32,
715 	CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP,
716 	CLK_CON_GAT_GOUT_AUD_CODEC_MCLK,
717 	CLK_CON_GAT_GOUT_AUD_TZPC_PCLK,
718 	CLK_CON_GAT_GOUT_AUD_GPIO_PCLK,
719 	CLK_CON_GAT_GOUT_AUD_PPMU_ACLK,
720 	CLK_CON_GAT_GOUT_AUD_PPMU_PCLK,
721 	CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1,
722 	CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK,
723 	CLK_CON_GAT_GOUT_AUD_WDT_PCLK,
724 };
725 
726 /* List of parent clocks for Muxes in CMU_AUD */
727 PNAME(mout_aud_pll_p)		= { "oscclk", "fout_aud_pll" };
728 PNAME(mout_aud_cpu_user_p)	= { "oscclk", "dout_aud" };
729 PNAME(mout_aud_cpu_p)		= { "dout_aud_cpu", "mout_aud_cpu_user" };
730 PNAME(mout_aud_cpu_hch_p)	= { "mout_aud_cpu", "oscclk" };
731 PNAME(mout_aud_uaif0_p)		= { "dout_aud_uaif0", "ioclk_audiocdclk0" };
732 PNAME(mout_aud_uaif1_p)		= { "dout_aud_uaif1", "ioclk_audiocdclk1" };
733 PNAME(mout_aud_uaif2_p)		= { "dout_aud_uaif2", "ioclk_audiocdclk2" };
734 PNAME(mout_aud_uaif3_p)		= { "dout_aud_uaif3", "ioclk_audiocdclk3" };
735 PNAME(mout_aud_uaif4_p)		= { "dout_aud_uaif4", "ioclk_audiocdclk4" };
736 PNAME(mout_aud_uaif5_p)		= { "dout_aud_uaif5", "ioclk_audiocdclk5" };
737 PNAME(mout_aud_uaif6_p)		= { "dout_aud_uaif6", "ioclk_audiocdclk6" };
738 PNAME(mout_aud_tick_usb_user_p)	= { "oscclk", "tick_usb" };
739 PNAME(mout_aud_fm_p)		= { "oscclk", "dout_aud_fm_spdy" };
740 
741 /*
742  * Do not provide PLL table to PLL_AUD, as MANUAL_PLL_CTRL bit is not set
743  * for that PLL by default, so set_rate operation would fail.
744  */
745 static const struct samsung_pll_clock aud_pll_clks[] __initconst = {
746 	PLL(pll_0831x, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk",
747 	    PLL_LOCKTIME_PLL_AUD, PLL_CON3_PLL_AUD, NULL),
748 };
749 
750 static const struct samsung_fixed_rate_clock aud_fixed_clks[] __initconst = {
751 	FRATE(IOCLK_AUDIOCDCLK0, "ioclk_audiocdclk0", NULL, 0, 25000000),
752 	FRATE(IOCLK_AUDIOCDCLK1, "ioclk_audiocdclk1", NULL, 0, 25000000),
753 	FRATE(IOCLK_AUDIOCDCLK2, "ioclk_audiocdclk2", NULL, 0, 25000000),
754 	FRATE(IOCLK_AUDIOCDCLK3, "ioclk_audiocdclk3", NULL, 0, 25000000),
755 	FRATE(IOCLK_AUDIOCDCLK4, "ioclk_audiocdclk4", NULL, 0, 25000000),
756 	FRATE(IOCLK_AUDIOCDCLK5, "ioclk_audiocdclk5", NULL, 0, 25000000),
757 	FRATE(IOCLK_AUDIOCDCLK6, "ioclk_audiocdclk6", NULL, 0, 25000000),
758 	FRATE(TICK_USB, "tick_usb", NULL, 0, 60000000),
759 };
760 
761 static const struct samsung_mux_clock aud_mux_clks[] __initconst = {
762 	MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p,
763 	    PLL_CON0_PLL_AUD, 4, 1),
764 	MUX(CLK_MOUT_AUD_CPU_USER, "mout_aud_cpu_user", mout_aud_cpu_user_p,
765 	    PLL_CON0_MUX_CLKCMU_AUD_CPU_USER, 4, 1),
766 	MUX(CLK_MOUT_AUD_TICK_USB_USER, "mout_aud_tick_usb_user",
767 	    mout_aud_tick_usb_user_p,
768 	    PLL_CON0_MUX_TICK_USB_USER, 4, 1),
769 	MUX(CLK_MOUT_AUD_CPU, "mout_aud_cpu", mout_aud_cpu_p,
770 	    CLK_CON_MUX_MUX_CLK_AUD_CPU, 0, 1),
771 	MUX(CLK_MOUT_AUD_CPU_HCH, "mout_aud_cpu_hch", mout_aud_cpu_hch_p,
772 	    CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH, 0, 1),
773 	MUX(CLK_MOUT_AUD_UAIF0, "mout_aud_uaif0", mout_aud_uaif0_p,
774 	    CLK_CON_MUX_MUX_CLK_AUD_UAIF0, 0, 1),
775 	MUX(CLK_MOUT_AUD_UAIF1, "mout_aud_uaif1", mout_aud_uaif1_p,
776 	    CLK_CON_MUX_MUX_CLK_AUD_UAIF1, 0, 1),
777 	MUX(CLK_MOUT_AUD_UAIF2, "mout_aud_uaif2", mout_aud_uaif2_p,
778 	    CLK_CON_MUX_MUX_CLK_AUD_UAIF2, 0, 1),
779 	MUX(CLK_MOUT_AUD_UAIF3, "mout_aud_uaif3", mout_aud_uaif3_p,
780 	    CLK_CON_MUX_MUX_CLK_AUD_UAIF3, 0, 1),
781 	MUX(CLK_MOUT_AUD_UAIF4, "mout_aud_uaif4", mout_aud_uaif4_p,
782 	    CLK_CON_MUX_MUX_CLK_AUD_UAIF4, 0, 1),
783 	MUX(CLK_MOUT_AUD_UAIF5, "mout_aud_uaif5", mout_aud_uaif5_p,
784 	    CLK_CON_MUX_MUX_CLK_AUD_UAIF5, 0, 1),
785 	MUX(CLK_MOUT_AUD_UAIF6, "mout_aud_uaif6", mout_aud_uaif6_p,
786 	    CLK_CON_MUX_MUX_CLK_AUD_UAIF6, 0, 1),
787 	MUX(CLK_MOUT_AUD_FM, "mout_aud_fm", mout_aud_fm_p,
788 	    CLK_CON_MUX_MUX_CLK_AUD_FM, 0, 1),
789 };
790 
791 static const struct samsung_div_clock aud_div_clks[] __initconst = {
792 	DIV(CLK_DOUT_AUD_CPU, "dout_aud_cpu", "mout_aud_pll",
793 	    CLK_CON_DIV_DIV_CLK_AUD_CPU, 0, 4),
794 	DIV(CLK_DOUT_AUD_BUSD, "dout_aud_busd", "mout_aud_pll",
795 	    CLK_CON_DIV_DIV_CLK_AUD_BUSD, 0, 4),
796 	DIV(CLK_DOUT_AUD_BUSP, "dout_aud_busp", "mout_aud_pll",
797 	    CLK_CON_DIV_DIV_CLK_AUD_BUSP, 0, 4),
798 	DIV(CLK_DOUT_AUD_AUDIF, "dout_aud_audif", "mout_aud_pll",
799 	    CLK_CON_DIV_DIV_CLK_AUD_AUDIF, 0, 9),
800 	DIV(CLK_DOUT_AUD_CPU_ACLK, "dout_aud_cpu_aclk", "mout_aud_cpu_hch",
801 	    CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK, 0, 3),
802 	DIV(CLK_DOUT_AUD_CPU_PCLKDBG, "dout_aud_cpu_pclkdbg",
803 	    "mout_aud_cpu_hch",
804 	    CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG, 0, 3),
805 	DIV(CLK_DOUT_AUD_MCLK, "dout_aud_mclk", "dout_aud_audif",
806 	    CLK_CON_DIV_DIV_CLK_AUD_MCLK, 0, 2),
807 	DIV(CLK_DOUT_AUD_CNT, "dout_aud_cnt", "dout_aud_audif",
808 	    CLK_CON_DIV_DIV_CLK_AUD_CNT, 0, 10),
809 	DIV(CLK_DOUT_AUD_UAIF0, "dout_aud_uaif0", "dout_aud_audif",
810 	    CLK_CON_DIV_DIV_CLK_AUD_UAIF0, 0, 10),
811 	DIV(CLK_DOUT_AUD_UAIF1, "dout_aud_uaif1", "dout_aud_audif",
812 	    CLK_CON_DIV_DIV_CLK_AUD_UAIF1, 0, 10),
813 	DIV(CLK_DOUT_AUD_UAIF2, "dout_aud_uaif2", "dout_aud_audif",
814 	    CLK_CON_DIV_DIV_CLK_AUD_UAIF2, 0, 10),
815 	DIV(CLK_DOUT_AUD_UAIF3, "dout_aud_uaif3", "dout_aud_audif",
816 	    CLK_CON_DIV_DIV_CLK_AUD_UAIF3, 0, 10),
817 	DIV(CLK_DOUT_AUD_UAIF4, "dout_aud_uaif4", "dout_aud_audif",
818 	    CLK_CON_DIV_DIV_CLK_AUD_UAIF4, 0, 10),
819 	DIV(CLK_DOUT_AUD_UAIF5, "dout_aud_uaif5", "dout_aud_audif",
820 	    CLK_CON_DIV_DIV_CLK_AUD_UAIF5, 0, 10),
821 	DIV(CLK_DOUT_AUD_UAIF6, "dout_aud_uaif6", "dout_aud_audif",
822 	    CLK_CON_DIV_DIV_CLK_AUD_UAIF6, 0, 10),
823 	DIV(CLK_DOUT_AUD_FM_SPDY, "dout_aud_fm_spdy", "mout_aud_tick_usb_user",
824 	    CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY, 0, 1),
825 	DIV(CLK_DOUT_AUD_FM, "dout_aud_fm", "mout_aud_fm",
826 	    CLK_CON_DIV_DIV_CLK_AUD_FM, 0, 10),
827 };
828 
829 static const struct samsung_gate_clock aud_gate_clks[] __initconst = {
830 	GATE(CLK_GOUT_AUD_CA32_CCLK, "gout_aud_ca32_cclk", "mout_aud_cpu_hch",
831 	     CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32, 21, 0, 0),
832 	GATE(CLK_GOUT_AUD_ASB_CCLK, "gout_aud_asb_cclk", "dout_aud_cpu_aclk",
833 	     CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB, 21, 0, 0),
834 	GATE(CLK_GOUT_AUD_DAP_CCLK, "gout_aud_dap_cclk", "dout_aud_cpu_pclkdbg",
835 	     CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP, 21, 0, 0),
836 	/* TODO: Should be enabled in ABOX driver (or made CLK_IS_CRITICAL) */
837 	GATE(CLK_GOUT_AUD_ABOX_ACLK, "gout_aud_abox_aclk", "dout_aud_busd",
838 	     CLK_CON_GAT_GOUT_AUD_ABOX_ACLK, 21, CLK_IGNORE_UNUSED, 0),
839 	GATE(CLK_GOUT_AUD_GPIO_PCLK, "gout_aud_gpio_pclk", "dout_aud_busd",
840 	     CLK_CON_GAT_GOUT_AUD_GPIO_PCLK, 21, 0, 0),
841 	GATE(CLK_GOUT_AUD_PPMU_ACLK, "gout_aud_ppmu_aclk", "dout_aud_busd",
842 	     CLK_CON_GAT_GOUT_AUD_PPMU_ACLK, 21, 0, 0),
843 	GATE(CLK_GOUT_AUD_PPMU_PCLK, "gout_aud_ppmu_pclk", "dout_aud_busd",
844 	     CLK_CON_GAT_GOUT_AUD_PPMU_PCLK, 21, 0, 0),
845 	GATE(CLK_GOUT_AUD_SYSMMU_CLK, "gout_aud_sysmmu_clk", "dout_aud_busd",
846 	     CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1, 21, 0, 0),
847 	GATE(CLK_GOUT_AUD_SYSREG_PCLK, "gout_aud_sysreg_pclk", "dout_aud_busd",
848 	     CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK, 21, 0, 0),
849 	GATE(CLK_GOUT_AUD_WDT_PCLK, "gout_aud_wdt_pclk", "dout_aud_busd",
850 	     CLK_CON_GAT_GOUT_AUD_WDT_PCLK, 21, 0, 0),
851 	GATE(CLK_GOUT_AUD_TZPC_PCLK, "gout_aud_tzpc_pclk", "dout_aud_busp",
852 	     CLK_CON_GAT_GOUT_AUD_TZPC_PCLK, 21, 0, 0),
853 	GATE(CLK_GOUT_AUD_CODEC_MCLK, "gout_aud_codec_mclk", "dout_aud_mclk",
854 	     CLK_CON_GAT_GOUT_AUD_CODEC_MCLK, 21, 0, 0),
855 	GATE(CLK_GOUT_AUD_CNT_BCLK, "gout_aud_cnt_bclk", "dout_aud_cnt",
856 	     CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT, 21, 0, 0),
857 	GATE(CLK_GOUT_AUD_UAIF0_BCLK, "gout_aud_uaif0_bclk", "mout_aud_uaif0",
858 	     CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0, 21, 0, 0),
859 	GATE(CLK_GOUT_AUD_UAIF1_BCLK, "gout_aud_uaif1_bclk", "mout_aud_uaif1",
860 	     CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1, 21, 0, 0),
861 	GATE(CLK_GOUT_AUD_UAIF2_BCLK, "gout_aud_uaif2_bclk", "mout_aud_uaif2",
862 	     CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2, 21, 0, 0),
863 	GATE(CLK_GOUT_AUD_UAIF3_BCLK, "gout_aud_uaif3_bclk", "mout_aud_uaif3",
864 	     CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3, 21, 0, 0),
865 	GATE(CLK_GOUT_AUD_UAIF4_BCLK, "gout_aud_uaif4_bclk", "mout_aud_uaif4",
866 	     CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4, 21, 0, 0),
867 	GATE(CLK_GOUT_AUD_UAIF5_BCLK, "gout_aud_uaif5_bclk", "mout_aud_uaif5",
868 	     CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5, 21, 0, 0),
869 	GATE(CLK_GOUT_AUD_UAIF6_BCLK, "gout_aud_uaif6_bclk", "mout_aud_uaif6",
870 	     CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6, 21, 0, 0),
871 	GATE(CLK_GOUT_AUD_SPDY_BCLK, "gout_aud_spdy_bclk", "dout_aud_fm",
872 	     CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY, 21, 0, 0),
873 };
874 
875 static const struct samsung_cmu_info aud_cmu_info __initconst = {
876 	.pll_clks		= aud_pll_clks,
877 	.nr_pll_clks		= ARRAY_SIZE(aud_pll_clks),
878 	.mux_clks		= aud_mux_clks,
879 	.nr_mux_clks		= ARRAY_SIZE(aud_mux_clks),
880 	.div_clks		= aud_div_clks,
881 	.nr_div_clks		= ARRAY_SIZE(aud_div_clks),
882 	.gate_clks		= aud_gate_clks,
883 	.nr_gate_clks		= ARRAY_SIZE(aud_gate_clks),
884 	.fixed_clks		= aud_fixed_clks,
885 	.nr_fixed_clks		= ARRAY_SIZE(aud_fixed_clks),
886 	.nr_clk_ids		= AUD_NR_CLK,
887 	.clk_regs		= aud_clk_regs,
888 	.nr_clk_regs		= ARRAY_SIZE(aud_clk_regs),
889 	.clk_name		= "dout_aud",
890 };
891 
892 /* ---- CMU_CMGP ------------------------------------------------------------ */
893 
894 /* Register Offset definitions for CMU_CMGP (0x11c00000) */
895 #define CLK_CON_MUX_CLK_CMGP_ADC		0x1000
896 #define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0	0x1004
897 #define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1	0x1008
898 #define CLK_CON_DIV_DIV_CLK_CMGP_ADC		0x1800
899 #define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0	0x1804
900 #define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1	0x1808
901 #define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0	0x200c
902 #define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1	0x2010
903 #define CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK		0x2018
904 #define CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK	0x2040
905 #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK	0x2044
906 #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK	0x2048
907 #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK	0x204c
908 #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK	0x2050
909 
910 static const unsigned long cmgp_clk_regs[] __initconst = {
911 	CLK_CON_MUX_CLK_CMGP_ADC,
912 	CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0,
913 	CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1,
914 	CLK_CON_DIV_DIV_CLK_CMGP_ADC,
915 	CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0,
916 	CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1,
917 	CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0,
918 	CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1,
919 	CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK,
920 	CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK,
921 	CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK,
922 	CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK,
923 	CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK,
924 	CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK,
925 };
926 
927 /* List of parent clocks for Muxes in CMU_CMGP */
928 PNAME(mout_cmgp_usi0_p)	= { "clk_rco_cmgp", "gout_clkcmu_cmgp_bus" };
929 PNAME(mout_cmgp_usi1_p)	= { "clk_rco_cmgp", "gout_clkcmu_cmgp_bus" };
930 PNAME(mout_cmgp_adc_p)	= { "oscclk", "dout_cmgp_adc" };
931 
932 static const struct samsung_fixed_rate_clock cmgp_fixed_clks[] __initconst = {
933 	FRATE(CLK_RCO_CMGP, "clk_rco_cmgp", NULL, 0, 49152000),
934 };
935 
936 static const struct samsung_mux_clock cmgp_mux_clks[] __initconst = {
937 	MUX(CLK_MOUT_CMGP_ADC, "mout_cmgp_adc", mout_cmgp_adc_p,
938 	    CLK_CON_MUX_CLK_CMGP_ADC, 0, 1),
939 	MUX(CLK_MOUT_CMGP_USI0, "mout_cmgp_usi0", mout_cmgp_usi0_p,
940 	    CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0, 0, 1),
941 	MUX(CLK_MOUT_CMGP_USI1, "mout_cmgp_usi1", mout_cmgp_usi1_p,
942 	    CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1, 0, 1),
943 };
944 
945 static const struct samsung_div_clock cmgp_div_clks[] __initconst = {
946 	DIV(CLK_DOUT_CMGP_ADC, "dout_cmgp_adc", "gout_clkcmu_cmgp_bus",
947 	    CLK_CON_DIV_DIV_CLK_CMGP_ADC, 0, 4),
948 	DIV(CLK_DOUT_CMGP_USI0, "dout_cmgp_usi0", "mout_cmgp_usi0",
949 	    CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0, 0, 5),
950 	DIV(CLK_DOUT_CMGP_USI1, "dout_cmgp_usi1", "mout_cmgp_usi1",
951 	    CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1, 0, 5),
952 };
953 
954 static const struct samsung_gate_clock cmgp_gate_clks[] __initconst = {
955 	GATE(CLK_GOUT_CMGP_ADC_S0_PCLK, "gout_adc_s0_pclk",
956 	     "gout_clkcmu_cmgp_bus",
957 	     CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0, 21, 0, 0),
958 	GATE(CLK_GOUT_CMGP_ADC_S1_PCLK, "gout_adc_s1_pclk",
959 	     "gout_clkcmu_cmgp_bus",
960 	     CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1, 21, 0, 0),
961 	/* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
962 	GATE(CLK_GOUT_CMGP_GPIO_PCLK, "gout_gpio_cmgp_pclk",
963 	     "gout_clkcmu_cmgp_bus",
964 	     CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK, 21, CLK_IGNORE_UNUSED, 0),
965 	GATE(CLK_GOUT_CMGP_USI0_IPCLK, "gout_cmgp_usi0_ipclk", "dout_cmgp_usi0",
966 	     CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK, 21, 0, 0),
967 	GATE(CLK_GOUT_CMGP_USI0_PCLK, "gout_cmgp_usi0_pclk",
968 	     "gout_clkcmu_cmgp_bus",
969 	     CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK, 21, 0, 0),
970 	GATE(CLK_GOUT_CMGP_USI1_IPCLK, "gout_cmgp_usi1_ipclk", "dout_cmgp_usi1",
971 	     CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK, 21, 0, 0),
972 	GATE(CLK_GOUT_CMGP_USI1_PCLK, "gout_cmgp_usi1_pclk",
973 	     "gout_clkcmu_cmgp_bus",
974 	     CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK, 21, 0, 0),
975 	GATE(CLK_GOUT_SYSREG_CMGP_PCLK, "gout_sysreg_cmgp_pclk",
976 	     "gout_clkcmu_cmgp_bus",
977 	     CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK, 21, 0, 0),
978 };
979 
980 static const struct samsung_cmu_info cmgp_cmu_info __initconst = {
981 	.mux_clks		= cmgp_mux_clks,
982 	.nr_mux_clks		= ARRAY_SIZE(cmgp_mux_clks),
983 	.div_clks		= cmgp_div_clks,
984 	.nr_div_clks		= ARRAY_SIZE(cmgp_div_clks),
985 	.gate_clks		= cmgp_gate_clks,
986 	.nr_gate_clks		= ARRAY_SIZE(cmgp_gate_clks),
987 	.fixed_clks		= cmgp_fixed_clks,
988 	.nr_fixed_clks		= ARRAY_SIZE(cmgp_fixed_clks),
989 	.nr_clk_ids		= CMGP_NR_CLK,
990 	.clk_regs		= cmgp_clk_regs,
991 	.nr_clk_regs		= ARRAY_SIZE(cmgp_clk_regs),
992 	.clk_name		= "gout_clkcmu_cmgp_bus",
993 };
994 
995 /* ---- CMU_HSI ------------------------------------------------------------- */
996 
997 /* Register Offset definitions for CMU_HSI (0x13400000) */
998 #define PLL_CON0_MUX_CLKCMU_HSI_BUS_USER			0x0600
999 #define PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER			0x0610
1000 #define PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER			0x0620
1001 #define CLK_CON_MUX_MUX_CLK_HSI_RTC				0x1000
1002 #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV		0x2008
1003 #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50		0x200c
1004 #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26		0x2010
1005 #define CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK			0x2018
1006 #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK			0x2024
1007 #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN			0x2028
1008 #define CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK			0x2038
1009 #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20	0x203c
1010 #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY		0x2040
1011 
1012 static const unsigned long hsi_clk_regs[] __initconst = {
1013 	PLL_CON0_MUX_CLKCMU_HSI_BUS_USER,
1014 	PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER,
1015 	PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER,
1016 	CLK_CON_MUX_MUX_CLK_HSI_RTC,
1017 	CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV,
1018 	CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50,
1019 	CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26,
1020 	CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK,
1021 	CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK,
1022 	CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN,
1023 	CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK,
1024 	CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20,
1025 	CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY,
1026 };
1027 
1028 /* List of parent clocks for Muxes in CMU_HSI */
1029 PNAME(mout_hsi_bus_user_p)	= { "oscclk", "dout_hsi_bus" };
1030 PNAME(mout_hsi_mmc_card_user_p)	= { "oscclk", "dout_hsi_mmc_card" };
1031 PNAME(mout_hsi_usb20drd_user_p)	= { "oscclk", "dout_hsi_usb20drd" };
1032 PNAME(mout_hsi_rtc_p)		= { "rtcclk", "oscclk" };
1033 
1034 static const struct samsung_mux_clock hsi_mux_clks[] __initconst = {
1035 	MUX(CLK_MOUT_HSI_BUS_USER, "mout_hsi_bus_user", mout_hsi_bus_user_p,
1036 	    PLL_CON0_MUX_CLKCMU_HSI_BUS_USER, 4, 1),
1037 	MUX_F(CLK_MOUT_HSI_MMC_CARD_USER, "mout_hsi_mmc_card_user",
1038 	      mout_hsi_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER,
1039 	      4, 1, CLK_SET_RATE_PARENT, 0),
1040 	MUX(CLK_MOUT_HSI_USB20DRD_USER, "mout_hsi_usb20drd_user",
1041 	    mout_hsi_usb20drd_user_p, PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER,
1042 	    4, 1),
1043 	MUX(CLK_MOUT_HSI_RTC, "mout_hsi_rtc", mout_hsi_rtc_p,
1044 	    CLK_CON_MUX_MUX_CLK_HSI_RTC, 0, 1),
1045 };
1046 
1047 static const struct samsung_gate_clock hsi_gate_clks[] __initconst = {
1048 	GATE(CLK_GOUT_USB_RTC_CLK, "gout_usb_rtc", "mout_hsi_rtc",
1049 	     CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, 21, 0, 0),
1050 	GATE(CLK_GOUT_USB_REF_CLK, "gout_usb_ref", "mout_hsi_usb20drd_user",
1051 	     CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, 21, 0, 0),
1052 	GATE(CLK_GOUT_USB_PHY_REF_CLK, "gout_usb_phy_ref", "oscclk",
1053 	     CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, 21, 0, 0),
1054 	/* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
1055 	GATE(CLK_GOUT_GPIO_HSI_PCLK, "gout_gpio_hsi_pclk", "mout_hsi_bus_user",
1056 	     CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1057 	GATE(CLK_GOUT_MMC_CARD_ACLK, "gout_mmc_card_aclk", "mout_hsi_bus_user",
1058 	     CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, 21, 0, 0),
1059 	GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin",
1060 	     "mout_hsi_mmc_card_user",
1061 	     CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 21, CLK_SET_RATE_PARENT, 0),
1062 	GATE(CLK_GOUT_SYSREG_HSI_PCLK, "gout_sysreg_hsi_pclk",
1063 	     "mout_hsi_bus_user",
1064 	     CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, 21, 0, 0),
1065 	GATE(CLK_GOUT_USB_PHY_ACLK, "gout_usb_phy_aclk", "mout_hsi_bus_user",
1066 	     CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20, 21, 0, 0),
1067 	GATE(CLK_GOUT_USB_BUS_EARLY_CLK, "gout_usb_bus_early",
1068 	     "mout_hsi_bus_user",
1069 	     CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, 21, 0, 0),
1070 };
1071 
1072 static const struct samsung_cmu_info hsi_cmu_info __initconst = {
1073 	.mux_clks		= hsi_mux_clks,
1074 	.nr_mux_clks		= ARRAY_SIZE(hsi_mux_clks),
1075 	.gate_clks		= hsi_gate_clks,
1076 	.nr_gate_clks		= ARRAY_SIZE(hsi_gate_clks),
1077 	.nr_clk_ids		= HSI_NR_CLK,
1078 	.clk_regs		= hsi_clk_regs,
1079 	.nr_clk_regs		= ARRAY_SIZE(hsi_clk_regs),
1080 	.clk_name		= "dout_hsi_bus",
1081 };
1082 
1083 /* ---- CMU_IS -------------------------------------------------------------- */
1084 
1085 #define PLL_CON0_MUX_CLKCMU_IS_BUS_USER		0x0600
1086 #define PLL_CON0_MUX_CLKCMU_IS_GDC_USER		0x0610
1087 #define PLL_CON0_MUX_CLKCMU_IS_ITP_USER		0x0620
1088 #define PLL_CON0_MUX_CLKCMU_IS_VRA_USER		0x0630
1089 #define CLK_CON_DIV_DIV_CLK_IS_BUSP		0x1800
1090 #define CLK_CON_GAT_CLK_IS_CMU_IS_PCLK		0x2000
1091 #define CLK_CON_GAT_GOUT_IS_CSIS0_ACLK		0x2040
1092 #define CLK_CON_GAT_GOUT_IS_CSIS1_ACLK		0x2044
1093 #define CLK_CON_GAT_GOUT_IS_CSIS2_ACLK		0x2048
1094 #define CLK_CON_GAT_GOUT_IS_TZPC_PCLK		0x204c
1095 #define CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA	0x2050
1096 #define CLK_CON_GAT_GOUT_IS_CLK_GDC		0x2054
1097 #define CLK_CON_GAT_GOUT_IS_CLK_IPP		0x2058
1098 #define CLK_CON_GAT_GOUT_IS_CLK_ITP		0x205c
1099 #define CLK_CON_GAT_GOUT_IS_CLK_MCSC		0x2060
1100 #define CLK_CON_GAT_GOUT_IS_CLK_VRA		0x2064
1101 #define CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK	0x2074
1102 #define CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK	0x2078
1103 #define CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK	0x207c
1104 #define CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK	0x2080
1105 #define CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1	0x2098
1106 #define CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1	0x209c
1107 #define CLK_CON_GAT_GOUT_IS_SYSREG_PCLK		0x20a0
1108 
1109 static const unsigned long is_clk_regs[] __initconst = {
1110 	PLL_CON0_MUX_CLKCMU_IS_BUS_USER,
1111 	PLL_CON0_MUX_CLKCMU_IS_GDC_USER,
1112 	PLL_CON0_MUX_CLKCMU_IS_ITP_USER,
1113 	PLL_CON0_MUX_CLKCMU_IS_VRA_USER,
1114 	CLK_CON_DIV_DIV_CLK_IS_BUSP,
1115 	CLK_CON_GAT_CLK_IS_CMU_IS_PCLK,
1116 	CLK_CON_GAT_GOUT_IS_CSIS0_ACLK,
1117 	CLK_CON_GAT_GOUT_IS_CSIS1_ACLK,
1118 	CLK_CON_GAT_GOUT_IS_CSIS2_ACLK,
1119 	CLK_CON_GAT_GOUT_IS_TZPC_PCLK,
1120 	CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA,
1121 	CLK_CON_GAT_GOUT_IS_CLK_GDC,
1122 	CLK_CON_GAT_GOUT_IS_CLK_IPP,
1123 	CLK_CON_GAT_GOUT_IS_CLK_ITP,
1124 	CLK_CON_GAT_GOUT_IS_CLK_MCSC,
1125 	CLK_CON_GAT_GOUT_IS_CLK_VRA,
1126 	CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK,
1127 	CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK,
1128 	CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK,
1129 	CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK,
1130 	CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1,
1131 	CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1,
1132 	CLK_CON_GAT_GOUT_IS_SYSREG_PCLK,
1133 };
1134 
1135 /* List of parent clocks for Muxes in CMU_IS */
1136 PNAME(mout_is_bus_user_p)	= { "oscclk", "dout_is_bus" };
1137 PNAME(mout_is_itp_user_p)	= { "oscclk", "dout_is_itp" };
1138 PNAME(mout_is_vra_user_p)	= { "oscclk", "dout_is_vra" };
1139 PNAME(mout_is_gdc_user_p)	= { "oscclk", "dout_is_gdc" };
1140 
1141 static const struct samsung_mux_clock is_mux_clks[] __initconst = {
1142 	MUX(CLK_MOUT_IS_BUS_USER, "mout_is_bus_user", mout_is_bus_user_p,
1143 	    PLL_CON0_MUX_CLKCMU_IS_BUS_USER, 4, 1),
1144 	MUX(CLK_MOUT_IS_ITP_USER, "mout_is_itp_user", mout_is_itp_user_p,
1145 	    PLL_CON0_MUX_CLKCMU_IS_ITP_USER, 4, 1),
1146 	MUX(CLK_MOUT_IS_VRA_USER, "mout_is_vra_user", mout_is_vra_user_p,
1147 	    PLL_CON0_MUX_CLKCMU_IS_VRA_USER, 4, 1),
1148 	MUX(CLK_MOUT_IS_GDC_USER, "mout_is_gdc_user", mout_is_gdc_user_p,
1149 	    PLL_CON0_MUX_CLKCMU_IS_GDC_USER, 4, 1),
1150 };
1151 
1152 static const struct samsung_div_clock is_div_clks[] __initconst = {
1153 	DIV(CLK_DOUT_IS_BUSP, "dout_is_busp", "mout_is_bus_user",
1154 	    CLK_CON_DIV_DIV_CLK_IS_BUSP, 0, 2),
1155 };
1156 
1157 static const struct samsung_gate_clock is_gate_clks[] __initconst = {
1158 	/* TODO: Should be enabled in IS driver */
1159 	GATE(CLK_GOUT_IS_CMU_IS_PCLK, "gout_is_cmu_is_pclk", "dout_is_busp",
1160 	     CLK_CON_GAT_CLK_IS_CMU_IS_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1161 	GATE(CLK_GOUT_IS_CSIS0_ACLK, "gout_is_csis0_aclk", "mout_is_bus_user",
1162 	     CLK_CON_GAT_GOUT_IS_CSIS0_ACLK, 21, 0, 0),
1163 	GATE(CLK_GOUT_IS_CSIS1_ACLK, "gout_is_csis1_aclk", "mout_is_bus_user",
1164 	     CLK_CON_GAT_GOUT_IS_CSIS1_ACLK, 21, 0, 0),
1165 	GATE(CLK_GOUT_IS_CSIS2_ACLK, "gout_is_csis2_aclk", "mout_is_bus_user",
1166 	     CLK_CON_GAT_GOUT_IS_CSIS2_ACLK, 21, 0, 0),
1167 	GATE(CLK_GOUT_IS_TZPC_PCLK, "gout_is_tzpc_pclk", "dout_is_busp",
1168 	     CLK_CON_GAT_GOUT_IS_TZPC_PCLK, 21, 0, 0),
1169 	GATE(CLK_GOUT_IS_CSIS_DMA_CLK, "gout_is_csis_dma_clk",
1170 	     "mout_is_bus_user",
1171 	     CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA, 21, 0, 0),
1172 	GATE(CLK_GOUT_IS_GDC_CLK, "gout_is_gdc_clk", "mout_is_gdc_user",
1173 	     CLK_CON_GAT_GOUT_IS_CLK_GDC, 21, 0, 0),
1174 	GATE(CLK_GOUT_IS_IPP_CLK, "gout_is_ipp_clk", "mout_is_bus_user",
1175 	     CLK_CON_GAT_GOUT_IS_CLK_IPP, 21, 0, 0),
1176 	GATE(CLK_GOUT_IS_ITP_CLK, "gout_is_itp_clk", "mout_is_itp_user",
1177 	     CLK_CON_GAT_GOUT_IS_CLK_ITP, 21, 0, 0),
1178 	GATE(CLK_GOUT_IS_MCSC_CLK, "gout_is_mcsc_clk", "mout_is_itp_user",
1179 	     CLK_CON_GAT_GOUT_IS_CLK_MCSC, 21, 0, 0),
1180 	GATE(CLK_GOUT_IS_VRA_CLK, "gout_is_vra_clk", "mout_is_vra_user",
1181 	     CLK_CON_GAT_GOUT_IS_CLK_VRA, 21, 0, 0),
1182 	GATE(CLK_GOUT_IS_PPMU_IS0_ACLK, "gout_is_ppmu_is0_aclk",
1183 	     "mout_is_bus_user",
1184 	     CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK, 21, 0, 0),
1185 	GATE(CLK_GOUT_IS_PPMU_IS0_PCLK, "gout_is_ppmu_is0_pclk", "dout_is_busp",
1186 	     CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK, 21, 0, 0),
1187 	GATE(CLK_GOUT_IS_PPMU_IS1_ACLK, "gout_is_ppmu_is1_aclk",
1188 	     "mout_is_itp_user",
1189 	     CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK, 21, 0, 0),
1190 	GATE(CLK_GOUT_IS_PPMU_IS1_PCLK, "gout_is_ppmu_is1_pclk", "dout_is_busp",
1191 	     CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK, 21, 0, 0),
1192 	GATE(CLK_GOUT_IS_SYSMMU_IS0_CLK, "gout_is_sysmmu_is0_clk",
1193 	     "mout_is_bus_user",
1194 	     CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1, 21, 0, 0),
1195 	GATE(CLK_GOUT_IS_SYSMMU_IS1_CLK, "gout_is_sysmmu_is1_clk",
1196 	     "mout_is_itp_user",
1197 	     CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1, 21, 0, 0),
1198 	GATE(CLK_GOUT_IS_SYSREG_PCLK, "gout_is_sysreg_pclk", "dout_is_busp",
1199 	     CLK_CON_GAT_GOUT_IS_SYSREG_PCLK, 21, 0, 0),
1200 };
1201 
1202 static const struct samsung_cmu_info is_cmu_info __initconst = {
1203 	.mux_clks		= is_mux_clks,
1204 	.nr_mux_clks		= ARRAY_SIZE(is_mux_clks),
1205 	.div_clks		= is_div_clks,
1206 	.nr_div_clks		= ARRAY_SIZE(is_div_clks),
1207 	.gate_clks		= is_gate_clks,
1208 	.nr_gate_clks		= ARRAY_SIZE(is_gate_clks),
1209 	.nr_clk_ids		= IS_NR_CLK,
1210 	.clk_regs		= is_clk_regs,
1211 	.nr_clk_regs		= ARRAY_SIZE(is_clk_regs),
1212 	.clk_name		= "dout_is_bus",
1213 };
1214 
1215 /* ---- CMU_MFCMSCL --------------------------------------------------------- */
1216 
1217 #define PLL_CON0_MUX_CLKCMU_MFCMSCL_JPEG_USER		0x0600
1218 #define PLL_CON0_MUX_CLKCMU_MFCMSCL_M2M_USER		0x0610
1219 #define PLL_CON0_MUX_CLKCMU_MFCMSCL_MCSC_USER		0x0620
1220 #define PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER		0x0630
1221 #define CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP		0x1800
1222 #define CLK_CON_GAT_CLK_MFCMSCL_CMU_MFCMSCL_PCLK	0x2000
1223 #define CLK_CON_GAT_GOUT_MFCMSCL_TZPC_PCLK		0x2038
1224 #define CLK_CON_GAT_GOUT_MFCMSCL_JPEG_ACLK		0x203c
1225 #define CLK_CON_GAT_GOUT_MFCMSCL_M2M_ACLK		0x2048
1226 #define CLK_CON_GAT_GOUT_MFCMSCL_MCSC_I_CLK		0x204c
1227 #define CLK_CON_GAT_GOUT_MFCMSCL_MFC_ACLK		0x2050
1228 #define CLK_CON_GAT_GOUT_MFCMSCL_PPMU_ACLK		0x2054
1229 #define CLK_CON_GAT_GOUT_MFCMSCL_PPMU_PCLK		0x2058
1230 #define CLK_CON_GAT_GOUT_MFCMSCL_SYSMMU_CLK_S1		0x2074
1231 #define CLK_CON_GAT_GOUT_MFCMSCL_SYSREG_PCLK		0x2078
1232 
1233 static const unsigned long mfcmscl_clk_regs[] __initconst = {
1234 	PLL_CON0_MUX_CLKCMU_MFCMSCL_JPEG_USER,
1235 	PLL_CON0_MUX_CLKCMU_MFCMSCL_M2M_USER,
1236 	PLL_CON0_MUX_CLKCMU_MFCMSCL_MCSC_USER,
1237 	PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER,
1238 	CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP,
1239 	CLK_CON_GAT_CLK_MFCMSCL_CMU_MFCMSCL_PCLK,
1240 	CLK_CON_GAT_GOUT_MFCMSCL_TZPC_PCLK,
1241 	CLK_CON_GAT_GOUT_MFCMSCL_JPEG_ACLK,
1242 	CLK_CON_GAT_GOUT_MFCMSCL_M2M_ACLK,
1243 	CLK_CON_GAT_GOUT_MFCMSCL_MCSC_I_CLK,
1244 	CLK_CON_GAT_GOUT_MFCMSCL_MFC_ACLK,
1245 	CLK_CON_GAT_GOUT_MFCMSCL_PPMU_ACLK,
1246 	CLK_CON_GAT_GOUT_MFCMSCL_PPMU_PCLK,
1247 	CLK_CON_GAT_GOUT_MFCMSCL_SYSMMU_CLK_S1,
1248 	CLK_CON_GAT_GOUT_MFCMSCL_SYSREG_PCLK,
1249 };
1250 
1251 /* List of parent clocks for Muxes in CMU_MFCMSCL */
1252 PNAME(mout_mfcmscl_mfc_user_p)	= { "oscclk", "dout_mfcmscl_mfc" };
1253 PNAME(mout_mfcmscl_m2m_user_p)	= { "oscclk", "dout_mfcmscl_m2m" };
1254 PNAME(mout_mfcmscl_mcsc_user_p)	= { "oscclk", "dout_mfcmscl_mcsc" };
1255 PNAME(mout_mfcmscl_jpeg_user_p)	= { "oscclk", "dout_mfcmscl_jpeg" };
1256 
1257 static const struct samsung_mux_clock mfcmscl_mux_clks[] __initconst = {
1258 	MUX(CLK_MOUT_MFCMSCL_MFC_USER, "mout_mfcmscl_mfc_user",
1259 	    mout_mfcmscl_mfc_user_p,
1260 	    PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER, 4, 1),
1261 	MUX(CLK_MOUT_MFCMSCL_M2M_USER, "mout_mfcmscl_m2m_user",
1262 	    mout_mfcmscl_m2m_user_p,
1263 	    PLL_CON0_MUX_CLKCMU_MFCMSCL_M2M_USER, 4, 1),
1264 	MUX(CLK_MOUT_MFCMSCL_MCSC_USER, "mout_mfcmscl_mcsc_user",
1265 	    mout_mfcmscl_mcsc_user_p,
1266 	    PLL_CON0_MUX_CLKCMU_MFCMSCL_MCSC_USER, 4, 1),
1267 	MUX(CLK_MOUT_MFCMSCL_JPEG_USER, "mout_mfcmscl_jpeg_user",
1268 	    mout_mfcmscl_jpeg_user_p,
1269 	    PLL_CON0_MUX_CLKCMU_MFCMSCL_JPEG_USER, 4, 1),
1270 };
1271 
1272 static const struct samsung_div_clock mfcmscl_div_clks[] __initconst = {
1273 	DIV(CLK_DOUT_MFCMSCL_BUSP, "dout_mfcmscl_busp", "mout_mfcmscl_mfc_user",
1274 	    CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP, 0, 3),
1275 };
1276 
1277 static const struct samsung_gate_clock mfcmscl_gate_clks[] __initconst = {
1278 	/* TODO: Should be enabled in MFC driver */
1279 	GATE(CLK_GOUT_MFCMSCL_CMU_MFCMSCL_PCLK, "gout_mfcmscl_cmu_mfcmscl_pclk",
1280 	     "dout_mfcmscl_busp", CLK_CON_GAT_CLK_MFCMSCL_CMU_MFCMSCL_PCLK,
1281 	     21, CLK_IGNORE_UNUSED, 0),
1282 	GATE(CLK_GOUT_MFCMSCL_TZPC_PCLK, "gout_mfcmscl_tzpc_pclk",
1283 	     "dout_mfcmscl_busp", CLK_CON_GAT_GOUT_MFCMSCL_TZPC_PCLK,
1284 	     21, 0, 0),
1285 	GATE(CLK_GOUT_MFCMSCL_JPEG_ACLK, "gout_mfcmscl_jpeg_aclk",
1286 	     "mout_mfcmscl_jpeg_user", CLK_CON_GAT_GOUT_MFCMSCL_JPEG_ACLK,
1287 	     21, 0, 0),
1288 	GATE(CLK_GOUT_MFCMSCL_M2M_ACLK, "gout_mfcmscl_m2m_aclk",
1289 	     "mout_mfcmscl_m2m_user", CLK_CON_GAT_GOUT_MFCMSCL_M2M_ACLK,
1290 	     21, 0, 0),
1291 	GATE(CLK_GOUT_MFCMSCL_MCSC_CLK, "gout_mfcmscl_mcsc_clk",
1292 	     "mout_mfcmscl_mcsc_user", CLK_CON_GAT_GOUT_MFCMSCL_MCSC_I_CLK,
1293 	     21, 0, 0),
1294 	GATE(CLK_GOUT_MFCMSCL_MFC_ACLK, "gout_mfcmscl_mfc_aclk",
1295 	     "mout_mfcmscl_mfc_user", CLK_CON_GAT_GOUT_MFCMSCL_MFC_ACLK,
1296 	     21, 0, 0),
1297 	GATE(CLK_GOUT_MFCMSCL_PPMU_ACLK, "gout_mfcmscl_ppmu_aclk",
1298 	     "mout_mfcmscl_mfc_user", CLK_CON_GAT_GOUT_MFCMSCL_PPMU_ACLK,
1299 	     21, 0, 0),
1300 	GATE(CLK_GOUT_MFCMSCL_PPMU_PCLK, "gout_mfcmscl_ppmu_pclk",
1301 	     "dout_mfcmscl_busp", CLK_CON_GAT_GOUT_MFCMSCL_PPMU_PCLK,
1302 	     21, 0, 0),
1303 	GATE(CLK_GOUT_MFCMSCL_SYSMMU_CLK, "gout_mfcmscl_sysmmu_clk",
1304 	     "mout_mfcmscl_mfc_user", CLK_CON_GAT_GOUT_MFCMSCL_SYSMMU_CLK_S1,
1305 	     21, 0, 0),
1306 	GATE(CLK_GOUT_MFCMSCL_SYSREG_PCLK, "gout_mfcmscl_sysreg_pclk",
1307 	     "dout_mfcmscl_busp", CLK_CON_GAT_GOUT_MFCMSCL_SYSREG_PCLK,
1308 	     21, 0, 0),
1309 };
1310 
1311 static const struct samsung_cmu_info mfcmscl_cmu_info __initconst = {
1312 	.mux_clks		= mfcmscl_mux_clks,
1313 	.nr_mux_clks		= ARRAY_SIZE(mfcmscl_mux_clks),
1314 	.div_clks		= mfcmscl_div_clks,
1315 	.nr_div_clks		= ARRAY_SIZE(mfcmscl_div_clks),
1316 	.gate_clks		= mfcmscl_gate_clks,
1317 	.nr_gate_clks		= ARRAY_SIZE(mfcmscl_gate_clks),
1318 	.nr_clk_ids		= MFCMSCL_NR_CLK,
1319 	.clk_regs		= mfcmscl_clk_regs,
1320 	.nr_clk_regs		= ARRAY_SIZE(mfcmscl_clk_regs),
1321 	.clk_name		= "dout_mfcmscl_mfc",
1322 };
1323 
1324 /* ---- CMU_PERI ------------------------------------------------------------ */
1325 
1326 /* Register Offset definitions for CMU_PERI (0x10030000) */
1327 #define PLL_CON0_MUX_CLKCMU_PERI_BUS_USER	0x0600
1328 #define PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER	0x0610
1329 #define PLL_CON0_MUX_CLKCMU_PERI_SPI_USER	0x0620
1330 #define PLL_CON0_MUX_CLKCMU_PERI_UART_USER	0x0630
1331 #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0	0x1800
1332 #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1	0x1804
1333 #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2	0x1808
1334 #define CLK_CON_DIV_DIV_CLK_PERI_SPI_0		0x180c
1335 #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0	0x200c
1336 #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1	0x2010
1337 #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2	0x2014
1338 #define CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK	0x2020
1339 #define CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK	0x2024
1340 #define CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK	0x2028
1341 #define CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK	0x202c
1342 #define CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK	0x2030
1343 #define CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK	0x2034
1344 #define CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK	0x2038
1345 #define CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK	0x203c
1346 #define CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK	0x2040
1347 #define CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK	0x2044
1348 #define CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK	0x2048
1349 #define CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK	0x204c
1350 #define CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK	0x2050
1351 #define CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK	0x2054
1352 #define CLK_CON_GAT_GOUT_PERI_MCT_PCLK		0x205c
1353 #define CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK	0x2064
1354 #define CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK	0x209c
1355 #define CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK	0x20a0
1356 #define CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK	0x20a4
1357 #define CLK_CON_GAT_GOUT_PERI_UART_IPCLK	0x20a8
1358 #define CLK_CON_GAT_GOUT_PERI_UART_PCLK		0x20ac
1359 #define CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK	0x20b0
1360 #define CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK	0x20b4
1361 
1362 static const unsigned long peri_clk_regs[] __initconst = {
1363 	PLL_CON0_MUX_CLKCMU_PERI_BUS_USER,
1364 	PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER,
1365 	PLL_CON0_MUX_CLKCMU_PERI_SPI_USER,
1366 	PLL_CON0_MUX_CLKCMU_PERI_UART_USER,
1367 	CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0,
1368 	CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1,
1369 	CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2,
1370 	CLK_CON_DIV_DIV_CLK_PERI_SPI_0,
1371 	CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0,
1372 	CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1,
1373 	CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2,
1374 	CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK,
1375 	CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK,
1376 	CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK,
1377 	CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK,
1378 	CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK,
1379 	CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK,
1380 	CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK,
1381 	CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK,
1382 	CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK,
1383 	CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK,
1384 	CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK,
1385 	CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK,
1386 	CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK,
1387 	CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK,
1388 	CLK_CON_GAT_GOUT_PERI_MCT_PCLK,
1389 	CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK,
1390 	CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK,
1391 	CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK,
1392 	CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK,
1393 	CLK_CON_GAT_GOUT_PERI_UART_IPCLK,
1394 	CLK_CON_GAT_GOUT_PERI_UART_PCLK,
1395 	CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK,
1396 	CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK,
1397 };
1398 
1399 /* List of parent clocks for Muxes in CMU_PERI */
1400 PNAME(mout_peri_bus_user_p)	= { "oscclk", "dout_peri_bus" };
1401 PNAME(mout_peri_uart_user_p)	= { "oscclk", "dout_peri_uart" };
1402 PNAME(mout_peri_hsi2c_user_p)	= { "oscclk", "dout_peri_ip" };
1403 PNAME(mout_peri_spi_user_p)	= { "oscclk", "dout_peri_ip" };
1404 
1405 static const struct samsung_mux_clock peri_mux_clks[] __initconst = {
1406 	MUX(CLK_MOUT_PERI_BUS_USER, "mout_peri_bus_user", mout_peri_bus_user_p,
1407 	    PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 4, 1),
1408 	MUX(CLK_MOUT_PERI_UART_USER, "mout_peri_uart_user",
1409 	    mout_peri_uart_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART_USER, 4, 1),
1410 	MUX(CLK_MOUT_PERI_HSI2C_USER, "mout_peri_hsi2c_user",
1411 	    mout_peri_hsi2c_user_p, PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER, 4, 1),
1412 	MUX(CLK_MOUT_PERI_SPI_USER, "mout_peri_spi_user", mout_peri_spi_user_p,
1413 	    PLL_CON0_MUX_CLKCMU_PERI_SPI_USER, 4, 1),
1414 };
1415 
1416 static const struct samsung_div_clock peri_div_clks[] __initconst = {
1417 	DIV(CLK_DOUT_PERI_HSI2C0, "dout_peri_hsi2c0", "gout_peri_hsi2c0",
1418 	    CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0, 0, 5),
1419 	DIV(CLK_DOUT_PERI_HSI2C1, "dout_peri_hsi2c1", "gout_peri_hsi2c1",
1420 	    CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1, 0, 5),
1421 	DIV(CLK_DOUT_PERI_HSI2C2, "dout_peri_hsi2c2", "gout_peri_hsi2c2",
1422 	    CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2, 0, 5),
1423 	DIV(CLK_DOUT_PERI_SPI0, "dout_peri_spi0", "mout_peri_spi_user",
1424 	    CLK_CON_DIV_DIV_CLK_PERI_SPI_0, 0, 5),
1425 };
1426 
1427 static const struct samsung_gate_clock peri_gate_clks[] __initconst = {
1428 	GATE(CLK_GOUT_PERI_HSI2C0, "gout_peri_hsi2c0", "mout_peri_hsi2c_user",
1429 	     CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0, 21, 0, 0),
1430 	GATE(CLK_GOUT_PERI_HSI2C1, "gout_peri_hsi2c1", "mout_peri_hsi2c_user",
1431 	     CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1, 21, 0, 0),
1432 	GATE(CLK_GOUT_PERI_HSI2C2, "gout_peri_hsi2c2", "mout_peri_hsi2c_user",
1433 	     CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2, 21, 0, 0),
1434 	GATE(CLK_GOUT_HSI2C0_IPCLK, "gout_hsi2c0_ipclk", "dout_peri_hsi2c0",
1435 	     CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK, 21, 0, 0),
1436 	GATE(CLK_GOUT_HSI2C0_PCLK, "gout_hsi2c0_pclk", "mout_peri_bus_user",
1437 	     CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK, 21, 0, 0),
1438 	GATE(CLK_GOUT_HSI2C1_IPCLK, "gout_hsi2c1_ipclk", "dout_peri_hsi2c1",
1439 	     CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK, 21, 0, 0),
1440 	GATE(CLK_GOUT_HSI2C1_PCLK, "gout_hsi2c1_pclk", "mout_peri_bus_user",
1441 	     CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK, 21, 0, 0),
1442 	GATE(CLK_GOUT_HSI2C2_IPCLK, "gout_hsi2c2_ipclk", "dout_peri_hsi2c2",
1443 	     CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK, 21, 0, 0),
1444 	GATE(CLK_GOUT_HSI2C2_PCLK, "gout_hsi2c2_pclk", "mout_peri_bus_user",
1445 	     CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK, 21, 0, 0),
1446 	GATE(CLK_GOUT_I2C0_PCLK, "gout_i2c0_pclk", "mout_peri_bus_user",
1447 	     CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, 21, 0, 0),
1448 	GATE(CLK_GOUT_I2C1_PCLK, "gout_i2c1_pclk", "mout_peri_bus_user",
1449 	     CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, 21, 0, 0),
1450 	GATE(CLK_GOUT_I2C2_PCLK, "gout_i2c2_pclk", "mout_peri_bus_user",
1451 	     CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, 21, 0, 0),
1452 	GATE(CLK_GOUT_I2C3_PCLK, "gout_i2c3_pclk", "mout_peri_bus_user",
1453 	     CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, 21, 0, 0),
1454 	GATE(CLK_GOUT_I2C4_PCLK, "gout_i2c4_pclk", "mout_peri_bus_user",
1455 	     CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, 21, 0, 0),
1456 	GATE(CLK_GOUT_I2C5_PCLK, "gout_i2c5_pclk", "mout_peri_bus_user",
1457 	     CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, 21, 0, 0),
1458 	GATE(CLK_GOUT_I2C6_PCLK, "gout_i2c6_pclk", "mout_peri_bus_user",
1459 	     CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, 21, 0, 0),
1460 	GATE(CLK_GOUT_MCT_PCLK, "gout_mct_pclk", "mout_peri_bus_user",
1461 	     CLK_CON_GAT_GOUT_PERI_MCT_PCLK, 21, 0, 0),
1462 	GATE(CLK_GOUT_PWM_MOTOR_PCLK, "gout_pwm_motor_pclk",
1463 	     "mout_peri_bus_user",
1464 	     CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 21, 0, 0),
1465 	GATE(CLK_GOUT_SPI0_IPCLK, "gout_spi0_ipclk", "dout_peri_spi0",
1466 	     CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK, 21, 0, 0),
1467 	GATE(CLK_GOUT_SPI0_PCLK, "gout_spi0_pclk", "mout_peri_bus_user",
1468 	     CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 21, 0, 0),
1469 	GATE(CLK_GOUT_SYSREG_PERI_PCLK, "gout_sysreg_peri_pclk",
1470 	     "mout_peri_bus_user",
1471 	     CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK, 21, 0, 0),
1472 	GATE(CLK_GOUT_UART_IPCLK, "gout_uart_ipclk", "mout_peri_uart_user",
1473 	     CLK_CON_GAT_GOUT_PERI_UART_IPCLK, 21, 0, 0),
1474 	GATE(CLK_GOUT_UART_PCLK, "gout_uart_pclk", "mout_peri_bus_user",
1475 	     CLK_CON_GAT_GOUT_PERI_UART_PCLK, 21, 0, 0),
1476 	GATE(CLK_GOUT_WDT0_PCLK, "gout_wdt0_pclk", "mout_peri_bus_user",
1477 	     CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK, 21, 0, 0),
1478 	GATE(CLK_GOUT_WDT1_PCLK, "gout_wdt1_pclk", "mout_peri_bus_user",
1479 	     CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK, 21, 0, 0),
1480 	/* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
1481 	GATE(CLK_GOUT_GPIO_PERI_PCLK, "gout_gpio_peri_pclk",
1482 	     "mout_peri_bus_user",
1483 	     CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1484 };
1485 
1486 static const struct samsung_cmu_info peri_cmu_info __initconst = {
1487 	.mux_clks		= peri_mux_clks,
1488 	.nr_mux_clks		= ARRAY_SIZE(peri_mux_clks),
1489 	.div_clks		= peri_div_clks,
1490 	.nr_div_clks		= ARRAY_SIZE(peri_div_clks),
1491 	.gate_clks		= peri_gate_clks,
1492 	.nr_gate_clks		= ARRAY_SIZE(peri_gate_clks),
1493 	.nr_clk_ids		= PERI_NR_CLK,
1494 	.clk_regs		= peri_clk_regs,
1495 	.nr_clk_regs		= ARRAY_SIZE(peri_clk_regs),
1496 	.clk_name		= "dout_peri_bus",
1497 };
1498 
1499 static void __init exynos850_cmu_peri_init(struct device_node *np)
1500 {
1501 	exynos_arm64_register_cmu(NULL, np, &peri_cmu_info);
1502 }
1503 
1504 /* Register CMU_PERI early, as it's needed for MCT timer */
1505 CLK_OF_DECLARE(exynos850_cmu_peri, "samsung,exynos850-cmu-peri",
1506 	       exynos850_cmu_peri_init);
1507 
1508 /* ---- CMU_CORE ------------------------------------------------------------ */
1509 
1510 /* Register Offset definitions for CMU_CORE (0x12000000) */
1511 #define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER	0x0600
1512 #define PLL_CON0_MUX_CLKCMU_CORE_CCI_USER	0x0610
1513 #define PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER	0x0620
1514 #define PLL_CON0_MUX_CLKCMU_CORE_SSS_USER	0x0630
1515 #define CLK_CON_MUX_MUX_CLK_CORE_GIC		0x1000
1516 #define CLK_CON_DIV_DIV_CLK_CORE_BUSP		0x1800
1517 #define CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK	0x2038
1518 #define CLK_CON_GAT_GOUT_CORE_GIC_CLK		0x2040
1519 #define CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK	0x2044
1520 #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK	0x20e8
1521 #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN	0x20ec
1522 #define CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK	0x2128
1523 #define CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK	0x212c
1524 #define CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK	0x2130
1525 
1526 static const unsigned long core_clk_regs[] __initconst = {
1527 	PLL_CON0_MUX_CLKCMU_CORE_BUS_USER,
1528 	PLL_CON0_MUX_CLKCMU_CORE_CCI_USER,
1529 	PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER,
1530 	PLL_CON0_MUX_CLKCMU_CORE_SSS_USER,
1531 	CLK_CON_MUX_MUX_CLK_CORE_GIC,
1532 	CLK_CON_DIV_DIV_CLK_CORE_BUSP,
1533 	CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK,
1534 	CLK_CON_GAT_GOUT_CORE_GIC_CLK,
1535 	CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK,
1536 	CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK,
1537 	CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN,
1538 	CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK,
1539 	CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK,
1540 	CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK,
1541 };
1542 
1543 /* List of parent clocks for Muxes in CMU_CORE */
1544 PNAME(mout_core_bus_user_p)		= { "oscclk", "dout_core_bus" };
1545 PNAME(mout_core_cci_user_p)		= { "oscclk", "dout_core_cci" };
1546 PNAME(mout_core_mmc_embd_user_p)	= { "oscclk", "dout_core_mmc_embd" };
1547 PNAME(mout_core_sss_user_p)		= { "oscclk", "dout_core_sss" };
1548 PNAME(mout_core_gic_p)			= { "dout_core_busp", "oscclk" };
1549 
1550 static const struct samsung_mux_clock core_mux_clks[] __initconst = {
1551 	MUX(CLK_MOUT_CORE_BUS_USER, "mout_core_bus_user", mout_core_bus_user_p,
1552 	    PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 4, 1),
1553 	MUX(CLK_MOUT_CORE_CCI_USER, "mout_core_cci_user", mout_core_cci_user_p,
1554 	    PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, 4, 1),
1555 	MUX_F(CLK_MOUT_CORE_MMC_EMBD_USER, "mout_core_mmc_embd_user",
1556 	      mout_core_mmc_embd_user_p, PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER,
1557 	      4, 1, CLK_SET_RATE_PARENT, 0),
1558 	MUX(CLK_MOUT_CORE_SSS_USER, "mout_core_sss_user", mout_core_sss_user_p,
1559 	    PLL_CON0_MUX_CLKCMU_CORE_SSS_USER, 4, 1),
1560 	MUX(CLK_MOUT_CORE_GIC, "mout_core_gic", mout_core_gic_p,
1561 	    CLK_CON_MUX_MUX_CLK_CORE_GIC, 0, 1),
1562 };
1563 
1564 static const struct samsung_div_clock core_div_clks[] __initconst = {
1565 	DIV(CLK_DOUT_CORE_BUSP, "dout_core_busp", "mout_core_bus_user",
1566 	    CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 2),
1567 };
1568 
1569 static const struct samsung_gate_clock core_gate_clks[] __initconst = {
1570 	/* CCI (interconnect) clock must be always running */
1571 	GATE(CLK_GOUT_CCI_ACLK, "gout_cci_aclk", "mout_core_cci_user",
1572 	     CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 21, CLK_IS_CRITICAL, 0),
1573 	/* GIC (interrupt controller) clock must be always running */
1574 	GATE(CLK_GOUT_GIC_CLK, "gout_gic_clk", "mout_core_gic",
1575 	     CLK_CON_GAT_GOUT_CORE_GIC_CLK, 21, CLK_IS_CRITICAL, 0),
1576 	GATE(CLK_GOUT_MMC_EMBD_ACLK, "gout_mmc_embd_aclk", "dout_core_busp",
1577 	     CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK, 21, 0, 0),
1578 	GATE(CLK_GOUT_MMC_EMBD_SDCLKIN, "gout_mmc_embd_sdclkin",
1579 	     "mout_core_mmc_embd_user", CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN,
1580 	     21, CLK_SET_RATE_PARENT, 0),
1581 	GATE(CLK_GOUT_SSS_ACLK, "gout_sss_aclk", "mout_core_sss_user",
1582 	     CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK, 21, 0, 0),
1583 	GATE(CLK_GOUT_SSS_PCLK, "gout_sss_pclk", "dout_core_busp",
1584 	     CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK, 21, 0, 0),
1585 	/* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
1586 	GATE(CLK_GOUT_GPIO_CORE_PCLK, "gout_gpio_core_pclk", "dout_core_busp",
1587 	     CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1588 	GATE(CLK_GOUT_SYSREG_CORE_PCLK, "gout_sysreg_core_pclk",
1589 	     "dout_core_busp",
1590 	     CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK, 21, 0, 0),
1591 };
1592 
1593 static const struct samsung_cmu_info core_cmu_info __initconst = {
1594 	.mux_clks		= core_mux_clks,
1595 	.nr_mux_clks		= ARRAY_SIZE(core_mux_clks),
1596 	.div_clks		= core_div_clks,
1597 	.nr_div_clks		= ARRAY_SIZE(core_div_clks),
1598 	.gate_clks		= core_gate_clks,
1599 	.nr_gate_clks		= ARRAY_SIZE(core_gate_clks),
1600 	.nr_clk_ids		= CORE_NR_CLK,
1601 	.clk_regs		= core_clk_regs,
1602 	.nr_clk_regs		= ARRAY_SIZE(core_clk_regs),
1603 	.clk_name		= "dout_core_bus",
1604 };
1605 
1606 /* ---- CMU_DPU ------------------------------------------------------------- */
1607 
1608 /* Register Offset definitions for CMU_DPU (0x13000000) */
1609 #define PLL_CON0_MUX_CLKCMU_DPU_USER		0x0600
1610 #define CLK_CON_DIV_DIV_CLK_DPU_BUSP		0x1800
1611 #define CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK	0x2004
1612 #define CLK_CON_GAT_GOUT_DPU_ACLK_DECON0	0x2010
1613 #define CLK_CON_GAT_GOUT_DPU_ACLK_DMA		0x2014
1614 #define CLK_CON_GAT_GOUT_DPU_ACLK_DPP		0x2018
1615 #define CLK_CON_GAT_GOUT_DPU_PPMU_ACLK		0x2028
1616 #define CLK_CON_GAT_GOUT_DPU_PPMU_PCLK		0x202c
1617 #define CLK_CON_GAT_GOUT_DPU_SMMU_CLK		0x2038
1618 #define CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK	0x203c
1619 
1620 static const unsigned long dpu_clk_regs[] __initconst = {
1621 	PLL_CON0_MUX_CLKCMU_DPU_USER,
1622 	CLK_CON_DIV_DIV_CLK_DPU_BUSP,
1623 	CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK,
1624 	CLK_CON_GAT_GOUT_DPU_ACLK_DECON0,
1625 	CLK_CON_GAT_GOUT_DPU_ACLK_DMA,
1626 	CLK_CON_GAT_GOUT_DPU_ACLK_DPP,
1627 	CLK_CON_GAT_GOUT_DPU_PPMU_ACLK,
1628 	CLK_CON_GAT_GOUT_DPU_PPMU_PCLK,
1629 	CLK_CON_GAT_GOUT_DPU_SMMU_CLK,
1630 	CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK,
1631 };
1632 
1633 /* List of parent clocks for Muxes in CMU_DPU */
1634 PNAME(mout_dpu_user_p)		= { "oscclk", "dout_dpu" };
1635 
1636 static const struct samsung_mux_clock dpu_mux_clks[] __initconst = {
1637 	MUX(CLK_MOUT_DPU_USER, "mout_dpu_user", mout_dpu_user_p,
1638 	    PLL_CON0_MUX_CLKCMU_DPU_USER, 4, 1),
1639 };
1640 
1641 static const struct samsung_div_clock dpu_div_clks[] __initconst = {
1642 	DIV(CLK_DOUT_DPU_BUSP, "dout_dpu_busp", "mout_dpu_user",
1643 	    CLK_CON_DIV_DIV_CLK_DPU_BUSP, 0, 3),
1644 };
1645 
1646 static const struct samsung_gate_clock dpu_gate_clks[] __initconst = {
1647 	/* TODO: Should be enabled in DSIM driver */
1648 	GATE(CLK_GOUT_DPU_CMU_DPU_PCLK, "gout_dpu_cmu_dpu_pclk",
1649 	     "dout_dpu_busp",
1650 	     CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1651 	GATE(CLK_GOUT_DPU_DECON0_ACLK, "gout_dpu_decon0_aclk", "mout_dpu_user",
1652 	     CLK_CON_GAT_GOUT_DPU_ACLK_DECON0, 21, 0, 0),
1653 	GATE(CLK_GOUT_DPU_DMA_ACLK, "gout_dpu_dma_aclk", "mout_dpu_user",
1654 	     CLK_CON_GAT_GOUT_DPU_ACLK_DMA, 21, 0, 0),
1655 	GATE(CLK_GOUT_DPU_DPP_ACLK, "gout_dpu_dpp_aclk", "mout_dpu_user",
1656 	     CLK_CON_GAT_GOUT_DPU_ACLK_DPP, 21, 0, 0),
1657 	GATE(CLK_GOUT_DPU_PPMU_ACLK, "gout_dpu_ppmu_aclk", "mout_dpu_user",
1658 	     CLK_CON_GAT_GOUT_DPU_PPMU_ACLK, 21, 0, 0),
1659 	GATE(CLK_GOUT_DPU_PPMU_PCLK, "gout_dpu_ppmu_pclk", "dout_dpu_busp",
1660 	     CLK_CON_GAT_GOUT_DPU_PPMU_PCLK, 21, 0, 0),
1661 	GATE(CLK_GOUT_DPU_SMMU_CLK, "gout_dpu_smmu_clk", "mout_dpu_user",
1662 	     CLK_CON_GAT_GOUT_DPU_SMMU_CLK, 21, 0, 0),
1663 	GATE(CLK_GOUT_DPU_SYSREG_PCLK, "gout_dpu_sysreg_pclk", "dout_dpu_busp",
1664 	     CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK, 21, 0, 0),
1665 };
1666 
1667 static const struct samsung_cmu_info dpu_cmu_info __initconst = {
1668 	.mux_clks		= dpu_mux_clks,
1669 	.nr_mux_clks		= ARRAY_SIZE(dpu_mux_clks),
1670 	.div_clks		= dpu_div_clks,
1671 	.nr_div_clks		= ARRAY_SIZE(dpu_div_clks),
1672 	.gate_clks		= dpu_gate_clks,
1673 	.nr_gate_clks		= ARRAY_SIZE(dpu_gate_clks),
1674 	.nr_clk_ids		= DPU_NR_CLK,
1675 	.clk_regs		= dpu_clk_regs,
1676 	.nr_clk_regs		= ARRAY_SIZE(dpu_clk_regs),
1677 	.clk_name		= "dout_dpu",
1678 };
1679 
1680 /* ---- platform_driver ----------------------------------------------------- */
1681 
1682 static int __init exynos850_cmu_probe(struct platform_device *pdev)
1683 {
1684 	const struct samsung_cmu_info *info;
1685 	struct device *dev = &pdev->dev;
1686 
1687 	info = of_device_get_match_data(dev);
1688 	exynos_arm64_register_cmu(dev, dev->of_node, info);
1689 
1690 	return 0;
1691 }
1692 
1693 static const struct of_device_id exynos850_cmu_of_match[] = {
1694 	{
1695 		.compatible = "samsung,exynos850-cmu-apm",
1696 		.data = &apm_cmu_info,
1697 	}, {
1698 		.compatible = "samsung,exynos850-cmu-aud",
1699 		.data = &aud_cmu_info,
1700 	}, {
1701 		.compatible = "samsung,exynos850-cmu-cmgp",
1702 		.data = &cmgp_cmu_info,
1703 	}, {
1704 		.compatible = "samsung,exynos850-cmu-hsi",
1705 		.data = &hsi_cmu_info,
1706 	}, {
1707 		.compatible = "samsung,exynos850-cmu-is",
1708 		.data = &is_cmu_info,
1709 	}, {
1710 		.compatible = "samsung,exynos850-cmu-mfcmscl",
1711 		.data = &mfcmscl_cmu_info,
1712 	}, {
1713 		.compatible = "samsung,exynos850-cmu-core",
1714 		.data = &core_cmu_info,
1715 	}, {
1716 		.compatible = "samsung,exynos850-cmu-dpu",
1717 		.data = &dpu_cmu_info,
1718 	}, {
1719 	},
1720 };
1721 
1722 static struct platform_driver exynos850_cmu_driver __refdata = {
1723 	.driver	= {
1724 		.name = "exynos850-cmu",
1725 		.of_match_table = exynos850_cmu_of_match,
1726 		.suppress_bind_attrs = true,
1727 	},
1728 	.probe = exynos850_cmu_probe,
1729 };
1730 
1731 static int __init exynos850_cmu_init(void)
1732 {
1733 	return platform_driver_register(&exynos850_cmu_driver);
1734 }
1735 core_initcall(exynos850_cmu_init);
1736