aspeed: ast2600: Keep PLL power on

According to the PLL vendor, we should keep PLL power on so don't toggle
the power down bit in PLL initialization.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtec

aspeed: ast2600: Keep PLL power on

According to the PLL vendor, we should keep PLL power on so don't toggle
the power down bit in PLL initialization.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I6dbba8bbb0c51a569a2ced6fdd3d69645b9f4391

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clk: ast2600: fix ast2600_find_dly32_tap return value

the return value of ast2600_find_dly32_tap should be the tap number, not
the delay time in pico-second.

Signed-off-by: Dylan Hung <dylan_hung@a

clk: ast2600: fix ast2600_find_dly32_tap return value

the return value of ast2600_find_dly32_tap should be the tap number, not
the delay time in pico-second.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: Id0a9704c95d4cd0d6f77d0dc0933a129c777ffde

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ast2600:bclk is come from epll.
it will update in datasheet

Signed-off-by: ryan_chen <ryan_chen@aspeedtech.com>
Change-Id: I0344972c5b7029c4f66c72d2cdb4466709dcea8e

clk: ast2600: Enable UART pinmux

Enable UART1~13 pinmux when their clocks are enabled.
We are doing this due to the SPL size limitation to 64KB,
which canno afford the pinctrl driver framework.

Sig

clk: ast2600: Enable UART pinmux

Enable UART1~13 pinmux when their clocks are enabled.
We are doing this due to the SPL size limitation to 64KB,
which canno afford the pinctrl driver framework.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Change-Id: Icccb58a29b676b6f7be6bc8b4f8edfb18b2e77dd

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clk: ast2600: Use a for-loop to search the MII delay value

We used binary-search to search the MII delay but this method is
difficult to handle the corner cases such as invalid lookup table, the
tar

clk: ast2600: Use a for-loop to search the MII delay value

We used binary-search to search the MII delay but this method is
difficult to handle the corner cases such as invalid lookup table, the
target delay time is out of the table. Now we use a simple for-loop to
find the delay value, if no proper delay time is found, return -1 to
specific the error condition.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I24ec3403b57113f00517da595fddc3d9870bcb07

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clk: ast2600: Setup RGMII TX delay according to the DLY32 calculation

There is a duplicate DLY32 delay cell embedded in AST2600 SOC that is
the same with the one used for RGMII clock delay. The del

clk: ast2600: Setup RGMII TX delay according to the DLY32 calculation

There is a duplicate DLY32 delay cell embedded in AST2600 SOC that is
the same with the one used for RGMII clock delay. The delay time of
each tap delay can be measured by the embedded frequency counters
SCU320 and SCU330. So we can set up the TX delay according to the
runtime measured value to cover the chip-to-chip delay time variation.

v2: revise coding style

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I42c6cf09f36baf9ded22accf476cc93ae4991d86

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clk: ast2600: rework for the MAC interface delay

replace bitfield access by simple "FIELD_PREP" and bitshift operations
to meet kernel coding style.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech

clk: ast2600: rework for the MAC interface delay

replace bitfield access by simple "FIELD_PREP" and bitshift operations
to meet kernel coding style.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I9956eafae0b88fd96143fa7ee61a88bd32579674

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clk: ast2600: Configure UART reset source

Configure the reset sources of UART1~4 if the corresponding
drivers are mounted.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Change-Id: I57f

clk: ast2600: Configure UART reset source

Configure the reset sources of UART1~4 if the corresponding
drivers are mounted.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Change-Id: I57f5444cc5273a554405fcc10bd507442e6b35d0

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clk: SD: Fix clock calculation method for SD controller

The method for calculating clock frequency is different
between AST2600-A1 and AST2600-A2/A3.

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@asp

clk: SD: Fix clock calculation method for SD controller

The method for calculating clock frequency is different
between AST2600-A1 and AST2600-A2/A3.

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Change-Id: Id32c21c4aa1345be4713f90ed67910924d51c31a

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clk: aspeed: Add RSA/ECC clock to AST2600

Add clock control for the ARCY controller, which is
the RSA/ECC HW crypto engine of AST26xx SoCs

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>

clk: aspeed: Add RSA/ECC clock to AST2600

Add clock control for the ARCY controller, which is
the RSA/ECC HW crypto engine of AST26xx SoCs

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Change-Id: Icd6b0d0fcdbdc5d43ce51254f2cc54b7caefd2b5

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Merge branch pull request #7 into aspeed-dev-v2019.04

Change-Id: I4c4f36b8edf63beb7b3afea6e4ba71f254b895c5

clk: aspeed: Add HACE yclk to ast2600

Reviewed-by: Klaus Heinrich Kiwi <klaus@linux.vnet.ibm.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>

sdhci: ast2600: HS200 support porting

- Change eMMC clock src from HPLL to MPLL if SCU300[11] is set.
- Parse device related properties when they exist.
- Add "sdhci_hs200" property for HS200 supp

sdhci: ast2600: HS200 support porting

- Change eMMC clock src from HPLL to MPLL if SCU300[11] is set.
- Parse device related properties when they exist.
- Add "sdhci_hs200" property for HS200 support.
- Add "max-frequency" for assigning different frequency,
e.g., 100MHz.

Change-Id: Iad4ec6c54f26afd3d6db78cb5485ff6cabbf7dd3
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>

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clk: aspeed: fix rsa clock

Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com>

clk:aspeed

update fix axi ahb div calculate

fix AST2600A2 apll calculate

get mac delay configuration from device tree

correct format

Merge branch 'ryan_port' into aspeed-dev-v2019.04

update for patch

update for patch

update for patch

update for patch

update format for patch

update compile fail