1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 */ 5 6 #include <common.h> 7 #include <clk-uclass.h> 8 #include <dm.h> 9 #include <asm/io.h> 10 #include <dm/lists.h> 11 #include <asm/arch/scu_ast2600.h> 12 #include <dt-bindings/clock/ast2600-clock.h> 13 #include <dt-bindings/reset/ast2600-reset.h> 14 15 /* 16 * MAC Clock Delay settings 17 */ 18 #define RGMII_TXCLK_ODLY 8 19 #define RMII_RXCLK_IDLY 2 20 21 #define MAC_DEF_DELAY_1G 0x0041b75d 22 #define MAC_DEF_DELAY_100M 0x00417410 23 #define MAC_DEF_DELAY_10M 0x00417410 24 25 #define MAC34_DEF_DELAY_1G 0x0010438a 26 #define MAC34_DEF_DELAY_100M 0x00104208 27 #define MAC34_DEF_DELAY_10M 0x00104208 28 29 /* 30 * TGMII Clock Duty constants, taken from Aspeed SDK 31 */ 32 #define RGMII2_TXCK_DUTY 0x66 33 #define RGMII1_TXCK_DUTY 0x64 34 #define D2PLL_DEFAULT_RATE (250 * 1000 * 1000) 35 #define CHIP_REVISION_ID GENMASK(23, 16) 36 37 DECLARE_GLOBAL_DATA_PTR; 38 39 /* 40 * Clock divider/multiplier configuration struct. 41 * For H-PLL and M-PLL the formula is 42 * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1) 43 * M - Numerator 44 * N - Denumerator 45 * P - Post Divider 46 * They have the same layout in their control register. 47 * 48 * D-PLL and D2-PLL have extra divider (OD + 1), which is not 49 * yet needed and ignored by clock configurations. 50 */ 51 union ast2600_pll_reg { 52 u32 w; 53 struct { 54 unsigned int m : 13; /* bit[12:0] */ 55 unsigned int n : 6; /* bit[18:13] */ 56 unsigned int p : 4; /* bit[22:19] */ 57 unsigned int off : 1; /* bit[23] */ 58 unsigned int bypass : 1; /* bit[24] */ 59 unsigned int reset : 1; /* bit[25] */ 60 unsigned int reserved : 6; /* bit[31:26] */ 61 } b; 62 }; 63 64 struct ast2600_pll_cfg { 65 union ast2600_pll_reg reg; 66 u32 ext_reg; 67 }; 68 69 struct ast2600_pll_desc { 70 u32 in; 71 u32 out; 72 struct ast2600_pll_cfg cfg; 73 }; 74 75 static const struct ast2600_pll_desc ast2600_pll_lookup[] = { 76 { 77 .in = AST2600_CLK_IN, 78 .out = 400000000, 79 .cfg.reg.b.m = 95, 80 .cfg.reg.b.n = 2, 81 .cfg.reg.b.p = 1, 82 .cfg.ext_reg = 0x31, 83 }, { 84 .in = AST2600_CLK_IN, 85 .out = 200000000, 86 .cfg.reg.b.m = 127, 87 .cfg.reg.b.n = 0, 88 .cfg.reg.b.p = 15, 89 .cfg.ext_reg = 0x3f, 90 }, { 91 .in = AST2600_CLK_IN, 92 .out = 334000000, 93 .cfg.reg.b.m = 667, 94 .cfg.reg.b.n = 4, 95 .cfg.reg.b.p = 9, 96 .cfg.ext_reg = 0x14d, 97 }, { 98 .in = AST2600_CLK_IN, 99 .out = 1000000000, 100 .cfg.reg.b.m = 119, 101 .cfg.reg.b.n = 2, 102 .cfg.reg.b.p = 0, 103 .cfg.ext_reg = 0x3d, 104 }, { 105 .in = AST2600_CLK_IN, 106 .out = 50000000, 107 .cfg.reg.b.m = 95, 108 .cfg.reg.b.n = 2, 109 .cfg.reg.b.p = 15, 110 .cfg.ext_reg = 0x31, 111 }, 112 }; 113 114 union mac_delay_1g { 115 u32 w; 116 struct { 117 unsigned int tx_delay_1 : 6; /* bit[5:0] */ 118 unsigned int tx_delay_2 : 6; /* bit[11:6] */ 119 unsigned int rx_delay_1 : 6; /* bit[17:12] */ 120 unsigned int rx_delay_2 : 6; /* bit[23:18] */ 121 unsigned int rx_clk_inv_1 : 1; /* bit[24] */ 122 unsigned int rx_clk_inv_2 : 1; /* bit[25] */ 123 unsigned int rmii_tx_data_at_falling_1 : 1; /* bit[26] */ 124 unsigned int rmii_tx_data_at_falling_2 : 1; /* bit[27] */ 125 unsigned int rgmiick_pad_dir : 1; /* bit[28] */ 126 unsigned int rmii_50m_oe_1 : 1; /* bit[29] */ 127 unsigned int rmii_50m_oe_2 : 1; /* bit[30] */ 128 unsigned int rgmii_125m_o_sel : 1; /* bit[31] */ 129 } b; 130 }; 131 132 union mac_delay_100_10 { 133 u32 w; 134 struct { 135 unsigned int tx_delay_1 : 6; /* bit[5:0] */ 136 unsigned int tx_delay_2 : 6; /* bit[11:6] */ 137 unsigned int rx_delay_1 : 6; /* bit[17:12] */ 138 unsigned int rx_delay_2 : 6; /* bit[23:18] */ 139 unsigned int rx_clk_inv_1 : 1; /* bit[24] */ 140 unsigned int rx_clk_inv_2 : 1; /* bit[25] */ 141 unsigned int reserved_0 : 6; /* bit[31:26] */ 142 } b; 143 }; 144 145 struct mac_delay_config { 146 u32 tx_delay_1000; 147 u32 rx_delay_1000; 148 u32 tx_delay_100; 149 u32 rx_delay_100; 150 u32 tx_delay_10; 151 u32 rx_delay_10; 152 }; 153 154 extern u32 ast2600_get_pll_rate(struct ast2600_scu *scu, int pll_idx) 155 { 156 u32 clkin = AST2600_CLK_IN; 157 u32 pll_reg = 0; 158 unsigned int mult, div = 1; 159 160 switch (pll_idx) { 161 case ASPEED_CLK_HPLL: 162 pll_reg = readl(&scu->h_pll_param); 163 break; 164 case ASPEED_CLK_MPLL: 165 pll_reg = readl(&scu->m_pll_param); 166 break; 167 case ASPEED_CLK_DPLL: 168 pll_reg = readl(&scu->d_pll_param); 169 break; 170 case ASPEED_CLK_EPLL: 171 pll_reg = readl(&scu->e_pll_param); 172 break; 173 } 174 if (pll_reg & BIT(24)) { 175 /* Pass through mode */ 176 mult = 1; 177 div = 1; 178 } else { 179 union ast2600_pll_reg reg; 180 /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) 181 * HPLL Numerator (M) = fix 0x5F when SCU500[10]=1 182 * Fixed 0xBF when SCU500[10]=0 and SCU500[8]=1 183 * SCU200[12:0] (default 0x8F) when SCU510[10]=0 and SCU510[8]=0 184 * HPLL Denumerator (N) = SCU200[18:13] (default 0x2) 185 * HPLL Divider (P) = SCU200[22:19] (default 0x0) 186 * HPLL Bandwidth Adj (NB) = fix 0x2F when SCU500[10]=1 187 * Fixed 0x5F when SCU500[10]=0 and SCU500[8]=1 188 * SCU204[11:0] (default 0x31) when SCU500[10]=0 and SCU500[8]=0 189 */ 190 reg.w = pll_reg; 191 if (pll_idx == ASPEED_CLK_HPLL) { 192 u32 hwstrap1 = readl(&scu->hwstrap1.hwstrap); 193 194 if (hwstrap1 & BIT(10)) { 195 reg.b.m = 0x5F; 196 } else { 197 if (hwstrap1 & BIT(8)) 198 reg.b.m = 0xBF; 199 /* Otherwise keep default 0x8F */ 200 } 201 } 202 mult = (reg.b.m + 1) / (reg.b.n + 1); 203 div = (reg.b.p + 1); 204 } 205 206 return ((clkin * mult) / div); 207 } 208 209 extern u32 ast2600_get_apll_rate(struct ast2600_scu *scu) 210 { 211 u32 hw_rev = readl(&scu->chip_id1); 212 u32 clkin = AST2600_CLK_IN; 213 u32 apll_reg = readl(&scu->a_pll_param); 214 unsigned int mult, div = 1; 215 216 if (((hw_rev & CHIP_REVISION_ID) >> 16) >= 2) { 217 //after A2 version 218 if (apll_reg & BIT(24)) { 219 /* Pass through mode */ 220 mult = 1; 221 div = 1; 222 } else { 223 /* F = 25Mhz * [(m + 1) / (n + 1)] / (p + 1) */ 224 u32 m = apll_reg & 0x1fff; 225 u32 n = (apll_reg >> 13) & 0x3f; 226 u32 p = (apll_reg >> 19) & 0xf; 227 228 mult = (m + 1); 229 div = (n + 1) * (p + 1); 230 } 231 } else { 232 if (apll_reg & BIT(20)) { 233 /* Pass through mode */ 234 mult = 1; 235 div = 1; 236 } else { 237 /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */ 238 u32 m = (apll_reg >> 5) & 0x3f; 239 u32 od = (apll_reg >> 4) & 0x1; 240 u32 n = apll_reg & 0xf; 241 242 mult = (2 - od) * (m + 2); 243 div = n + 1; 244 } 245 } 246 247 return ((clkin * mult) / div); 248 } 249 250 static u32 ast2600_a0_axi_ahb_div_table[] = { 251 2, 252 2, 253 3, 254 4, 255 }; 256 257 static u32 ast2600_a1_axi_ahb_div0_table[] = { 258 3, 259 2, 260 3, 261 4, 262 }; 263 264 static u32 ast2600_a1_axi_ahb_div1_table[] = { 265 3, 266 4, 267 6, 268 8, 269 }; 270 271 static u32 ast2600_a1_axi_ahb_default_table[] = { 272 3, 4, 3, 4, 2, 2, 2, 2, 273 }; 274 275 static u32 ast2600_get_hclk(struct ast2600_scu *scu) 276 { 277 u32 hw_rev = readl(&scu->chip_id1); 278 u32 hwstrap1 = readl(&scu->hwstrap1.hwstrap); 279 u32 axi_div = 1; 280 u32 ahb_div = 0; 281 u32 rate = 0; 282 283 if ((hw_rev & CHIP_REVISION_ID) >> 16) { 284 //After A0 285 if (hwstrap1 & BIT(16)) { 286 ast2600_a1_axi_ahb_div1_table[0] = 287 ast2600_a1_axi_ahb_default_table[(hwstrap1 >> 8) & 288 0x7] * 2; 289 axi_div = 1; 290 ahb_div = 291 ast2600_a1_axi_ahb_div1_table[(hwstrap1 >> 11) & 292 0x3]; 293 } else { 294 ast2600_a1_axi_ahb_div0_table[0] = 295 ast2600_a1_axi_ahb_default_table[(hwstrap1 >> 8) & 296 0x7]; 297 axi_div = 2; 298 ahb_div = 299 ast2600_a1_axi_ahb_div0_table[(hwstrap1 >> 11) & 300 0x3]; 301 } 302 } else { 303 //A0 : fix axi = hpll / 2 304 axi_div = 2; 305 ahb_div = ast2600_a0_axi_ahb_div_table[(hwstrap1 >> 11) & 0x3]; 306 } 307 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 308 309 return (rate / axi_div / ahb_div); 310 } 311 312 static u32 ast2600_get_bclk_rate(struct ast2600_scu *scu) 313 { 314 u32 rate; 315 u32 bclk_sel = (readl(&scu->clk_sel1) >> 20) & 0x7; 316 317 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 318 319 return (rate / ((bclk_sel + 1) * 4)); 320 } 321 322 static u32 ast2600_hpll_pclk1_div_table[] = { 323 4, 8, 12, 16, 20, 24, 28, 32, 324 }; 325 326 static u32 ast2600_hpll_pclk2_div_table[] = { 327 2, 4, 6, 8, 10, 12, 14, 16, 328 }; 329 330 static u32 ast2600_get_pclk1(struct ast2600_scu *scu) 331 { 332 u32 clk_sel1 = readl(&scu->clk_sel1); 333 u32 apb_div = ast2600_hpll_pclk1_div_table[((clk_sel1 >> 23) & 0x7)]; 334 u32 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 335 336 return (rate / apb_div); 337 } 338 339 static u32 ast2600_get_pclk2(struct ast2600_scu *scu) 340 { 341 u32 clk_sel4 = readl(&scu->clk_sel4); 342 u32 apb_div = ast2600_hpll_pclk2_div_table[((clk_sel4 >> 9) & 0x7)]; 343 u32 rate = ast2600_get_hclk(scu); 344 345 return (rate / apb_div); 346 } 347 348 static u32 ast2600_get_uxclk_in_rate(struct ast2600_scu *scu) 349 { 350 u32 clk_in = 0; 351 u32 uxclk_sel = readl(&scu->clk_sel5); 352 353 uxclk_sel &= 0x3; 354 switch (uxclk_sel) { 355 case 0: 356 clk_in = ast2600_get_apll_rate(scu) / 4; 357 break; 358 case 1: 359 clk_in = ast2600_get_apll_rate(scu) / 2; 360 break; 361 case 2: 362 clk_in = ast2600_get_apll_rate(scu); 363 break; 364 case 3: 365 clk_in = ast2600_get_hclk(scu); 366 break; 367 } 368 369 return clk_in; 370 } 371 372 static u32 ast2600_get_huxclk_in_rate(struct ast2600_scu *scu) 373 { 374 u32 clk_in = 0; 375 u32 huclk_sel = readl(&scu->clk_sel5); 376 377 huclk_sel = ((huclk_sel >> 3) & 0x3); 378 switch (huclk_sel) { 379 case 0: 380 clk_in = ast2600_get_apll_rate(scu) / 4; 381 break; 382 case 1: 383 clk_in = ast2600_get_apll_rate(scu) / 2; 384 break; 385 case 2: 386 clk_in = ast2600_get_apll_rate(scu); 387 break; 388 case 3: 389 clk_in = ast2600_get_hclk(scu); 390 break; 391 } 392 393 return clk_in; 394 } 395 396 static u32 ast2600_get_uart_uxclk_rate(struct ast2600_scu *scu) 397 { 398 u32 clk_in = ast2600_get_uxclk_in_rate(scu); 399 u32 div_reg = readl(&scu->uart_24m_ref_uxclk); 400 unsigned int mult, div; 401 402 u32 n = (div_reg >> 8) & 0x3ff; 403 u32 r = div_reg & 0xff; 404 405 mult = r; 406 div = (n * 2); 407 return (clk_in * mult) / div; 408 } 409 410 static u32 ast2600_get_uart_huxclk_rate(struct ast2600_scu *scu) 411 { 412 u32 clk_in = ast2600_get_huxclk_in_rate(scu); 413 u32 div_reg = readl(&scu->uart_24m_ref_huxclk); 414 415 unsigned int mult, div; 416 417 u32 n = (div_reg >> 8) & 0x3ff; 418 u32 r = div_reg & 0xff; 419 420 mult = r; 421 div = (n * 2); 422 return (clk_in * mult) / div; 423 } 424 425 static u32 ast2600_get_sdio_clk_rate(struct ast2600_scu *scu) 426 { 427 u32 clkin = 0; 428 u32 clk_sel = readl(&scu->clk_sel4); 429 u32 div = (clk_sel >> 28) & 0x7; 430 431 if (clk_sel & BIT(8)) 432 clkin = ast2600_get_apll_rate(scu); 433 else 434 clkin = ast2600_get_hclk(scu); 435 436 div = (div + 1) << 1; 437 438 return (clkin / div); 439 } 440 441 static u32 ast2600_get_emmc_clk_rate(struct ast2600_scu *scu) 442 { 443 u32 clkin = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 444 u32 clk_sel = readl(&scu->clk_sel1); 445 u32 div = (clk_sel >> 12) & 0x7; 446 447 div = (div + 1) << 2; 448 449 return (clkin / div); 450 } 451 452 static u32 ast2600_get_uart_clk_rate(struct ast2600_scu *scu, int uart_idx) 453 { 454 u32 uart_sel = readl(&scu->clk_sel4); 455 u32 uart_sel5 = readl(&scu->clk_sel5); 456 ulong uart_clk = 0; 457 458 switch (uart_idx) { 459 case 1: 460 case 2: 461 case 3: 462 case 4: 463 case 6: 464 if (uart_sel & BIT(uart_idx - 1)) 465 uart_clk = ast2600_get_uart_huxclk_rate(scu); 466 else 467 uart_clk = ast2600_get_uart_uxclk_rate(scu); 468 break; 469 case 5: //24mhz is come form usb phy 48Mhz 470 { 471 u8 uart5_clk_sel = 0; 472 //high bit 473 if (readl(&scu->misc_ctrl1) & BIT(12)) 474 uart5_clk_sel = 0x2; 475 else 476 uart5_clk_sel = 0x0; 477 478 if (readl(&scu->clk_sel2) & BIT(14)) 479 uart5_clk_sel |= 0x1; 480 481 switch (uart5_clk_sel) { 482 case 0: 483 uart_clk = 24000000; 484 break; 485 case 1: 486 uart_clk = 192000000; 487 break; 488 case 2: 489 uart_clk = 24000000 / 13; 490 break; 491 case 3: 492 uart_clk = 192000000 / 13; 493 break; 494 } 495 } break; 496 case 7: 497 case 8: 498 case 9: 499 case 10: 500 case 11: 501 case 12: 502 case 13: 503 if (uart_sel5 & BIT(uart_idx - 1)) 504 uart_clk = ast2600_get_uart_huxclk_rate(scu); 505 else 506 uart_clk = ast2600_get_uart_uxclk_rate(scu); 507 break; 508 } 509 510 return uart_clk; 511 } 512 513 static ulong ast2600_clk_get_rate(struct clk *clk) 514 { 515 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 516 ulong rate = 0; 517 518 switch (clk->id) { 519 case ASPEED_CLK_HPLL: 520 case ASPEED_CLK_EPLL: 521 case ASPEED_CLK_DPLL: 522 case ASPEED_CLK_MPLL: 523 rate = ast2600_get_pll_rate(priv->scu, clk->id); 524 break; 525 case ASPEED_CLK_AHB: 526 rate = ast2600_get_hclk(priv->scu); 527 break; 528 case ASPEED_CLK_APB1: 529 rate = ast2600_get_pclk1(priv->scu); 530 break; 531 case ASPEED_CLK_APB2: 532 rate = ast2600_get_pclk2(priv->scu); 533 break; 534 case ASPEED_CLK_APLL: 535 rate = ast2600_get_apll_rate(priv->scu); 536 break; 537 case ASPEED_CLK_GATE_UART1CLK: 538 rate = ast2600_get_uart_clk_rate(priv->scu, 1); 539 break; 540 case ASPEED_CLK_GATE_UART2CLK: 541 rate = ast2600_get_uart_clk_rate(priv->scu, 2); 542 break; 543 case ASPEED_CLK_GATE_UART3CLK: 544 rate = ast2600_get_uart_clk_rate(priv->scu, 3); 545 break; 546 case ASPEED_CLK_GATE_UART4CLK: 547 rate = ast2600_get_uart_clk_rate(priv->scu, 4); 548 break; 549 case ASPEED_CLK_GATE_UART5CLK: 550 rate = ast2600_get_uart_clk_rate(priv->scu, 5); 551 break; 552 case ASPEED_CLK_BCLK: 553 rate = ast2600_get_bclk_rate(priv->scu); 554 break; 555 case ASPEED_CLK_SDIO: 556 rate = ast2600_get_sdio_clk_rate(priv->scu); 557 break; 558 case ASPEED_CLK_EMMC: 559 rate = ast2600_get_emmc_clk_rate(priv->scu); 560 break; 561 case ASPEED_CLK_UARTX: 562 rate = ast2600_get_uart_uxclk_rate(priv->scu); 563 break; 564 case ASPEED_CLK_HUARTX: 565 rate = ast2600_get_uart_huxclk_rate(priv->scu); 566 break; 567 default: 568 pr_debug("can't get clk rate\n"); 569 return -ENOENT; 570 } 571 572 return rate; 573 } 574 575 /** 576 * @brief lookup PLL divider config by input/output rate 577 * @param[in] *pll - PLL descriptor 578 * @return true - if PLL divider config is found, false - else 579 * The function caller shall fill "pll->in" and "pll->out", 580 * then this function will search the lookup table 581 * to find a valid PLL divider configuration. 582 */ 583 static bool ast2600_search_clock_config(struct ast2600_pll_desc *pll) 584 { 585 u32 i; 586 bool is_found = false; 587 588 for (i = 0; i < ARRAY_SIZE(ast2600_pll_lookup); i++) { 589 const struct ast2600_pll_desc *def_cfg = &ast2600_pll_lookup[i]; 590 591 if (def_cfg->in == pll->in && def_cfg->out == pll->out) { 592 is_found = true; 593 pll->cfg.reg.w = def_cfg->cfg.reg.w; 594 pll->cfg.ext_reg = def_cfg->cfg.ext_reg; 595 break; 596 } 597 } 598 return is_found; 599 } 600 601 static u32 ast2600_configure_pll(struct ast2600_scu *scu, 602 struct ast2600_pll_cfg *p_cfg, int pll_idx) 603 { 604 u32 addr, addr_ext; 605 u32 reg; 606 607 switch (pll_idx) { 608 case ASPEED_CLK_HPLL: 609 addr = (u32)(&scu->h_pll_param); 610 addr_ext = (u32)(&scu->h_pll_ext_param); 611 break; 612 case ASPEED_CLK_MPLL: 613 addr = (u32)(&scu->m_pll_param); 614 addr_ext = (u32)(&scu->m_pll_ext_param); 615 break; 616 case ASPEED_CLK_DPLL: 617 addr = (u32)(&scu->d_pll_param); 618 addr_ext = (u32)(&scu->d_pll_ext_param); 619 break; 620 case ASPEED_CLK_EPLL: 621 addr = (u32)(&scu->e_pll_param); 622 addr_ext = (u32)(&scu->e_pll_ext_param); 623 break; 624 default: 625 debug("unknown PLL index\n"); 626 return 1; 627 } 628 629 p_cfg->reg.b.bypass = 0; 630 p_cfg->reg.b.off = 1; 631 p_cfg->reg.b.reset = 1; 632 633 reg = readl(addr); 634 reg &= ~GENMASK(25, 0); 635 reg |= p_cfg->reg.w; 636 writel(reg, addr); 637 638 /* write extend parameter */ 639 writel(p_cfg->ext_reg, addr_ext); 640 udelay(100); 641 p_cfg->reg.b.off = 0; 642 p_cfg->reg.b.reset = 0; 643 reg &= ~GENMASK(25, 0); 644 reg |= p_cfg->reg.w; 645 writel(reg, addr); 646 while (!(readl(addr_ext) & BIT(31))) 647 ; 648 649 return 0; 650 } 651 652 static u32 ast2600_configure_ddr(struct ast2600_scu *scu, ulong rate) 653 { 654 struct ast2600_pll_desc mpll; 655 656 mpll.in = AST2600_CLK_IN; 657 mpll.out = rate; 658 if (ast2600_search_clock_config(&mpll) == false) { 659 printf("error!! unable to find valid DDR clock setting\n"); 660 return 0; 661 } 662 ast2600_configure_pll(scu, &mpll.cfg, ASPEED_CLK_MPLL); 663 664 return ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL); 665 } 666 667 static ulong ast2600_clk_set_rate(struct clk *clk, ulong rate) 668 { 669 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 670 ulong new_rate; 671 672 switch (clk->id) { 673 case ASPEED_CLK_MPLL: 674 new_rate = ast2600_configure_ddr(priv->scu, rate); 675 break; 676 default: 677 return -ENOENT; 678 } 679 680 return new_rate; 681 } 682 683 #define SCU_CLKSTOP_MAC1 (20) 684 #define SCU_CLKSTOP_MAC2 (21) 685 #define SCU_CLKSTOP_MAC3 (20) 686 #define SCU_CLKSTOP_MAC4 (21) 687 688 static u32 ast2600_configure_mac12_clk(struct ast2600_scu *scu, struct udevice *dev) 689 { 690 union mac_delay_1g reg_1g; 691 union mac_delay_100_10 reg_100, reg_10; 692 struct mac_delay_config mac1_cfg, mac2_cfg; 693 int ret; 694 695 reg_1g.w = (readl(&scu->mac12_clk_delay) & ~GENMASK(25, 0)) | 696 MAC_DEF_DELAY_1G; 697 reg_100.w = MAC_DEF_DELAY_100M; 698 reg_10.w = MAC_DEF_DELAY_10M; 699 700 ret = dev_read_u32_array(dev, "mac0-clk-delay", (u32 *)&mac1_cfg, sizeof(mac1_cfg) / sizeof(u32)); 701 if (!ret) { 702 reg_1g.b.tx_delay_1 = mac1_cfg.tx_delay_1000; 703 reg_1g.b.rx_delay_1 = mac1_cfg.rx_delay_1000; 704 reg_100.b.tx_delay_1 = mac1_cfg.tx_delay_100; 705 reg_100.b.rx_delay_1 = mac1_cfg.rx_delay_100; 706 reg_10.b.tx_delay_1 = mac1_cfg.tx_delay_10; 707 reg_10.b.rx_delay_1 = mac1_cfg.rx_delay_10; 708 } 709 710 ret = dev_read_u32_array(dev, "mac1-clk-delay", (u32 *)&mac2_cfg, sizeof(mac2_cfg) / sizeof(u32)); 711 if (!ret) { 712 reg_1g.b.tx_delay_2 = mac2_cfg.tx_delay_1000; 713 reg_1g.b.rx_delay_2 = mac2_cfg.rx_delay_1000; 714 reg_100.b.tx_delay_2 = mac2_cfg.tx_delay_100; 715 reg_100.b.rx_delay_2 = mac2_cfg.rx_delay_100; 716 reg_10.b.tx_delay_2 = mac2_cfg.tx_delay_10; 717 reg_10.b.rx_delay_2 = mac2_cfg.rx_delay_10; 718 } 719 720 writel(reg_1g.w, &scu->mac12_clk_delay); 721 writel(reg_100.w, &scu->mac12_clk_delay_100M); 722 writel(reg_10.w, &scu->mac12_clk_delay_10M); 723 724 /* MAC AHB = HPLL / 6 */ 725 clrsetbits_le32(&scu->clk_sel1, GENMASK(18, 16), (0x2 << 16)); 726 727 return 0; 728 } 729 730 static u32 ast2600_configure_mac34_clk(struct ast2600_scu *scu, struct udevice *dev) 731 { 732 union mac_delay_1g reg_1g; 733 union mac_delay_100_10 reg_100, reg_10; 734 struct mac_delay_config mac3_cfg, mac4_cfg; 735 int ret; 736 737 /* 738 * scu350[31] RGMII 125M source: 0 = from IO pin 739 * scu350[25:0] MAC 1G delay 740 */ 741 reg_1g.w = (readl(&scu->mac34_clk_delay) & ~GENMASK(25, 0)) | 742 MAC34_DEF_DELAY_1G; 743 reg_1g.b.rgmii_125m_o_sel = 0; 744 reg_100.w = MAC34_DEF_DELAY_100M; 745 reg_10.w = MAC34_DEF_DELAY_10M; 746 747 ret = dev_read_u32_array(dev, "mac2-clk-delay", (u32 *)&mac3_cfg, sizeof(mac3_cfg) / sizeof(u32)); 748 if (!ret) { 749 reg_1g.b.tx_delay_1 = mac3_cfg.tx_delay_1000; 750 reg_1g.b.rx_delay_1 = mac3_cfg.rx_delay_1000; 751 reg_100.b.tx_delay_1 = mac3_cfg.tx_delay_100; 752 reg_100.b.rx_delay_1 = mac3_cfg.rx_delay_100; 753 reg_10.b.tx_delay_1 = mac3_cfg.tx_delay_10; 754 reg_10.b.rx_delay_1 = mac3_cfg.rx_delay_10; 755 } 756 757 ret = dev_read_u32_array(dev, "mac3-clk-delay", (u32 *)&mac4_cfg, sizeof(mac4_cfg) / sizeof(u32)); 758 if (!ret) { 759 reg_1g.b.tx_delay_2 = mac4_cfg.tx_delay_1000; 760 reg_1g.b.rx_delay_2 = mac4_cfg.rx_delay_1000; 761 reg_100.b.tx_delay_2 = mac4_cfg.tx_delay_100; 762 reg_100.b.rx_delay_2 = mac4_cfg.rx_delay_100; 763 reg_10.b.tx_delay_2 = mac4_cfg.tx_delay_10; 764 reg_10.b.rx_delay_2 = mac4_cfg.rx_delay_10; 765 } 766 767 writel(reg_1g.w, &scu->mac34_clk_delay); 768 writel(reg_100.w, &scu->mac34_clk_delay_100M); 769 writel(reg_10.w, &scu->mac34_clk_delay_10M); 770 771 /* 772 * clock source seletion and divider 773 * scu310[26:24] : MAC AHB bus clock = HCLK / 2 774 * scu310[18:16] : RMII 50M = HCLK_200M / 4 775 */ 776 clrsetbits_le32(&scu->clk_sel4, (GENMASK(26, 24) | GENMASK(18, 16)), 777 ((0x0 << 24) | (0x3 << 16))); 778 779 /* 780 * set driving strength 781 * scu458[3:2] : MAC4 driving strength 782 * scu458[1:0] : MAC3 driving strength 783 */ 784 clrsetbits_le32(&scu->pinmux_ctrl16, GENMASK(3, 0), 785 (0x3 << 2) | (0x3 << 0)); 786 787 return 0; 788 } 789 790 /** 791 * ast2600 RGMII clock source tree 792 * 125M from external PAD -------->|\ 793 * HPLL -->|\ | |---->RGMII 125M for MAC#1 & MAC#2 794 * | |---->| divider |---->|/ + 795 * EPLL -->|/ | 796 * | 797 * +---------<-----------|RGMIICK PAD output enable|<-------------+ 798 * | 799 * +--------------------------->|\ 800 * | |----> RGMII 125M for MAC#3 & MAC#4 801 * HCLK 200M ---->|divider|---->|/ 802 * To simplify the control flow: 803 * 1. RGMII 1/2 always use EPLL as the internal clock source 804 * 2. RGMII 3/4 always use RGMIICK pad as the RGMII 125M source 805 * 125M from external PAD -------->|\ 806 * | |---->RGMII 125M for MAC#1 & MAC#2 807 * EPLL---->| divider |--->|/ + 808 * | 809 * +<--------------------|RGMIICK PAD output enable|<-------------+ 810 * | 811 * +--------------------------->RGMII 125M for MAC#3 & MAC#4 812 */ 813 #define RGMIICK_SRC_PAD 0 814 #define RGMIICK_SRC_EPLL 1 /* recommended */ 815 #define RGMIICK_SRC_HPLL 2 816 817 #define RGMIICK_DIV2 1 818 #define RGMIICK_DIV3 2 819 #define RGMIICK_DIV4 3 820 #define RGMIICK_DIV5 4 821 #define RGMIICK_DIV6 5 822 #define RGMIICK_DIV7 6 823 #define RGMIICK_DIV8 7 /* recommended */ 824 825 #define RMIICK_DIV4 0 826 #define RMIICK_DIV8 1 827 #define RMIICK_DIV12 2 828 #define RMIICK_DIV16 3 829 #define RMIICK_DIV20 4 /* recommended */ 830 #define RMIICK_DIV24 5 831 #define RMIICK_DIV28 6 832 #define RMIICK_DIV32 7 833 834 struct ast2600_mac_clk_div { 835 u32 src; /* 0=external PAD, 1=internal PLL */ 836 u32 fin; /* divider input speed */ 837 u32 n; /* 0=div2, 1=div2, 2=div3, 3=div4,...,7=div8 */ 838 u32 fout; /* fout = fin / n */ 839 }; 840 841 struct ast2600_mac_clk_div rgmii_clk_defconfig = { 842 .src = ASPEED_CLK_EPLL, 843 .fin = 1000000000, 844 .n = RGMIICK_DIV8, 845 .fout = 125000000, 846 }; 847 848 struct ast2600_mac_clk_div rmii_clk_defconfig = { 849 .src = ASPEED_CLK_EPLL, 850 .fin = 1000000000, 851 .n = RMIICK_DIV20, 852 .fout = 50000000, 853 }; 854 855 static void ast2600_init_mac_pll(struct ast2600_scu *p_scu, 856 struct ast2600_mac_clk_div *p_cfg) 857 { 858 struct ast2600_pll_desc pll; 859 860 pll.in = AST2600_CLK_IN; 861 pll.out = p_cfg->fin; 862 if (ast2600_search_clock_config(&pll) == false) { 863 pr_err("unable to find valid ETHNET MAC clock setting\n"); 864 debug("%s: pll cfg = 0x%08x 0x%08x\n", __func__, pll.cfg.reg.w, 865 pll.cfg.ext_reg); 866 debug("%s: pll cfg = %02x %02x %02x\n", __func__, 867 pll.cfg.reg.b.m, pll.cfg.reg.b.n, pll.cfg.reg.b.p); 868 return; 869 } 870 ast2600_configure_pll(p_scu, &pll.cfg, p_cfg->src); 871 } 872 873 static void ast2600_init_rgmii_clk(struct ast2600_scu *p_scu, 874 struct ast2600_mac_clk_div *p_cfg) 875 { 876 u32 reg_304 = readl(&p_scu->clk_sel2); 877 u32 reg_340 = readl(&p_scu->mac12_clk_delay); 878 u32 reg_350 = readl(&p_scu->mac34_clk_delay); 879 880 reg_340 &= ~GENMASK(31, 29); 881 /* scu340[28]: RGMIICK PAD output enable (to MAC 3/4) */ 882 reg_340 |= BIT(28); 883 if (p_cfg->src == ASPEED_CLK_EPLL || p_cfg->src == ASPEED_CLK_HPLL) { 884 /* 885 * re-init PLL if the current PLL output frequency doesn't match 886 * the divider setting 887 */ 888 if (p_cfg->fin != ast2600_get_pll_rate(p_scu, p_cfg->src)) 889 ast2600_init_mac_pll(p_scu, p_cfg); 890 /* scu340[31]: select RGMII 125M from internal source */ 891 reg_340 |= BIT(31); 892 } 893 894 reg_304 &= ~GENMASK(23, 20); 895 896 /* set clock divider */ 897 reg_304 |= (p_cfg->n & 0x7) << 20; 898 899 /* select internal clock source */ 900 if (p_cfg->src == ASPEED_CLK_HPLL) 901 reg_304 |= BIT(23); 902 903 /* RGMII 3/4 clock source select */ 904 reg_350 &= ~BIT(31); 905 906 writel(reg_304, &p_scu->clk_sel2); 907 writel(reg_340, &p_scu->mac12_clk_delay); 908 writel(reg_350, &p_scu->mac34_clk_delay); 909 } 910 911 /** 912 * ast2600 RMII/NCSI clock source tree 913 * HPLL -->|\ 914 * | |---->| divider |----> RMII 50M for MAC#1 & MAC#2 915 * EPLL -->|/ 916 * HCLK(SCLICLK)---->| divider |----> RMII 50M for MAC#3 & MAC#4 917 */ 918 static void ast2600_init_rmii_clk(struct ast2600_scu *p_scu, 919 struct ast2600_mac_clk_div *p_cfg) 920 { 921 u32 reg_304; 922 u32 reg_310; 923 924 if (p_cfg->src == ASPEED_CLK_EPLL || p_cfg->src == ASPEED_CLK_HPLL) { 925 /* 926 * re-init PLL if the current PLL output frequency doesn't match 927 * the divider setting 928 */ 929 if (p_cfg->fin != ast2600_get_pll_rate(p_scu, p_cfg->src)) 930 ast2600_init_mac_pll(p_scu, p_cfg); 931 } 932 933 reg_304 = readl(&p_scu->clk_sel2); 934 reg_310 = readl(&p_scu->clk_sel4); 935 936 reg_304 &= ~GENMASK(19, 16); 937 938 /* set RMII 1/2 clock divider */ 939 reg_304 |= (p_cfg->n & 0x7) << 16; 940 941 /* RMII clock source selection */ 942 if (p_cfg->src == ASPEED_CLK_HPLL) 943 reg_304 |= BIT(19); 944 945 /* set RMII 3/4 clock divider */ 946 reg_310 &= ~GENMASK(18, 16); 947 reg_310 |= (0x3 << 16); 948 949 writel(reg_304, &p_scu->clk_sel2); 950 writel(reg_310, &p_scu->clk_sel4); 951 } 952 953 static u32 ast2600_configure_mac(struct ast2600_scu *scu, int index) 954 { 955 u32 reset_bit; 956 u32 clkstop_bit; 957 958 switch (index) { 959 case 1: 960 reset_bit = BIT(ASPEED_RESET_MAC1); 961 clkstop_bit = BIT(SCU_CLKSTOP_MAC1); 962 writel(reset_bit, &scu->sysreset_ctrl1); 963 udelay(100); 964 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 965 mdelay(10); 966 writel(reset_bit, &scu->sysreset_clr_ctrl1); 967 break; 968 case 2: 969 reset_bit = BIT(ASPEED_RESET_MAC2); 970 clkstop_bit = BIT(SCU_CLKSTOP_MAC2); 971 writel(reset_bit, &scu->sysreset_ctrl1); 972 udelay(100); 973 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 974 mdelay(10); 975 writel(reset_bit, &scu->sysreset_clr_ctrl1); 976 break; 977 case 3: 978 reset_bit = BIT(ASPEED_RESET_MAC3 - 32); 979 clkstop_bit = BIT(SCU_CLKSTOP_MAC3); 980 writel(reset_bit, &scu->sysreset_ctrl2); 981 udelay(100); 982 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 983 mdelay(10); 984 writel(reset_bit, &scu->sysreset_clr_ctrl2); 985 break; 986 case 4: 987 reset_bit = BIT(ASPEED_RESET_MAC4 - 32); 988 clkstop_bit = BIT(SCU_CLKSTOP_MAC4); 989 writel(reset_bit, &scu->sysreset_ctrl2); 990 udelay(100); 991 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 992 mdelay(10); 993 writel(reset_bit, &scu->sysreset_clr_ctrl2); 994 break; 995 default: 996 return -EINVAL; 997 } 998 999 return 0; 1000 } 1001 1002 #define SCU_CLK_ECC_RSA_FROM_HPLL_CLK BIT(19) 1003 #define SCU_CLK_ECC_RSA_CLK_MASK GENMASK(27, 26) 1004 #define SCU_CLK_ECC_RSA_CLK_DIV(x) ((x) << 26) 1005 static void ast2600_configure_rsa_ecc_clk(struct ast2600_scu *scu) 1006 { 1007 u32 clk_sel = readl(&scu->clk_sel1); 1008 1009 /* Configure RSA clock = HPLL/4 */ 1010 clk_sel |= SCU_CLK_ECC_RSA_FROM_HPLL_CLK; 1011 clk_sel &= ~SCU_CLK_ECC_RSA_CLK_MASK; 1012 clk_sel |= SCU_CLK_ECC_RSA_CLK_DIV(3); 1013 1014 writel(clk_sel, &scu->clk_sel1); 1015 } 1016 1017 #define SCU_CLKSTOP_SDIO 4 1018 static ulong ast2600_enable_sdclk(struct ast2600_scu *scu) 1019 { 1020 u32 reset_bit; 1021 u32 clkstop_bit; 1022 1023 reset_bit = BIT(ASPEED_RESET_SD - 32); 1024 clkstop_bit = BIT(SCU_CLKSTOP_SDIO); 1025 1026 writel(reset_bit, &scu->sysreset_ctrl2); 1027 1028 udelay(100); 1029 //enable clk 1030 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 1031 mdelay(10); 1032 writel(reset_bit, &scu->sysreset_clr_ctrl2); 1033 1034 return 0; 1035 } 1036 1037 #define SCU_CLKSTOP_EXTSD 31 1038 #define SCU_CLK_SD_MASK (0x7 << 28) 1039 #define SCU_CLK_SD_DIV(x) ((x) << 28) 1040 #define SCU_CLK_SD_FROM_APLL_CLK BIT(8) 1041 1042 static ulong ast2600_enable_extsdclk(struct ast2600_scu *scu) 1043 { 1044 u32 clk_sel = readl(&scu->clk_sel4); 1045 u32 enableclk_bit; 1046 u32 rate = 0; 1047 u32 div = 0; 1048 int i = 0; 1049 1050 enableclk_bit = BIT(SCU_CLKSTOP_EXTSD); 1051 1052 /* ast2600 sd controller max clk is 200Mhz : 1053 * use apll for clock source 800/4 = 200 : controller max is 200mhz 1054 */ 1055 rate = ast2600_get_apll_rate(scu); 1056 for (i = 0; i < 8; i++) { 1057 div = (i + 1) * 2; 1058 if ((rate / div) <= 200000000) 1059 break; 1060 } 1061 clk_sel &= ~SCU_CLK_SD_MASK; 1062 clk_sel |= SCU_CLK_SD_DIV(i) | SCU_CLK_SD_FROM_APLL_CLK; 1063 writel(clk_sel, &scu->clk_sel4); 1064 1065 //enable clk 1066 setbits_le32(&scu->clk_sel4, enableclk_bit); 1067 1068 return 0; 1069 } 1070 1071 #define SCU_CLKSTOP_EMMC 27 1072 static ulong ast2600_enable_emmcclk(struct ast2600_scu *scu) 1073 { 1074 u32 reset_bit; 1075 u32 clkstop_bit; 1076 1077 reset_bit = BIT(ASPEED_RESET_EMMC); 1078 clkstop_bit = BIT(SCU_CLKSTOP_EMMC); 1079 1080 writel(reset_bit, &scu->sysreset_ctrl1); 1081 udelay(100); 1082 //enable clk 1083 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 1084 mdelay(10); 1085 writel(reset_bit, &scu->sysreset_clr_ctrl1); 1086 1087 return 0; 1088 } 1089 1090 #define SCU_CLKSTOP_EXTEMMC 15 1091 #define SCU_CLK_EMMC_MASK (0x7 << 12) 1092 #define SCU_CLK_EMMC_DIV(x) ((x) << 12) 1093 #define SCU_CLK_EMMC_FROM_MPLL_CLK BIT(11) 1094 1095 static ulong ast2600_enable_extemmcclk(struct ast2600_scu *scu) 1096 { 1097 u32 revision_id = readl(&scu->chip_id1); 1098 u32 clk_sel = readl(&scu->clk_sel1); 1099 u32 enableclk_bit = BIT(SCU_CLKSTOP_EXTEMMC); 1100 u32 rate = 0; 1101 u32 div = 0; 1102 int i = 0; 1103 1104 /* 1105 * ast2600 eMMC controller max clk is 200Mhz 1106 * HPll->1/2->|\ 1107 * |->SCU300[11]->SCU300[14:12][1/N] + 1108 * MPLL------>|/ | 1109 * +----------------------------------------------+ 1110 * | 1111 * +---------> EMMC12C[15:8][1/N]-> eMMC clk 1112 */ 1113 if (((revision_id & CHIP_REVISION_ID) >> 16)) { 1114 //AST2600A1 : use mpll to be clk source 1115 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL); 1116 for (i = 0; i < 8; i++) { 1117 div = (i + 1) * 2; 1118 if ((rate / div) <= 200000000) 1119 break; 1120 } 1121 1122 clk_sel &= ~SCU_CLK_EMMC_MASK; 1123 clk_sel |= SCU_CLK_EMMC_DIV(i) | SCU_CLK_EMMC_FROM_MPLL_CLK; 1124 writel(clk_sel, &scu->clk_sel1); 1125 1126 } else { 1127 //AST2600A0 : use hpll to be clk source 1128 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 1129 1130 for (i = 0; i < 8; i++) { 1131 div = (i + 1) * 4; 1132 if ((rate / div) <= 200000000) 1133 break; 1134 } 1135 1136 clk_sel &= ~SCU_CLK_EMMC_MASK; 1137 clk_sel |= SCU_CLK_EMMC_DIV(i); 1138 writel(clk_sel, &scu->clk_sel1); 1139 } 1140 setbits_le32(&scu->clk_sel1, enableclk_bit); 1141 1142 return 0; 1143 } 1144 1145 #define SCU_CLKSTOP_FSICLK 30 1146 1147 static ulong ast2600_enable_fsiclk(struct ast2600_scu *scu) 1148 { 1149 u32 reset_bit; 1150 u32 clkstop_bit; 1151 1152 reset_bit = BIT(ASPEED_RESET_FSI % 32); 1153 clkstop_bit = BIT(SCU_CLKSTOP_FSICLK); 1154 1155 /* The FSI clock is shared between masters. If it's already on 1156 * don't touch it, as that will reset the existing master. 1157 */ 1158 if (!(readl(&scu->clk_stop_ctrl2) & clkstop_bit)) { 1159 debug("%s: already running, not touching it\n", __func__); 1160 return 0; 1161 } 1162 1163 writel(reset_bit, &scu->sysreset_ctrl2); 1164 udelay(100); 1165 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 1166 mdelay(10); 1167 writel(reset_bit, &scu->sysreset_clr_ctrl2); 1168 1169 return 0; 1170 } 1171 1172 static ulong ast2600_enable_usbahclk(struct ast2600_scu *scu) 1173 { 1174 u32 reset_bit; 1175 u32 clkstop_bit; 1176 1177 reset_bit = BIT(ASPEED_RESET_EHCI_P1); 1178 clkstop_bit = BIT(14); 1179 1180 writel(reset_bit, &scu->sysreset_ctrl1); 1181 udelay(100); 1182 writel(clkstop_bit, &scu->clk_stop_ctrl1); 1183 mdelay(20); 1184 writel(reset_bit, &scu->sysreset_clr_ctrl1); 1185 1186 return 0; 1187 } 1188 1189 static ulong ast2600_enable_usbbhclk(struct ast2600_scu *scu) 1190 { 1191 u32 reset_bit; 1192 u32 clkstop_bit; 1193 1194 reset_bit = BIT(ASPEED_RESET_EHCI_P2); 1195 clkstop_bit = BIT(7); 1196 1197 writel(reset_bit, &scu->sysreset_ctrl1); 1198 udelay(100); 1199 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 1200 mdelay(20); 1201 1202 writel(reset_bit, &scu->sysreset_clr_ctrl1); 1203 1204 return 0; 1205 } 1206 1207 static int ast2600_clk_enable(struct clk *clk) 1208 { 1209 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 1210 1211 switch (clk->id) { 1212 case ASPEED_CLK_GATE_MAC1CLK: 1213 ast2600_configure_mac(priv->scu, 1); 1214 break; 1215 case ASPEED_CLK_GATE_MAC2CLK: 1216 ast2600_configure_mac(priv->scu, 2); 1217 break; 1218 case ASPEED_CLK_GATE_MAC3CLK: 1219 ast2600_configure_mac(priv->scu, 3); 1220 break; 1221 case ASPEED_CLK_GATE_MAC4CLK: 1222 ast2600_configure_mac(priv->scu, 4); 1223 break; 1224 case ASPEED_CLK_GATE_SDCLK: 1225 ast2600_enable_sdclk(priv->scu); 1226 break; 1227 case ASPEED_CLK_GATE_SDEXTCLK: 1228 ast2600_enable_extsdclk(priv->scu); 1229 break; 1230 case ASPEED_CLK_GATE_EMMCCLK: 1231 ast2600_enable_emmcclk(priv->scu); 1232 break; 1233 case ASPEED_CLK_GATE_EMMCEXTCLK: 1234 ast2600_enable_extemmcclk(priv->scu); 1235 break; 1236 case ASPEED_CLK_GATE_FSICLK: 1237 ast2600_enable_fsiclk(priv->scu); 1238 break; 1239 case ASPEED_CLK_GATE_USBPORT1CLK: 1240 ast2600_enable_usbahclk(priv->scu); 1241 break; 1242 case ASPEED_CLK_GATE_USBPORT2CLK: 1243 ast2600_enable_usbbhclk(priv->scu); 1244 break; 1245 default: 1246 pr_err("can't enable clk\n"); 1247 return -ENOENT; 1248 } 1249 1250 return 0; 1251 } 1252 1253 struct clk_ops ast2600_clk_ops = { 1254 .get_rate = ast2600_clk_get_rate, 1255 .set_rate = ast2600_clk_set_rate, 1256 .enable = ast2600_clk_enable, 1257 }; 1258 1259 static int ast2600_clk_probe(struct udevice *dev) 1260 { 1261 struct ast2600_clk_priv *priv = dev_get_priv(dev); 1262 u32 uart_clk_source; 1263 1264 priv->scu = devfdt_get_addr_ptr(dev); 1265 if (IS_ERR(priv->scu)) 1266 return PTR_ERR(priv->scu); 1267 1268 uart_clk_source = dev_read_u32_default(dev, "uart-clk-source", 0x0); 1269 1270 if (uart_clk_source) { 1271 if (uart_clk_source & GENMASK(5, 0)) 1272 setbits_le32(&priv->scu->clk_sel4, 1273 uart_clk_source & GENMASK(5, 0)); 1274 if (uart_clk_source & GENMASK(12, 6)) 1275 setbits_le32(&priv->scu->clk_sel5, 1276 uart_clk_source & GENMASK(12, 6)); 1277 } 1278 1279 ast2600_init_rgmii_clk(priv->scu, &rgmii_clk_defconfig); 1280 ast2600_init_rmii_clk(priv->scu, &rmii_clk_defconfig); 1281 ast2600_configure_mac12_clk(priv->scu, dev); 1282 ast2600_configure_mac34_clk(priv->scu, dev); 1283 ast2600_configure_rsa_ecc_clk(priv->scu); 1284 1285 return 0; 1286 } 1287 1288 static int ast2600_clk_bind(struct udevice *dev) 1289 { 1290 int ret; 1291 1292 /* The reset driver does not have a device node, so bind it here */ 1293 ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev); 1294 if (ret) 1295 debug("Warning: No reset driver: ret=%d\n", ret); 1296 1297 return 0; 1298 } 1299 1300 struct aspeed_clks { 1301 ulong id; 1302 const char *name; 1303 }; 1304 1305 static struct aspeed_clks aspeed_clk_names[] = { 1306 { ASPEED_CLK_HPLL, "hpll" }, { ASPEED_CLK_MPLL, "mpll" }, 1307 { ASPEED_CLK_APLL, "apll" }, { ASPEED_CLK_EPLL, "epll" }, 1308 { ASPEED_CLK_DPLL, "dpll" }, { ASPEED_CLK_AHB, "hclk" }, 1309 { ASPEED_CLK_APB1, "pclk1" }, { ASPEED_CLK_APB2, "pclk2" }, 1310 { ASPEED_CLK_BCLK, "bclk" }, { ASPEED_CLK_UARTX, "uxclk" }, 1311 { ASPEED_CLK_HUARTX, "huxclk" }, 1312 }; 1313 1314 int soc_clk_dump(void) 1315 { 1316 struct udevice *dev; 1317 struct clk clk; 1318 unsigned long rate; 1319 int i, ret; 1320 1321 ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu), 1322 &dev); 1323 if (ret) 1324 return ret; 1325 1326 printf("Clk\t\tHz\n"); 1327 1328 for (i = 0; i < ARRAY_SIZE(aspeed_clk_names); i++) { 1329 clk.id = aspeed_clk_names[i].id; 1330 ret = clk_request(dev, &clk); 1331 if (ret < 0) { 1332 debug("%s clk_request() failed: %d\n", __func__, ret); 1333 continue; 1334 } 1335 1336 ret = clk_get_rate(&clk); 1337 rate = ret; 1338 1339 clk_free(&clk); 1340 1341 if (ret == -ENOTSUPP) { 1342 printf("clk ID %lu not supported yet\n", 1343 aspeed_clk_names[i].id); 1344 continue; 1345 } 1346 if (ret < 0) { 1347 printf("%s %lu: get_rate err: %d\n", __func__, 1348 aspeed_clk_names[i].id, ret); 1349 continue; 1350 } 1351 1352 printf("%s(%3lu):\t%lu\n", aspeed_clk_names[i].name, 1353 aspeed_clk_names[i].id, rate); 1354 } 1355 1356 return 0; 1357 } 1358 1359 static const struct udevice_id ast2600_clk_ids[] = { 1360 { 1361 .compatible = "aspeed,ast2600-scu", 1362 }, 1363 {} 1364 }; 1365 1366 U_BOOT_DRIVER(aspeed_scu) = { 1367 .name = "aspeed_scu", 1368 .id = UCLASS_CLK, 1369 .of_match = ast2600_clk_ids, 1370 .priv_auto_alloc_size = sizeof(struct ast2600_clk_priv), 1371 .ops = &ast2600_clk_ops, 1372 .bind = ast2600_clk_bind, 1373 .probe = ast2600_clk_probe, 1374 }; 1375