1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 */ 5 6 #include <common.h> 7 #include <clk-uclass.h> 8 #include <dm.h> 9 #include <asm/io.h> 10 #include <dm/lists.h> 11 #include <asm/arch/scu_ast2600.h> 12 #include <dt-bindings/clock/ast2600-clock.h> 13 #include <dt-bindings/reset/ast2600-reset.h> 14 15 /* 16 * MAC Clock Delay settings 17 */ 18 #define RGMII_TXCLK_ODLY 8 19 #define RMII_RXCLK_IDLY 2 20 21 #define MAC_DEF_DELAY_1G 0x0041b75d 22 #define MAC_DEF_DELAY_100M 0x00417410 23 #define MAC_DEF_DELAY_10M 0x00417410 24 25 #define MAC34_DEF_DELAY_1G 0x0010438a 26 #define MAC34_DEF_DELAY_100M 0x00104208 27 #define MAC34_DEF_DELAY_10M 0x00104208 28 29 /* 30 * TGMII Clock Duty constants, taken from Aspeed SDK 31 */ 32 #define RGMII2_TXCK_DUTY 0x66 33 #define RGMII1_TXCK_DUTY 0x64 34 #define D2PLL_DEFAULT_RATE (250 * 1000 * 1000) 35 #define CHIP_REVISION_ID GENMASK(23, 16) 36 37 DECLARE_GLOBAL_DATA_PTR; 38 39 /* 40 * Clock divider/multiplier configuration struct. 41 * For H-PLL and M-PLL the formula is 42 * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1) 43 * M - Numerator 44 * N - Denumerator 45 * P - Post Divider 46 * They have the same layout in their control register. 47 * 48 * D-PLL and D2-PLL have extra divider (OD + 1), which is not 49 * yet needed and ignored by clock configurations. 50 */ 51 union ast2600_pll_reg { 52 unsigned int w; 53 struct { 54 unsigned int m : 13; /* bit[12:0] */ 55 unsigned int n : 6; /* bit[18:13] */ 56 unsigned int p : 4; /* bit[22:19] */ 57 unsigned int off : 1; /* bit[23] */ 58 unsigned int bypass : 1; /* bit[24] */ 59 unsigned int reset : 1; /* bit[25] */ 60 unsigned int reserved : 6; /* bit[31:26] */ 61 } b; 62 }; 63 64 struct ast2600_pll_cfg { 65 union ast2600_pll_reg reg; 66 unsigned int ext_reg; 67 }; 68 69 struct ast2600_pll_desc { 70 u32 in; 71 u32 out; 72 struct ast2600_pll_cfg cfg; 73 }; 74 75 static const struct ast2600_pll_desc ast2600_pll_lookup[] = { 76 { 77 .in = AST2600_CLK_IN, 78 .out = 400000000, 79 .cfg.reg.b.m = 95, 80 .cfg.reg.b.n = 2, 81 .cfg.reg.b.p = 1, 82 .cfg.ext_reg = 0x31, 83 }, 84 { .in = AST2600_CLK_IN, 85 .out = 200000000, 86 .cfg.reg.b.m = 127, 87 .cfg.reg.b.n = 0, 88 .cfg.reg.b.p = 15, 89 .cfg.ext_reg = 0x3f }, 90 { .in = AST2600_CLK_IN, 91 .out = 334000000, 92 .cfg.reg.b.m = 667, 93 .cfg.reg.b.n = 4, 94 .cfg.reg.b.p = 9, 95 .cfg.ext_reg = 0x14d }, 96 { .in = AST2600_CLK_IN, 97 .out = 1000000000, 98 .cfg.reg.b.m = 119, 99 .cfg.reg.b.n = 2, 100 .cfg.reg.b.p = 0, 101 .cfg.ext_reg = 0x3d }, 102 { .in = AST2600_CLK_IN, 103 .out = 50000000, 104 .cfg.reg.b.m = 95, 105 .cfg.reg.b.n = 2, 106 .cfg.reg.b.p = 15, 107 .cfg.ext_reg = 0x31 }, 108 }; 109 110 extern u32 ast2600_get_pll_rate(struct ast2600_scu *scu, int pll_idx) 111 { 112 u32 clkin = AST2600_CLK_IN; 113 u32 pll_reg = 0; 114 unsigned int mult, div = 1; 115 116 switch (pll_idx) { 117 case ASPEED_CLK_HPLL: 118 pll_reg = readl(&scu->h_pll_param); 119 break; 120 case ASPEED_CLK_MPLL: 121 pll_reg = readl(&scu->m_pll_param); 122 break; 123 case ASPEED_CLK_DPLL: 124 pll_reg = readl(&scu->d_pll_param); 125 break; 126 case ASPEED_CLK_EPLL: 127 pll_reg = readl(&scu->e_pll_param); 128 break; 129 } 130 if (pll_reg & BIT(24)) { 131 /* Pass through mode */ 132 mult = 1; 133 div = 1; 134 } else { 135 union ast2600_pll_reg reg; 136 /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) 137 * HPLL Numerator (M) = fix 0x5F when SCU500[10]=1 138 * Fixed 0xBF when SCU500[10]=0 and SCU500[8]=1 139 * SCU200[12:0] (default 0x8F) when SCU510[10]=0 and SCU510[8]=0 140 * HPLL Denumerator (N) = SCU200[18:13] (default 0x2) 141 * HPLL Divider (P) = SCU200[22:19] (default 0x0) 142 * HPLL Bandwidth Adj (NB) = fix 0x2F when SCU500[10]=1 143 * Fixed 0x5F when SCU500[10]=0 and SCU500[8]=1 144 * SCU204[11:0] (default 0x31) when SCU500[10]=0 and SCU500[8]=0 145 */ 146 reg.w = pll_reg; 147 if (pll_idx == ASPEED_CLK_HPLL) { 148 u32 hwstrap1 = readl(&scu->hwstrap1.hwstrap); 149 150 if (hwstrap1 & BIT(10)) { 151 reg.b.m = 0x5F; 152 } else { 153 if (hwstrap1 & BIT(8)) 154 reg.b.m = 0xBF; 155 /* Otherwise keep default 0x8F */ 156 } 157 } 158 mult = (reg.b.m + 1) / (reg.b.n + 1); 159 div = (reg.b.p + 1); 160 } 161 162 return ((clkin * mult) / div); 163 } 164 165 extern u32 ast2600_get_apll_rate(struct ast2600_scu *scu) 166 { 167 u32 hw_rev = readl(&scu->chip_id1); 168 u32 clkin = AST2600_CLK_IN; 169 u32 apll_reg = readl(&scu->a_pll_param); 170 unsigned int mult, div = 1; 171 172 if (((hw_rev & CHIP_REVISION_ID) >> 16) >= 3) { 173 //after A2 version 174 if (apll_reg & BIT(24)) { 175 /* Pass through mode */ 176 mult = 1; 177 div = 1; 178 } else { 179 /* F = 25Mhz * [(m + 1) / (n + 1)] / (p + 1) */ 180 u32 m = apll_reg & 0x1fff; 181 u32 n = (apll_reg >> 13) & 0x3f; 182 u32 p = (apll_reg >> 19) & 0xf; 183 184 mult = (m + 1); 185 div = (n + 1) * (p + 1); 186 } 187 188 } else { 189 if (apll_reg & BIT(20)) { 190 /* Pass through mode */ 191 mult = 1; 192 div = 1; 193 } else { 194 /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */ 195 u32 m = (apll_reg >> 5) & 0x3f; 196 u32 od = (apll_reg >> 4) & 0x1; 197 u32 n = apll_reg & 0xf; 198 199 mult = (2 - od) * (m + 2); 200 div = n + 1; 201 } 202 } 203 204 return ((clkin * mult) / div); 205 } 206 207 static u32 ast2600_a0_axi_ahb_div_table[] = { 208 2, 209 2, 210 3, 211 4, 212 }; 213 214 static u32 ast2600_a1_axi_ahb_div0_table[] = { 215 3, 216 2, 217 3, 218 4, 219 }; 220 221 static u32 ast2600_a1_axi_ahb_div1_table[] = { 222 3, 223 4, 224 6, 225 8, 226 }; 227 228 static u32 ast2600_a1_axi_ahb_default_table[] = { 229 3, 4, 3, 4, 2, 2, 2, 2, 230 }; 231 232 static u32 ast2600_get_hclk(struct ast2600_scu *scu) 233 { 234 u32 hw_rev = readl(&scu->chip_id1); 235 u32 hwstrap1 = readl(&scu->hwstrap1.hwstrap); 236 u32 axi_div = 1; 237 u32 ahb_div = 0; 238 u32 rate = 0; 239 240 if ((hw_rev & CHIP_REVISION_ID) >> 16) { 241 //After A0 242 if (hwstrap1 & BIT(16)) { 243 ast2600_a1_axi_ahb_div1_table[0] = 244 ast2600_a1_axi_ahb_default_table[(hwstrap1 >> 8) & 245 0x3]; 246 axi_div = 1; 247 ahb_div = 248 ast2600_a1_axi_ahb_div1_table[(hwstrap1 >> 11) & 249 0x3]; 250 } else { 251 ast2600_a1_axi_ahb_div0_table[0] = 252 ast2600_a1_axi_ahb_default_table[(hwstrap1 >> 8) & 253 0x3]; 254 axi_div = 2; 255 ahb_div = 256 ast2600_a1_axi_ahb_div0_table[(hwstrap1 >> 11) & 257 0x3]; 258 } 259 } else { 260 //A0 : fix axi = hpll / 2 261 axi_div = 2; 262 ahb_div = ast2600_a0_axi_ahb_div_table[(hwstrap1 >> 11) & 0x3]; 263 } 264 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 265 266 return (rate / axi_div / ahb_div); 267 } 268 269 static u32 ast2600_get_bclk_rate(struct ast2600_scu *scu) 270 { 271 u32 rate; 272 u32 bclk_sel = (readl(&scu->clk_sel1) >> 20) & 0x7; 273 274 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 275 276 return (rate / ((bclk_sel + 1) * 4)); 277 } 278 279 static u32 ast2600_hpll_pclk1_div_table[] = { 280 4, 8, 12, 16, 20, 24, 28, 32, 281 }; 282 283 static u32 ast2600_hpll_pclk2_div_table[] = { 284 2, 4, 6, 8, 10, 12, 14, 16, 285 }; 286 287 static u32 ast2600_get_pclk1(struct ast2600_scu *scu) 288 { 289 u32 clk_sel1 = readl(&scu->clk_sel1); 290 u32 apb_div = ast2600_hpll_pclk1_div_table[((clk_sel1 >> 23) & 0x7)]; 291 u32 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 292 293 return (rate / apb_div); 294 } 295 296 static u32 ast2600_get_pclk2(struct ast2600_scu *scu) 297 { 298 u32 clk_sel4 = readl(&scu->clk_sel4); 299 u32 apb_div = ast2600_hpll_pclk2_div_table[((clk_sel4 >> 9) & 0x7)]; 300 u32 rate = ast2600_get_hclk(scu); 301 302 return (rate / apb_div); 303 } 304 305 static u32 ast2600_get_uxclk_in_rate(struct ast2600_scu *scu) 306 { 307 u32 clk_in = 0; 308 u32 uxclk_sel = readl(&scu->clk_sel5); 309 310 uxclk_sel &= 0x3; 311 switch (uxclk_sel) { 312 case 0: 313 clk_in = ast2600_get_apll_rate(scu) / 4; 314 break; 315 case 1: 316 clk_in = ast2600_get_apll_rate(scu) / 2; 317 break; 318 case 2: 319 clk_in = ast2600_get_apll_rate(scu); 320 break; 321 case 3: 322 clk_in = ast2600_get_hclk(scu); 323 break; 324 } 325 326 return clk_in; 327 } 328 329 static u32 ast2600_get_huxclk_in_rate(struct ast2600_scu *scu) 330 { 331 u32 clk_in = 0; 332 u32 huclk_sel = readl(&scu->clk_sel5); 333 334 huclk_sel = ((huclk_sel >> 3) & 0x3); 335 switch (huclk_sel) { 336 case 0: 337 clk_in = ast2600_get_apll_rate(scu) / 4; 338 break; 339 case 1: 340 clk_in = ast2600_get_apll_rate(scu) / 2; 341 break; 342 case 2: 343 clk_in = ast2600_get_apll_rate(scu); 344 break; 345 case 3: 346 clk_in = ast2600_get_hclk(scu); 347 break; 348 } 349 350 return clk_in; 351 } 352 353 static u32 ast2600_get_uart_uxclk_rate(struct ast2600_scu *scu) 354 { 355 u32 clk_in = ast2600_get_uxclk_in_rate(scu); 356 u32 div_reg = readl(&scu->uart_24m_ref_uxclk); 357 unsigned int mult, div; 358 359 u32 n = (div_reg >> 8) & 0x3ff; 360 u32 r = div_reg & 0xff; 361 362 mult = r; 363 div = (n * 2); 364 return (clk_in * mult) / div; 365 } 366 367 static u32 ast2600_get_uart_huxclk_rate(struct ast2600_scu *scu) 368 { 369 u32 clk_in = ast2600_get_huxclk_in_rate(scu); 370 u32 div_reg = readl(&scu->uart_24m_ref_huxclk); 371 372 unsigned int mult, div; 373 374 u32 n = (div_reg >> 8) & 0x3ff; 375 u32 r = div_reg & 0xff; 376 377 mult = r; 378 div = (n * 2); 379 return (clk_in * mult) / div; 380 } 381 382 static u32 ast2600_get_sdio_clk_rate(struct ast2600_scu *scu) 383 { 384 u32 clkin = 0; 385 u32 clk_sel = readl(&scu->clk_sel4); 386 u32 div = (clk_sel >> 28) & 0x7; 387 388 if (clk_sel & BIT(8)) 389 clkin = ast2600_get_apll_rate(scu); 390 else 391 clkin = ast2600_get_hclk(scu); 392 393 div = (div + 1) << 1; 394 395 return (clkin / div); 396 } 397 398 static u32 ast2600_get_emmc_clk_rate(struct ast2600_scu *scu) 399 { 400 u32 clkin = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 401 u32 clk_sel = readl(&scu->clk_sel1); 402 u32 div = (clk_sel >> 12) & 0x7; 403 404 div = (div + 1) << 2; 405 406 return (clkin / div); 407 } 408 409 static u32 ast2600_get_uart_clk_rate(struct ast2600_scu *scu, int uart_idx) 410 { 411 u32 uart_sel = readl(&scu->clk_sel4); 412 u32 uart_sel5 = readl(&scu->clk_sel5); 413 ulong uart_clk = 0; 414 415 switch (uart_idx) { 416 case 1: 417 case 2: 418 case 3: 419 case 4: 420 case 6: 421 if (uart_sel & BIT(uart_idx - 1)) 422 uart_clk = ast2600_get_uart_huxclk_rate(scu); 423 else 424 uart_clk = ast2600_get_uart_uxclk_rate(scu); 425 break; 426 case 5: //24mhz is come form usb phy 48Mhz 427 { 428 u8 uart5_clk_sel = 0; 429 //high bit 430 if (readl(&scu->misc_ctrl1) & BIT(12)) 431 uart5_clk_sel = 0x2; 432 else 433 uart5_clk_sel = 0x0; 434 435 if (readl(&scu->clk_sel2) & BIT(14)) 436 uart5_clk_sel |= 0x1; 437 438 switch (uart5_clk_sel) { 439 case 0: 440 uart_clk = 24000000; 441 break; 442 case 1: 443 uart_clk = 192000000; 444 break; 445 case 2: 446 uart_clk = 24000000 / 13; 447 break; 448 case 3: 449 uart_clk = 192000000 / 13; 450 break; 451 } 452 } break; 453 case 7: 454 case 8: 455 case 9: 456 case 10: 457 case 11: 458 case 12: 459 case 13: 460 if (uart_sel5 & BIT(uart_idx - 1)) 461 uart_clk = ast2600_get_uart_huxclk_rate(scu); 462 else 463 uart_clk = ast2600_get_uart_uxclk_rate(scu); 464 break; 465 } 466 467 return uart_clk; 468 } 469 470 static ulong ast2600_clk_get_rate(struct clk *clk) 471 { 472 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 473 ulong rate = 0; 474 475 switch (clk->id) { 476 case ASPEED_CLK_HPLL: 477 case ASPEED_CLK_EPLL: 478 case ASPEED_CLK_DPLL: 479 case ASPEED_CLK_MPLL: 480 rate = ast2600_get_pll_rate(priv->scu, clk->id); 481 break; 482 case ASPEED_CLK_AHB: 483 rate = ast2600_get_hclk(priv->scu); 484 break; 485 case ASPEED_CLK_APB1: 486 rate = ast2600_get_pclk1(priv->scu); 487 break; 488 case ASPEED_CLK_APB2: 489 rate = ast2600_get_pclk2(priv->scu); 490 break; 491 case ASPEED_CLK_APLL: 492 rate = ast2600_get_apll_rate(priv->scu); 493 break; 494 case ASPEED_CLK_GATE_UART1CLK: 495 rate = ast2600_get_uart_clk_rate(priv->scu, 1); 496 break; 497 case ASPEED_CLK_GATE_UART2CLK: 498 rate = ast2600_get_uart_clk_rate(priv->scu, 2); 499 break; 500 case ASPEED_CLK_GATE_UART3CLK: 501 rate = ast2600_get_uart_clk_rate(priv->scu, 3); 502 break; 503 case ASPEED_CLK_GATE_UART4CLK: 504 rate = ast2600_get_uart_clk_rate(priv->scu, 4); 505 break; 506 case ASPEED_CLK_GATE_UART5CLK: 507 rate = ast2600_get_uart_clk_rate(priv->scu, 5); 508 break; 509 case ASPEED_CLK_BCLK: 510 rate = ast2600_get_bclk_rate(priv->scu); 511 break; 512 case ASPEED_CLK_SDIO: 513 rate = ast2600_get_sdio_clk_rate(priv->scu); 514 break; 515 case ASPEED_CLK_EMMC: 516 rate = ast2600_get_emmc_clk_rate(priv->scu); 517 break; 518 case ASPEED_CLK_UARTX: 519 rate = ast2600_get_uart_uxclk_rate(priv->scu); 520 break; 521 case ASPEED_CLK_HUARTX: 522 rate = ast2600_get_uart_huxclk_rate(priv->scu); 523 break; 524 default: 525 pr_debug("can't get clk rate\n"); 526 return -ENOENT; 527 } 528 529 return rate; 530 } 531 532 /** 533 * @brief lookup PLL divider config by input/output rate 534 * @param[in] *pll - PLL descriptor 535 * @return true - if PLL divider config is found, false - else 536 * The function caller shall fill "pll->in" and "pll->out", 537 * then this function will search the lookup table 538 * to find a valid PLL divider configuration. 539 */ 540 static bool ast2600_search_clock_config(struct ast2600_pll_desc *pll) 541 { 542 u32 i; 543 bool is_found = false; 544 545 for (i = 0; i < ARRAY_SIZE(ast2600_pll_lookup); i++) { 546 const struct ast2600_pll_desc *def_cfg = &ast2600_pll_lookup[i]; 547 548 if (def_cfg->in == pll->in && def_cfg->out == pll->out) { 549 is_found = true; 550 pll->cfg.reg.w = def_cfg->cfg.reg.w; 551 pll->cfg.ext_reg = def_cfg->cfg.ext_reg; 552 break; 553 } 554 } 555 return is_found; 556 } 557 558 static u32 ast2600_configure_pll(struct ast2600_scu *scu, 559 struct ast2600_pll_cfg *p_cfg, int pll_idx) 560 { 561 u32 addr, addr_ext; 562 u32 reg; 563 564 switch (pll_idx) { 565 case ASPEED_CLK_HPLL: 566 addr = (u32)(&scu->h_pll_param); 567 addr_ext = (u32)(&scu->h_pll_ext_param); 568 break; 569 case ASPEED_CLK_MPLL: 570 addr = (u32)(&scu->m_pll_param); 571 addr_ext = (u32)(&scu->m_pll_ext_param); 572 break; 573 case ASPEED_CLK_DPLL: 574 addr = (u32)(&scu->d_pll_param); 575 addr_ext = (u32)(&scu->d_pll_ext_param); 576 break; 577 case ASPEED_CLK_EPLL: 578 addr = (u32)(&scu->e_pll_param); 579 addr_ext = (u32)(&scu->e_pll_ext_param); 580 break; 581 default: 582 debug("unknown PLL index\n"); 583 return 1; 584 } 585 586 p_cfg->reg.b.bypass = 0; 587 p_cfg->reg.b.off = 1; 588 p_cfg->reg.b.reset = 1; 589 590 reg = readl(addr); 591 reg &= ~GENMASK(25, 0); 592 reg |= p_cfg->reg.w; 593 writel(reg, addr); 594 595 /* write extend parameter */ 596 writel(p_cfg->ext_reg, addr_ext); 597 udelay(100); 598 p_cfg->reg.b.off = 0; 599 p_cfg->reg.b.reset = 0; 600 reg &= ~GENMASK(25, 0); 601 reg |= p_cfg->reg.w; 602 writel(reg, addr); 603 while (!(readl(addr_ext) & BIT(31))) 604 ; 605 606 return 0; 607 } 608 609 static u32 ast2600_configure_ddr(struct ast2600_scu *scu, ulong rate) 610 { 611 struct ast2600_pll_desc mpll; 612 613 mpll.in = AST2600_CLK_IN; 614 mpll.out = rate; 615 if (ast2600_search_clock_config(&mpll) == false) { 616 printf("error!! unable to find valid DDR clock setting\n"); 617 return 0; 618 } 619 ast2600_configure_pll(scu, &mpll.cfg, ASPEED_CLK_MPLL); 620 621 return ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL); 622 } 623 624 static ulong ast2600_clk_set_rate(struct clk *clk, ulong rate) 625 { 626 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 627 ulong new_rate; 628 629 switch (clk->id) { 630 case ASPEED_CLK_MPLL: 631 new_rate = ast2600_configure_ddr(priv->scu, rate); 632 break; 633 default: 634 return -ENOENT; 635 } 636 637 return new_rate; 638 } 639 640 #define SCU_CLKSTOP_MAC1 (20) 641 #define SCU_CLKSTOP_MAC2 (21) 642 #define SCU_CLKSTOP_MAC3 (20) 643 #define SCU_CLKSTOP_MAC4 (21) 644 645 static u32 ast2600_configure_mac12_clk(struct ast2600_scu *scu) 646 { 647 /* scu340[25:0]: 1G default delay */ 648 clrsetbits_le32(&scu->mac12_clk_delay, GENMASK(25, 0), 649 MAC_DEF_DELAY_1G); 650 651 /* set 100M/10M default delay */ 652 writel(MAC_DEF_DELAY_100M, &scu->mac12_clk_delay_100M); 653 writel(MAC_DEF_DELAY_10M, &scu->mac12_clk_delay_10M); 654 655 /* MAC AHB = HPLL / 6 */ 656 clrsetbits_le32(&scu->clk_sel1, GENMASK(18, 16), (0x2 << 16)); 657 658 return 0; 659 } 660 661 static u32 ast2600_configure_mac34_clk(struct ast2600_scu *scu) 662 { 663 /* 664 * scu350[31] RGMII 125M source: 0 = from IO pin 665 * scu350[25:0] MAC 1G delay 666 */ 667 clrsetbits_le32(&scu->mac34_clk_delay, (BIT(31) | GENMASK(25, 0)), 668 MAC34_DEF_DELAY_1G); 669 writel(MAC34_DEF_DELAY_100M, &scu->mac34_clk_delay_100M); 670 writel(MAC34_DEF_DELAY_10M, &scu->mac34_clk_delay_10M); 671 672 /* 673 * clock source seletion and divider 674 * scu310[26:24] : MAC AHB bus clock = HCLK / 2 675 * scu310[18:16] : RMII 50M = HCLK_200M / 4 676 */ 677 clrsetbits_le32(&scu->clk_sel4, (GENMASK(26, 24) | GENMASK(18, 16)), 678 ((0x0 << 24) | (0x3 << 16))); 679 680 /* 681 * set driving strength 682 * scu458[3:2] : MAC4 driving strength 683 * scu458[1:0] : MAC3 driving strength 684 */ 685 clrsetbits_le32(&scu->pinmux_ctrl16, GENMASK(3, 0), 686 (0x3 << 2) | (0x3 << 0)); 687 688 return 0; 689 } 690 691 /** 692 * ast2600 RGMII clock source tree 693 * 125M from external PAD -------->|\ 694 * HPLL -->|\ | |---->RGMII 125M for MAC#1 & MAC#2 695 * | |---->| divider |---->|/ + 696 * EPLL -->|/ | 697 * | 698 * +---------<-----------|RGMIICK PAD output enable|<-------------+ 699 * | 700 * +--------------------------->|\ 701 * | |----> RGMII 125M for MAC#3 & MAC#4 702 * HCLK 200M ---->|divider|---->|/ 703 * To simplify the control flow: 704 * 1. RGMII 1/2 always use EPLL as the internal clock source 705 * 2. RGMII 3/4 always use RGMIICK pad as the RGMII 125M source 706 * 125M from external PAD -------->|\ 707 * | |---->RGMII 125M for MAC#1 & MAC#2 708 * EPLL---->| divider |--->|/ + 709 * | 710 * +<--------------------|RGMIICK PAD output enable|<-------------+ 711 * | 712 * +--------------------------->RGMII 125M for MAC#3 & MAC#4 713 */ 714 #define RGMIICK_SRC_PAD 0 715 #define RGMIICK_SRC_EPLL 1 /* recommended */ 716 #define RGMIICK_SRC_HPLL 2 717 718 #define RGMIICK_DIV2 1 719 #define RGMIICK_DIV3 2 720 #define RGMIICK_DIV4 3 721 #define RGMIICK_DIV5 4 722 #define RGMIICK_DIV6 5 723 #define RGMIICK_DIV7 6 724 #define RGMIICK_DIV8 7 /* recommended */ 725 726 #define RMIICK_DIV4 0 727 #define RMIICK_DIV8 1 728 #define RMIICK_DIV12 2 729 #define RMIICK_DIV16 3 730 #define RMIICK_DIV20 4 /* recommended */ 731 #define RMIICK_DIV24 5 732 #define RMIICK_DIV28 6 733 #define RMIICK_DIV32 7 734 735 struct ast2600_mac_clk_div { 736 u32 src; /* 0=external PAD, 1=internal PLL */ 737 u32 fin; /* divider input speed */ 738 u32 n; /* 0=div2, 1=div2, 2=div3, 3=div4,...,7=div8 */ 739 u32 fout; /* fout = fin / n */ 740 }; 741 742 struct ast2600_mac_clk_div rgmii_clk_defconfig = { 743 .src = ASPEED_CLK_EPLL, 744 .fin = 1000000000, 745 .n = RGMIICK_DIV8, 746 .fout = 125000000, 747 }; 748 749 struct ast2600_mac_clk_div rmii_clk_defconfig = { 750 .src = ASPEED_CLK_EPLL, 751 .fin = 1000000000, 752 .n = RMIICK_DIV20, 753 .fout = 50000000, 754 }; 755 756 static void ast2600_init_mac_pll(struct ast2600_scu *p_scu, 757 struct ast2600_mac_clk_div *p_cfg) 758 { 759 struct ast2600_pll_desc pll; 760 761 pll.in = AST2600_CLK_IN; 762 pll.out = p_cfg->fin; 763 if (ast2600_search_clock_config(&pll) == false) { 764 pr_err("unable to find valid ETHNET MAC clock setting\n"); 765 debug("%s: pll cfg = 0x%08x 0x%08x\n", __func__, pll.cfg.reg.w, 766 pll.cfg.ext_reg); 767 debug("%s: pll cfg = %02x %02x %02x\n", __func__, 768 pll.cfg.reg.b.m, pll.cfg.reg.b.n, pll.cfg.reg.b.p); 769 return; 770 } 771 ast2600_configure_pll(p_scu, &pll.cfg, p_cfg->src); 772 } 773 774 static void ast2600_init_rgmii_clk(struct ast2600_scu *p_scu, 775 struct ast2600_mac_clk_div *p_cfg) 776 { 777 u32 reg_304 = readl(&p_scu->clk_sel2); 778 u32 reg_340 = readl(&p_scu->mac12_clk_delay); 779 u32 reg_350 = readl(&p_scu->mac34_clk_delay); 780 781 reg_340 &= ~GENMASK(31, 29); 782 /* scu340[28]: RGMIICK PAD output enable (to MAC 3/4) */ 783 reg_340 |= BIT(28); 784 if (p_cfg->src == ASPEED_CLK_EPLL || p_cfg->src == ASPEED_CLK_HPLL) { 785 /* 786 * re-init PLL if the current PLL output frequency doesn't match 787 * the divider setting 788 */ 789 if (p_cfg->fin != ast2600_get_pll_rate(p_scu, p_cfg->src)) 790 ast2600_init_mac_pll(p_scu, p_cfg); 791 /* scu340[31]: select RGMII 125M from internal source */ 792 reg_340 |= BIT(31); 793 } 794 795 reg_304 &= ~GENMASK(23, 20); 796 797 /* set clock divider */ 798 reg_304 |= (p_cfg->n & 0x7) << 20; 799 800 /* select internal clock source */ 801 if (p_cfg->src == ASPEED_CLK_HPLL) 802 reg_304 |= BIT(23); 803 804 /* RGMII 3/4 clock source select */ 805 reg_350 &= ~BIT(31); 806 807 writel(reg_304, &p_scu->clk_sel2); 808 writel(reg_340, &p_scu->mac12_clk_delay); 809 writel(reg_350, &p_scu->mac34_clk_delay); 810 } 811 812 /** 813 * ast2600 RMII/NCSI clock source tree 814 * HPLL -->|\ 815 * | |---->| divider |----> RMII 50M for MAC#1 & MAC#2 816 * EPLL -->|/ 817 * HCLK(SCLICLK)---->| divider |----> RMII 50M for MAC#3 & MAC#4 818 */ 819 static void ast2600_init_rmii_clk(struct ast2600_scu *p_scu, 820 struct ast2600_mac_clk_div *p_cfg) 821 { 822 u32 reg_304; 823 u32 reg_310; 824 825 if (p_cfg->src == ASPEED_CLK_EPLL || p_cfg->src == ASPEED_CLK_HPLL) { 826 /* 827 * re-init PLL if the current PLL output frequency doesn't match 828 * the divider setting 829 */ 830 if (p_cfg->fin != ast2600_get_pll_rate(p_scu, p_cfg->src)) 831 ast2600_init_mac_pll(p_scu, p_cfg); 832 } 833 834 reg_304 = readl(&p_scu->clk_sel2); 835 reg_310 = readl(&p_scu->clk_sel4); 836 837 reg_304 &= ~GENMASK(19, 16); 838 839 /* set RMII 1/2 clock divider */ 840 reg_304 |= (p_cfg->n & 0x7) << 16; 841 842 /* RMII clock source selection */ 843 if (p_cfg->src == ASPEED_CLK_HPLL) 844 reg_304 |= BIT(19); 845 846 /* set RMII 3/4 clock divider */ 847 reg_310 &= ~GENMASK(18, 16); 848 reg_310 |= (0x3 << 16); 849 850 writel(reg_304, &p_scu->clk_sel2); 851 writel(reg_310, &p_scu->clk_sel4); 852 } 853 854 static u32 ast2600_configure_mac(struct ast2600_scu *scu, int index) 855 { 856 u32 reset_bit; 857 u32 clkstop_bit; 858 859 switch (index) { 860 case 1: 861 reset_bit = BIT(ASPEED_RESET_MAC1); 862 clkstop_bit = BIT(SCU_CLKSTOP_MAC1); 863 writel(reset_bit, &scu->sysreset_ctrl1); 864 udelay(100); 865 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 866 mdelay(10); 867 writel(reset_bit, &scu->sysreset_clr_ctrl1); 868 break; 869 case 2: 870 reset_bit = BIT(ASPEED_RESET_MAC2); 871 clkstop_bit = BIT(SCU_CLKSTOP_MAC2); 872 writel(reset_bit, &scu->sysreset_ctrl1); 873 udelay(100); 874 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 875 mdelay(10); 876 writel(reset_bit, &scu->sysreset_clr_ctrl1); 877 break; 878 case 3: 879 reset_bit = BIT(ASPEED_RESET_MAC3 - 32); 880 clkstop_bit = BIT(SCU_CLKSTOP_MAC3); 881 writel(reset_bit, &scu->sysreset_ctrl2); 882 udelay(100); 883 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 884 mdelay(10); 885 writel(reset_bit, &scu->sysreset_clr_ctrl2); 886 break; 887 case 4: 888 reset_bit = BIT(ASPEED_RESET_MAC4 - 32); 889 clkstop_bit = BIT(SCU_CLKSTOP_MAC4); 890 writel(reset_bit, &scu->sysreset_ctrl2); 891 udelay(100); 892 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 893 mdelay(10); 894 writel(reset_bit, &scu->sysreset_clr_ctrl2); 895 break; 896 default: 897 return -EINVAL; 898 } 899 900 return 0; 901 } 902 903 #define SCU_CLK_ECC_RSA_FROM_HPLL_CLK BIT(19) 904 #define SCU_CLK_ECC_RSA_CLK_MASK GENMASK(27, 26) 905 #define SCU_CLK_ECC_RSA_CLK_DIV(x) ((x) << 26) 906 static void ast2600_configure_rsa_ecc_clk(struct ast2600_scu *scu) 907 { 908 u32 clk_sel = readl(&scu->clk_sel1); 909 910 /* Configure RSA clock = HPLL/3 */ 911 clk_sel |= SCU_CLK_ECC_RSA_FROM_HPLL_CLK; 912 clk_sel &= ~SCU_CLK_ECC_RSA_CLK_MASK; 913 clk_sel |= SCU_CLK_ECC_RSA_CLK_DIV(2); 914 915 writel(clk_sel, &scu->clk_sel1); 916 } 917 918 #define SCU_CLKSTOP_SDIO 4 919 static ulong ast2600_enable_sdclk(struct ast2600_scu *scu) 920 { 921 u32 reset_bit; 922 u32 clkstop_bit; 923 924 reset_bit = BIT(ASPEED_RESET_SD - 32); 925 clkstop_bit = BIT(SCU_CLKSTOP_SDIO); 926 927 writel(reset_bit, &scu->sysreset_ctrl2); 928 929 udelay(100); 930 //enable clk 931 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 932 mdelay(10); 933 writel(reset_bit, &scu->sysreset_clr_ctrl2); 934 935 return 0; 936 } 937 938 #define SCU_CLKSTOP_EXTSD 31 939 #define SCU_CLK_SD_MASK (0x7 << 28) 940 #define SCU_CLK_SD_DIV(x) ((x) << 28) 941 #define SCU_CLK_SD_FROM_APLL_CLK BIT(8) 942 943 static ulong ast2600_enable_extsdclk(struct ast2600_scu *scu) 944 { 945 u32 clk_sel = readl(&scu->clk_sel4); 946 u32 enableclk_bit; 947 u32 rate = 0; 948 u32 div = 0; 949 int i = 0; 950 951 enableclk_bit = BIT(SCU_CLKSTOP_EXTSD); 952 953 /* ast2600 sd controller max clk is 200Mhz : 954 * use apll for clock source 800/4 = 200 : controller max is 200mhz 955 */ 956 rate = ast2600_get_apll_rate(scu); 957 for (i = 0; i < 8; i++) { 958 div = (i + 1) * 2; 959 if ((rate / div) <= 200000000) 960 break; 961 } 962 clk_sel &= ~SCU_CLK_SD_MASK; 963 clk_sel |= SCU_CLK_SD_DIV(i) | SCU_CLK_SD_FROM_APLL_CLK; 964 writel(clk_sel, &scu->clk_sel4); 965 966 //enable clk 967 setbits_le32(&scu->clk_sel4, enableclk_bit); 968 969 return 0; 970 } 971 972 #define SCU_CLKSTOP_EMMC 27 973 static ulong ast2600_enable_emmcclk(struct ast2600_scu *scu) 974 { 975 u32 reset_bit; 976 u32 clkstop_bit; 977 978 reset_bit = BIT(ASPEED_RESET_EMMC); 979 clkstop_bit = BIT(SCU_CLKSTOP_EMMC); 980 981 writel(reset_bit, &scu->sysreset_ctrl1); 982 udelay(100); 983 //enable clk 984 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 985 mdelay(10); 986 writel(reset_bit, &scu->sysreset_clr_ctrl1); 987 988 return 0; 989 } 990 991 #define SCU_CLKSTOP_EXTEMMC 15 992 #define SCU_CLK_EMMC_MASK (0x7 << 12) 993 #define SCU_CLK_EMMC_DIV(x) ((x) << 12) 994 #define SCU_CLK_EMMC_FROM_MPLL_CLK BIT(11) 995 996 static ulong ast2600_enable_extemmcclk(struct ast2600_scu *scu) 997 { 998 u32 revision_id = readl(&scu->chip_id1); 999 u32 clk_sel = readl(&scu->clk_sel1); 1000 u32 enableclk_bit = BIT(SCU_CLKSTOP_EXTEMMC); 1001 u32 rate = 0; 1002 u32 div = 0; 1003 int i = 0; 1004 1005 /* 1006 * ast2600 eMMC controller max clk is 200Mhz 1007 * HPll->1/2->|\ 1008 * |->SCU300[11]->SCU300[14:12][1/N] + 1009 * MPLL------>|/ | 1010 * +----------------------------------------------+ 1011 * | 1012 * +---------> EMMC12C[15:8][1/N]-> eMMC clk 1013 */ 1014 if (((revision_id & CHIP_REVISION_ID) >> 16)) { 1015 //AST2600A1 : use mpll to be clk source 1016 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL); 1017 for (i = 0; i < 8; i++) { 1018 div = (i + 1) * 2; 1019 if ((rate / div) <= 200000000) 1020 break; 1021 } 1022 1023 clk_sel &= ~SCU_CLK_EMMC_MASK; 1024 clk_sel |= SCU_CLK_EMMC_DIV(i) | SCU_CLK_EMMC_FROM_MPLL_CLK; 1025 writel(clk_sel, &scu->clk_sel1); 1026 1027 } else { 1028 //AST2600A0 : use hpll to be clk source 1029 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 1030 1031 for (i = 0; i < 8; i++) { 1032 div = (i + 1) * 4; 1033 if ((rate / div) <= 200000000) 1034 break; 1035 } 1036 1037 clk_sel &= ~SCU_CLK_EMMC_MASK; 1038 clk_sel |= SCU_CLK_EMMC_DIV(i); 1039 writel(clk_sel, &scu->clk_sel1); 1040 } 1041 setbits_le32(&scu->clk_sel1, enableclk_bit); 1042 1043 return 0; 1044 } 1045 1046 #define SCU_CLKSTOP_FSICLK 30 1047 1048 static ulong ast2600_enable_fsiclk(struct ast2600_scu *scu) 1049 { 1050 u32 reset_bit; 1051 u32 clkstop_bit; 1052 1053 reset_bit = BIT(ASPEED_RESET_FSI % 32); 1054 clkstop_bit = BIT(SCU_CLKSTOP_FSICLK); 1055 1056 /* The FSI clock is shared between masters. If it's already on 1057 * don't touch it, as that will reset the existing master. 1058 */ 1059 if (!(readl(&scu->clk_stop_ctrl2) & clkstop_bit)) { 1060 debug("%s: already running, not touching it\n", __func__); 1061 return 0; 1062 } 1063 1064 writel(reset_bit, &scu->sysreset_ctrl2); 1065 udelay(100); 1066 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 1067 mdelay(10); 1068 writel(reset_bit, &scu->sysreset_clr_ctrl2); 1069 1070 return 0; 1071 } 1072 1073 static ulong ast2600_enable_usbahclk(struct ast2600_scu *scu) 1074 { 1075 u32 reset_bit; 1076 u32 clkstop_bit; 1077 1078 reset_bit = BIT(ASPEED_RESET_EHCI_P1); 1079 clkstop_bit = BIT(14); 1080 1081 writel(reset_bit, &scu->sysreset_ctrl1); 1082 udelay(100); 1083 writel(clkstop_bit, &scu->clk_stop_ctrl1); 1084 mdelay(20); 1085 writel(reset_bit, &scu->sysreset_clr_ctrl1); 1086 1087 return 0; 1088 } 1089 1090 static ulong ast2600_enable_usbbhclk(struct ast2600_scu *scu) 1091 { 1092 u32 reset_bit; 1093 u32 clkstop_bit; 1094 1095 reset_bit = BIT(ASPEED_RESET_EHCI_P2); 1096 clkstop_bit = BIT(7); 1097 1098 writel(reset_bit, &scu->sysreset_ctrl1); 1099 udelay(100); 1100 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 1101 mdelay(20); 1102 1103 writel(reset_bit, &scu->sysreset_clr_ctrl1); 1104 1105 return 0; 1106 } 1107 1108 static int ast2600_clk_enable(struct clk *clk) 1109 { 1110 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 1111 1112 switch (clk->id) { 1113 case ASPEED_CLK_GATE_MAC1CLK: 1114 ast2600_configure_mac(priv->scu, 1); 1115 break; 1116 case ASPEED_CLK_GATE_MAC2CLK: 1117 ast2600_configure_mac(priv->scu, 2); 1118 break; 1119 case ASPEED_CLK_GATE_MAC3CLK: 1120 ast2600_configure_mac(priv->scu, 3); 1121 break; 1122 case ASPEED_CLK_GATE_MAC4CLK: 1123 ast2600_configure_mac(priv->scu, 4); 1124 break; 1125 case ASPEED_CLK_GATE_SDCLK: 1126 ast2600_enable_sdclk(priv->scu); 1127 break; 1128 case ASPEED_CLK_GATE_SDEXTCLK: 1129 ast2600_enable_extsdclk(priv->scu); 1130 break; 1131 case ASPEED_CLK_GATE_EMMCCLK: 1132 ast2600_enable_emmcclk(priv->scu); 1133 break; 1134 case ASPEED_CLK_GATE_EMMCEXTCLK: 1135 ast2600_enable_extemmcclk(priv->scu); 1136 break; 1137 case ASPEED_CLK_GATE_FSICLK: 1138 ast2600_enable_fsiclk(priv->scu); 1139 break; 1140 case ASPEED_CLK_GATE_USBPORT1CLK: 1141 ast2600_enable_usbahclk(priv->scu); 1142 break; 1143 case ASPEED_CLK_GATE_USBPORT2CLK: 1144 ast2600_enable_usbbhclk(priv->scu); 1145 break; 1146 default: 1147 pr_err("can't enable clk\n"); 1148 return -ENOENT; 1149 } 1150 1151 return 0; 1152 } 1153 1154 struct clk_ops ast2600_clk_ops = { 1155 .get_rate = ast2600_clk_get_rate, 1156 .set_rate = ast2600_clk_set_rate, 1157 .enable = ast2600_clk_enable, 1158 }; 1159 1160 static int ast2600_clk_probe(struct udevice *dev) 1161 { 1162 struct ast2600_clk_priv *priv = dev_get_priv(dev); 1163 u32 uart_clk_source; 1164 1165 priv->scu = devfdt_get_addr_ptr(dev); 1166 if (IS_ERR(priv->scu)) 1167 return PTR_ERR(priv->scu); 1168 1169 uart_clk_source = dev_read_u32_default(dev, "uart-clk-source", 0x0); 1170 1171 if (uart_clk_source) { 1172 if (uart_clk_source & GENMASK(5, 0)) 1173 setbits_le32(&priv->scu->clk_sel4, 1174 uart_clk_source & GENMASK(5, 0)); 1175 if (uart_clk_source & GENMASK(12, 6)) 1176 setbits_le32(&priv->scu->clk_sel5, 1177 uart_clk_source & GENMASK(12, 6)); 1178 } 1179 1180 ast2600_init_rgmii_clk(priv->scu, &rgmii_clk_defconfig); 1181 ast2600_init_rmii_clk(priv->scu, &rmii_clk_defconfig); 1182 ast2600_configure_mac12_clk(priv->scu); 1183 ast2600_configure_mac34_clk(priv->scu); 1184 ast2600_configure_rsa_ecc_clk(priv->scu); 1185 1186 return 0; 1187 } 1188 1189 static int ast2600_clk_bind(struct udevice *dev) 1190 { 1191 int ret; 1192 1193 /* The reset driver does not have a device node, so bind it here */ 1194 ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev); 1195 if (ret) 1196 debug("Warning: No reset driver: ret=%d\n", ret); 1197 1198 return 0; 1199 } 1200 1201 struct aspeed_clks { 1202 ulong id; 1203 const char *name; 1204 }; 1205 1206 static struct aspeed_clks aspeed_clk_names[] = { 1207 { ASPEED_CLK_HPLL, "hpll" }, { ASPEED_CLK_MPLL, "mpll" }, 1208 { ASPEED_CLK_APLL, "apll" }, { ASPEED_CLK_EPLL, "epll" }, 1209 { ASPEED_CLK_DPLL, "dpll" }, { ASPEED_CLK_AHB, "hclk" }, 1210 { ASPEED_CLK_APB1, "pclk1" }, { ASPEED_CLK_APB2, "pclk2" }, 1211 { ASPEED_CLK_BCLK, "bclk" }, { ASPEED_CLK_UARTX, "uxclk" }, 1212 { ASPEED_CLK_HUARTX, "huxclk" }, 1213 }; 1214 1215 int soc_clk_dump(void) 1216 { 1217 struct udevice *dev; 1218 struct clk clk; 1219 unsigned long rate; 1220 int i, ret; 1221 1222 ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu), 1223 &dev); 1224 if (ret) 1225 return ret; 1226 1227 printf("Clk\t\tHz\n"); 1228 1229 for (i = 0; i < ARRAY_SIZE(aspeed_clk_names); i++) { 1230 clk.id = aspeed_clk_names[i].id; 1231 ret = clk_request(dev, &clk); 1232 if (ret < 0) { 1233 debug("%s clk_request() failed: %d\n", __func__, ret); 1234 continue; 1235 } 1236 1237 ret = clk_get_rate(&clk); 1238 rate = ret; 1239 1240 clk_free(&clk); 1241 1242 if (ret == -ENOTSUPP) { 1243 printf("clk ID %lu not supported yet\n", 1244 aspeed_clk_names[i].id); 1245 continue; 1246 } 1247 if (ret < 0) { 1248 printf("%s %lu: get_rate err: %d\n", __func__, 1249 aspeed_clk_names[i].id, ret); 1250 continue; 1251 } 1252 1253 printf("%s(%3lu):\t%lu\n", aspeed_clk_names[i].name, 1254 aspeed_clk_names[i].id, rate); 1255 } 1256 1257 return 0; 1258 } 1259 1260 static const struct udevice_id ast2600_clk_ids[] = { 1261 { 1262 .compatible = "aspeed,ast2600-scu", 1263 }, 1264 {} 1265 }; 1266 1267 U_BOOT_DRIVER(aspeed_scu) = { 1268 .name = "aspeed_scu", 1269 .id = UCLASS_CLK, 1270 .of_match = ast2600_clk_ids, 1271 .priv_auto_alloc_size = sizeof(struct ast2600_clk_priv), 1272 .ops = &ast2600_clk_ops, 1273 .bind = ast2600_clk_bind, 1274 .probe = ast2600_clk_probe, 1275 }; 1276