1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 */ 5 6 #include <common.h> 7 #include <clk-uclass.h> 8 #include <dm.h> 9 #include <asm/io.h> 10 #include <dm/lists.h> 11 #include <asm/arch/scu_ast2600.h> 12 #include <dt-bindings/clock/ast2600-clock.h> 13 #include <dt-bindings/reset/ast2600-reset.h> 14 15 /* 16 * MAC Clock Delay settings 17 */ 18 #define RGMII_TXCLK_ODLY 8 19 #define RMII_RXCLK_IDLY 2 20 21 #define MAC_DEF_DELAY_1G 0x0041b75d 22 #define MAC_DEF_DELAY_100M 0x00417410 23 #define MAC_DEF_DELAY_10M 0x00417410 24 25 #define MAC34_DEF_DELAY_1G 0x0010438a 26 #define MAC34_DEF_DELAY_100M 0x00104208 27 #define MAC34_DEF_DELAY_10M 0x00104208 28 29 /* 30 * TGMII Clock Duty constants, taken from Aspeed SDK 31 */ 32 #define RGMII2_TXCK_DUTY 0x66 33 #define RGMII1_TXCK_DUTY 0x64 34 #define D2PLL_DEFAULT_RATE (250 * 1000 * 1000) 35 #define CHIP_REVISION_ID GENMASK(23, 16) 36 37 DECLARE_GLOBAL_DATA_PTR; 38 39 /* 40 * Clock divider/multiplier configuration struct. 41 * For H-PLL and M-PLL the formula is 42 * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1) 43 * M - Numerator 44 * N - Denumerator 45 * P - Post Divider 46 * They have the same layout in their control register. 47 * 48 * D-PLL and D2-PLL have extra divider (OD + 1), which is not 49 * yet needed and ignored by clock configurations. 50 */ 51 union ast2600_pll_reg { 52 u32 w; 53 struct { 54 unsigned int m : 13; /* bit[12:0] */ 55 unsigned int n : 6; /* bit[18:13] */ 56 unsigned int p : 4; /* bit[22:19] */ 57 unsigned int off : 1; /* bit[23] */ 58 unsigned int bypass : 1; /* bit[24] */ 59 unsigned int reset : 1; /* bit[25] */ 60 unsigned int reserved : 6; /* bit[31:26] */ 61 } b; 62 }; 63 64 struct ast2600_pll_cfg { 65 union ast2600_pll_reg reg; 66 u32 ext_reg; 67 }; 68 69 struct ast2600_pll_desc { 70 u32 in; 71 u32 out; 72 struct ast2600_pll_cfg cfg; 73 }; 74 75 static const struct ast2600_pll_desc ast2600_pll_lookup[] = { 76 { 77 .in = AST2600_CLK_IN, 78 .out = 400000000, 79 .cfg.reg.b.m = 95, 80 .cfg.reg.b.n = 2, 81 .cfg.reg.b.p = 1, 82 .cfg.ext_reg = 0x31, 83 }, { 84 .in = AST2600_CLK_IN, 85 .out = 200000000, 86 .cfg.reg.b.m = 127, 87 .cfg.reg.b.n = 0, 88 .cfg.reg.b.p = 15, 89 .cfg.ext_reg = 0x3f, 90 }, { 91 .in = AST2600_CLK_IN, 92 .out = 334000000, 93 .cfg.reg.b.m = 667, 94 .cfg.reg.b.n = 4, 95 .cfg.reg.b.p = 9, 96 .cfg.ext_reg = 0x14d, 97 }, { 98 .in = AST2600_CLK_IN, 99 .out = 1000000000, 100 .cfg.reg.b.m = 119, 101 .cfg.reg.b.n = 2, 102 .cfg.reg.b.p = 0, 103 .cfg.ext_reg = 0x3d, 104 }, { 105 .in = AST2600_CLK_IN, 106 .out = 50000000, 107 .cfg.reg.b.m = 95, 108 .cfg.reg.b.n = 2, 109 .cfg.reg.b.p = 15, 110 .cfg.ext_reg = 0x31, 111 }, 112 }; 113 114 union mac_delay_1g { 115 u32 w; 116 struct { 117 unsigned int tx_delay_1 : 6; /* bit[5:0] */ 118 unsigned int tx_delay_2 : 6; /* bit[11:6] */ 119 unsigned int rx_delay_1 : 6; /* bit[17:12] */ 120 unsigned int rx_delay_2 : 6; /* bit[23:18] */ 121 unsigned int rx_clk_inv_1 : 1; /* bit[24] */ 122 unsigned int rx_clk_inv_2 : 1; /* bit[25] */ 123 unsigned int rmii_tx_data_at_falling_1 : 1; /* bit[26] */ 124 unsigned int rmii_tx_data_at_falling_2 : 1; /* bit[27] */ 125 unsigned int rgmiick_pad_dir : 1; /* bit[28] */ 126 unsigned int rmii_50m_oe_1 : 1; /* bit[29] */ 127 unsigned int rmii_50m_oe_2 : 1; /* bit[30] */ 128 unsigned int rgmii_125m_o_sel : 1; /* bit[31] */ 129 } b; 130 }; 131 132 union mac_delay_100_10 { 133 u32 w; 134 struct { 135 unsigned int tx_delay_1 : 6; /* bit[5:0] */ 136 unsigned int tx_delay_2 : 6; /* bit[11:6] */ 137 unsigned int rx_delay_1 : 6; /* bit[17:12] */ 138 unsigned int rx_delay_2 : 6; /* bit[23:18] */ 139 unsigned int rx_clk_inv_1 : 1; /* bit[24] */ 140 unsigned int rx_clk_inv_2 : 1; /* bit[25] */ 141 unsigned int reserved_0 : 6; /* bit[31:26] */ 142 } b; 143 }; 144 145 struct mac_delay_config { 146 u32 tx_delay_1000; 147 u32 rx_delay_1000; 148 u32 tx_delay_100; 149 u32 rx_delay_100; 150 u32 tx_delay_10; 151 u32 rx_delay_10; 152 }; 153 154 extern u32 ast2600_get_pll_rate(struct ast2600_scu *scu, int pll_idx) 155 { 156 u32 clkin = AST2600_CLK_IN; 157 u32 pll_reg = 0; 158 unsigned int mult, div = 1; 159 160 switch (pll_idx) { 161 case ASPEED_CLK_HPLL: 162 pll_reg = readl(&scu->h_pll_param); 163 break; 164 case ASPEED_CLK_MPLL: 165 pll_reg = readl(&scu->m_pll_param); 166 break; 167 case ASPEED_CLK_DPLL: 168 pll_reg = readl(&scu->d_pll_param); 169 break; 170 case ASPEED_CLK_EPLL: 171 pll_reg = readl(&scu->e_pll_param); 172 break; 173 } 174 if (pll_reg & BIT(24)) { 175 /* Pass through mode */ 176 mult = 1; 177 div = 1; 178 } else { 179 union ast2600_pll_reg reg; 180 /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) 181 * HPLL Numerator (M) = fix 0x5F when SCU500[10]=1 182 * Fixed 0xBF when SCU500[10]=0 and SCU500[8]=1 183 * SCU200[12:0] (default 0x8F) when SCU510[10]=0 and SCU510[8]=0 184 * HPLL Denumerator (N) = SCU200[18:13] (default 0x2) 185 * HPLL Divider (P) = SCU200[22:19] (default 0x0) 186 * HPLL Bandwidth Adj (NB) = fix 0x2F when SCU500[10]=1 187 * Fixed 0x5F when SCU500[10]=0 and SCU500[8]=1 188 * SCU204[11:0] (default 0x31) when SCU500[10]=0 and SCU500[8]=0 189 */ 190 reg.w = pll_reg; 191 if (pll_idx == ASPEED_CLK_HPLL) { 192 u32 hwstrap1 = readl(&scu->hwstrap1.hwstrap); 193 194 if (hwstrap1 & BIT(10)) { 195 reg.b.m = 0x5F; 196 } else { 197 if (hwstrap1 & BIT(8)) 198 reg.b.m = 0xBF; 199 /* Otherwise keep default 0x8F */ 200 } 201 } 202 mult = (reg.b.m + 1) / (reg.b.n + 1); 203 div = (reg.b.p + 1); 204 } 205 206 return ((clkin * mult) / div); 207 } 208 209 extern u32 ast2600_get_apll_rate(struct ast2600_scu *scu) 210 { 211 u32 hw_rev = readl(&scu->chip_id1); 212 u32 clkin = AST2600_CLK_IN; 213 u32 apll_reg = readl(&scu->a_pll_param); 214 unsigned int mult, div = 1; 215 216 if (((hw_rev & CHIP_REVISION_ID) >> 16) >= 2) { 217 //after A2 version 218 if (apll_reg & BIT(24)) { 219 /* Pass through mode */ 220 mult = 1; 221 div = 1; 222 } else { 223 /* F = 25Mhz * [(m + 1) / (n + 1)] / (p + 1) */ 224 u32 m = apll_reg & 0x1fff; 225 u32 n = (apll_reg >> 13) & 0x3f; 226 u32 p = (apll_reg >> 19) & 0xf; 227 228 mult = (m + 1); 229 div = (n + 1) * (p + 1); 230 } 231 } else { 232 if (apll_reg & BIT(20)) { 233 /* Pass through mode */ 234 mult = 1; 235 div = 1; 236 } else { 237 /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */ 238 u32 m = (apll_reg >> 5) & 0x3f; 239 u32 od = (apll_reg >> 4) & 0x1; 240 u32 n = apll_reg & 0xf; 241 242 mult = (2 - od) * (m + 2); 243 div = n + 1; 244 } 245 } 246 247 return ((clkin * mult) / div); 248 } 249 250 static u32 ast2600_a0_axi_ahb_div_table[] = { 251 2, 252 2, 253 3, 254 4, 255 }; 256 257 static u32 ast2600_a1_axi_ahb_div0_table[] = { 258 3, 259 2, 260 3, 261 4, 262 }; 263 264 static u32 ast2600_a1_axi_ahb_div1_table[] = { 265 3, 266 4, 267 6, 268 8, 269 }; 270 271 static u32 ast2600_a1_axi_ahb_default_table[] = { 272 3, 4, 3, 4, 2, 2, 2, 2, 273 }; 274 275 static u32 ast2600_get_hclk(struct ast2600_scu *scu) 276 { 277 u32 hw_rev = readl(&scu->chip_id1); 278 u32 hwstrap1 = readl(&scu->hwstrap1.hwstrap); 279 u32 axi_div = 1; 280 u32 ahb_div = 0; 281 u32 rate = 0; 282 283 if ((hw_rev & CHIP_REVISION_ID) >> 16) { 284 //After A0 285 if (hwstrap1 & BIT(16)) { 286 ast2600_a1_axi_ahb_div1_table[0] = 287 ast2600_a1_axi_ahb_default_table[(hwstrap1 >> 8) & 288 0x7] * 2; 289 axi_div = 1; 290 ahb_div = 291 ast2600_a1_axi_ahb_div1_table[(hwstrap1 >> 11) & 292 0x3]; 293 } else { 294 ast2600_a1_axi_ahb_div0_table[0] = 295 ast2600_a1_axi_ahb_default_table[(hwstrap1 >> 8) & 296 0x7]; 297 axi_div = 2; 298 ahb_div = 299 ast2600_a1_axi_ahb_div0_table[(hwstrap1 >> 11) & 300 0x3]; 301 } 302 } else { 303 //A0 : fix axi = hpll / 2 304 axi_div = 2; 305 ahb_div = ast2600_a0_axi_ahb_div_table[(hwstrap1 >> 11) & 0x3]; 306 } 307 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 308 309 return (rate / axi_div / ahb_div); 310 } 311 312 static u32 ast2600_get_bclk_rate(struct ast2600_scu *scu) 313 { 314 u32 rate; 315 u32 bclk_sel = (readl(&scu->clk_sel1) >> 20) & 0x7; 316 317 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 318 319 return (rate / ((bclk_sel + 1) * 4)); 320 } 321 322 static u32 ast2600_hpll_pclk1_div_table[] = { 323 4, 8, 12, 16, 20, 24, 28, 32, 324 }; 325 326 static u32 ast2600_hpll_pclk2_div_table[] = { 327 2, 4, 6, 8, 10, 12, 14, 16, 328 }; 329 330 static u32 ast2600_get_pclk1(struct ast2600_scu *scu) 331 { 332 u32 clk_sel1 = readl(&scu->clk_sel1); 333 u32 apb_div = ast2600_hpll_pclk1_div_table[((clk_sel1 >> 23) & 0x7)]; 334 u32 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 335 336 return (rate / apb_div); 337 } 338 339 static u32 ast2600_get_pclk2(struct ast2600_scu *scu) 340 { 341 u32 clk_sel4 = readl(&scu->clk_sel4); 342 u32 apb_div = ast2600_hpll_pclk2_div_table[((clk_sel4 >> 9) & 0x7)]; 343 u32 rate = ast2600_get_hclk(scu); 344 345 return (rate / apb_div); 346 } 347 348 static u32 ast2600_get_uxclk_in_rate(struct ast2600_scu *scu) 349 { 350 u32 clk_in = 0; 351 u32 uxclk_sel = readl(&scu->clk_sel5); 352 353 uxclk_sel &= 0x3; 354 switch (uxclk_sel) { 355 case 0: 356 clk_in = ast2600_get_apll_rate(scu) / 4; 357 break; 358 case 1: 359 clk_in = ast2600_get_apll_rate(scu) / 2; 360 break; 361 case 2: 362 clk_in = ast2600_get_apll_rate(scu); 363 break; 364 case 3: 365 clk_in = ast2600_get_hclk(scu); 366 break; 367 } 368 369 return clk_in; 370 } 371 372 static u32 ast2600_get_huxclk_in_rate(struct ast2600_scu *scu) 373 { 374 u32 clk_in = 0; 375 u32 huclk_sel = readl(&scu->clk_sel5); 376 377 huclk_sel = ((huclk_sel >> 3) & 0x3); 378 switch (huclk_sel) { 379 case 0: 380 clk_in = ast2600_get_apll_rate(scu) / 4; 381 break; 382 case 1: 383 clk_in = ast2600_get_apll_rate(scu) / 2; 384 break; 385 case 2: 386 clk_in = ast2600_get_apll_rate(scu); 387 break; 388 case 3: 389 clk_in = ast2600_get_hclk(scu); 390 break; 391 } 392 393 return clk_in; 394 } 395 396 static u32 ast2600_get_uart_uxclk_rate(struct ast2600_scu *scu) 397 { 398 u32 clk_in = ast2600_get_uxclk_in_rate(scu); 399 u32 div_reg = readl(&scu->uart_24m_ref_uxclk); 400 unsigned int mult, div; 401 402 u32 n = (div_reg >> 8) & 0x3ff; 403 u32 r = div_reg & 0xff; 404 405 mult = r; 406 div = (n * 2); 407 return (clk_in * mult) / div; 408 } 409 410 static u32 ast2600_get_uart_huxclk_rate(struct ast2600_scu *scu) 411 { 412 u32 clk_in = ast2600_get_huxclk_in_rate(scu); 413 u32 div_reg = readl(&scu->uart_24m_ref_huxclk); 414 415 unsigned int mult, div; 416 417 u32 n = (div_reg >> 8) & 0x3ff; 418 u32 r = div_reg & 0xff; 419 420 mult = r; 421 div = (n * 2); 422 return (clk_in * mult) / div; 423 } 424 425 static u32 ast2600_get_sdio_clk_rate(struct ast2600_scu *scu) 426 { 427 u32 clkin = 0; 428 u32 clk_sel = readl(&scu->clk_sel4); 429 u32 div = (clk_sel >> 28) & 0x7; 430 u32 hw_rev = readl(&scu->chip_id1); 431 432 if (clk_sel & BIT(8)) 433 clkin = ast2600_get_apll_rate(scu); 434 else 435 clkin = ast2600_get_hclk(scu); 436 437 div = (1 + div) * 2; 438 if (((hw_rev & GENMASK(23, 16)) >> 16) >= 2) 439 div = (div & 0xf) ? div : 1; 440 441 return (clkin / div); 442 } 443 444 static u32 ast2600_get_emmc_clk_rate(struct ast2600_scu *scu) 445 { 446 u32 mmc_clk_src = readl(&scu->clk_sel1); 447 u32 clkin; 448 u32 clk_sel = readl(&scu->clk_sel1); 449 u32 div = (clk_sel >> 12) & 0x7; 450 451 if (mmc_clk_src & BIT(11)) { 452 /* emmc clock comes from MPLL */ 453 clkin = ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL); 454 div = (div + 1) * 2; 455 } else { 456 clkin = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 457 div = (div + 1) << 2; 458 } 459 460 return (clkin / div); 461 } 462 463 static u32 ast2600_get_uart_clk_rate(struct ast2600_scu *scu, int uart_idx) 464 { 465 u32 hicr9 = readl(0x1e789098); 466 u32 uart_sel = readl(&scu->clk_sel4); 467 u32 uart_sel5 = readl(&scu->clk_sel5); 468 ulong uart_clk = 0; 469 470 switch (uart_idx) { 471 case 1: 472 case 2: 473 case 3: 474 case 4: 475 hicr9 &= ~(BIT(uart_idx + 3)); 476 writel(hicr9, 0x1e789098); 477 case 6: 478 if (uart_sel & BIT(uart_idx - 1)) 479 uart_clk = ast2600_get_uart_huxclk_rate(scu); 480 else 481 uart_clk = ast2600_get_uart_uxclk_rate(scu); 482 break; 483 case 5: //24mhz is come form usb phy 48Mhz 484 { 485 u8 uart5_clk_sel = 0; 486 //high bit 487 if (readl(&scu->misc_ctrl1) & BIT(12)) 488 uart5_clk_sel = 0x2; 489 else 490 uart5_clk_sel = 0x0; 491 492 if (readl(&scu->clk_sel2) & BIT(14)) 493 uart5_clk_sel |= 0x1; 494 495 switch (uart5_clk_sel) { 496 case 0: 497 uart_clk = 24000000; 498 break; 499 case 1: 500 uart_clk = 192000000; 501 break; 502 case 2: 503 uart_clk = 24000000 / 13; 504 break; 505 case 3: 506 uart_clk = 192000000 / 13; 507 break; 508 } 509 } break; 510 case 7: 511 case 8: 512 case 9: 513 case 10: 514 case 11: 515 case 12: 516 case 13: 517 if (uart_sel5 & BIT(uart_idx - 1)) 518 uart_clk = ast2600_get_uart_huxclk_rate(scu); 519 else 520 uart_clk = ast2600_get_uart_uxclk_rate(scu); 521 break; 522 } 523 524 return uart_clk; 525 } 526 527 static ulong ast2600_clk_get_rate(struct clk *clk) 528 { 529 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 530 ulong rate = 0; 531 532 switch (clk->id) { 533 case ASPEED_CLK_HPLL: 534 case ASPEED_CLK_EPLL: 535 case ASPEED_CLK_DPLL: 536 case ASPEED_CLK_MPLL: 537 rate = ast2600_get_pll_rate(priv->scu, clk->id); 538 break; 539 case ASPEED_CLK_AHB: 540 rate = ast2600_get_hclk(priv->scu); 541 break; 542 case ASPEED_CLK_APB1: 543 rate = ast2600_get_pclk1(priv->scu); 544 break; 545 case ASPEED_CLK_APB2: 546 rate = ast2600_get_pclk2(priv->scu); 547 break; 548 case ASPEED_CLK_APLL: 549 rate = ast2600_get_apll_rate(priv->scu); 550 break; 551 case ASPEED_CLK_GATE_UART1CLK: 552 rate = ast2600_get_uart_clk_rate(priv->scu, 1); 553 break; 554 case ASPEED_CLK_GATE_UART2CLK: 555 rate = ast2600_get_uart_clk_rate(priv->scu, 2); 556 break; 557 case ASPEED_CLK_GATE_UART3CLK: 558 rate = ast2600_get_uart_clk_rate(priv->scu, 3); 559 break; 560 case ASPEED_CLK_GATE_UART4CLK: 561 rate = ast2600_get_uart_clk_rate(priv->scu, 4); 562 break; 563 case ASPEED_CLK_GATE_UART5CLK: 564 rate = ast2600_get_uart_clk_rate(priv->scu, 5); 565 break; 566 case ASPEED_CLK_BCLK: 567 rate = ast2600_get_bclk_rate(priv->scu); 568 break; 569 case ASPEED_CLK_SDIO: 570 rate = ast2600_get_sdio_clk_rate(priv->scu); 571 break; 572 case ASPEED_CLK_EMMC: 573 rate = ast2600_get_emmc_clk_rate(priv->scu); 574 break; 575 case ASPEED_CLK_UARTX: 576 rate = ast2600_get_uart_uxclk_rate(priv->scu); 577 break; 578 case ASPEED_CLK_HUARTX: 579 rate = ast2600_get_uart_huxclk_rate(priv->scu); 580 break; 581 default: 582 pr_debug("can't get clk rate\n"); 583 return -ENOENT; 584 } 585 586 return rate; 587 } 588 589 /** 590 * @brief lookup PLL divider config by input/output rate 591 * @param[in] *pll - PLL descriptor 592 * @return true - if PLL divider config is found, false - else 593 * The function caller shall fill "pll->in" and "pll->out", 594 * then this function will search the lookup table 595 * to find a valid PLL divider configuration. 596 */ 597 static bool ast2600_search_clock_config(struct ast2600_pll_desc *pll) 598 { 599 u32 i; 600 bool is_found = false; 601 602 for (i = 0; i < ARRAY_SIZE(ast2600_pll_lookup); i++) { 603 const struct ast2600_pll_desc *def_cfg = &ast2600_pll_lookup[i]; 604 605 if (def_cfg->in == pll->in && def_cfg->out == pll->out) { 606 is_found = true; 607 pll->cfg.reg.w = def_cfg->cfg.reg.w; 608 pll->cfg.ext_reg = def_cfg->cfg.ext_reg; 609 break; 610 } 611 } 612 return is_found; 613 } 614 615 static u32 ast2600_configure_pll(struct ast2600_scu *scu, 616 struct ast2600_pll_cfg *p_cfg, int pll_idx) 617 { 618 u32 addr, addr_ext; 619 u32 reg; 620 621 switch (pll_idx) { 622 case ASPEED_CLK_HPLL: 623 addr = (u32)(&scu->h_pll_param); 624 addr_ext = (u32)(&scu->h_pll_ext_param); 625 break; 626 case ASPEED_CLK_MPLL: 627 addr = (u32)(&scu->m_pll_param); 628 addr_ext = (u32)(&scu->m_pll_ext_param); 629 break; 630 case ASPEED_CLK_DPLL: 631 addr = (u32)(&scu->d_pll_param); 632 addr_ext = (u32)(&scu->d_pll_ext_param); 633 break; 634 case ASPEED_CLK_EPLL: 635 addr = (u32)(&scu->e_pll_param); 636 addr_ext = (u32)(&scu->e_pll_ext_param); 637 break; 638 default: 639 debug("unknown PLL index\n"); 640 return 1; 641 } 642 643 p_cfg->reg.b.bypass = 0; 644 p_cfg->reg.b.off = 1; 645 p_cfg->reg.b.reset = 1; 646 647 reg = readl(addr); 648 reg &= ~GENMASK(25, 0); 649 reg |= p_cfg->reg.w; 650 writel(reg, addr); 651 652 /* write extend parameter */ 653 writel(p_cfg->ext_reg, addr_ext); 654 udelay(100); 655 p_cfg->reg.b.off = 0; 656 p_cfg->reg.b.reset = 0; 657 reg &= ~GENMASK(25, 0); 658 reg |= p_cfg->reg.w; 659 writel(reg, addr); 660 while (!(readl(addr_ext) & BIT(31))) 661 ; 662 663 return 0; 664 } 665 666 static u32 ast2600_configure_ddr(struct ast2600_scu *scu, ulong rate) 667 { 668 struct ast2600_pll_desc mpll; 669 670 mpll.in = AST2600_CLK_IN; 671 mpll.out = rate; 672 if (ast2600_search_clock_config(&mpll) == false) { 673 printf("error!! unable to find valid DDR clock setting\n"); 674 return 0; 675 } 676 ast2600_configure_pll(scu, &mpll.cfg, ASPEED_CLK_MPLL); 677 678 return ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL); 679 } 680 681 static ulong ast2600_clk_set_rate(struct clk *clk, ulong rate) 682 { 683 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 684 ulong new_rate; 685 686 switch (clk->id) { 687 case ASPEED_CLK_MPLL: 688 new_rate = ast2600_configure_ddr(priv->scu, rate); 689 break; 690 default: 691 return -ENOENT; 692 } 693 694 return new_rate; 695 } 696 697 #define SCU_CLKSTOP_MAC1 (20) 698 #define SCU_CLKSTOP_MAC2 (21) 699 #define SCU_CLKSTOP_MAC3 (20) 700 #define SCU_CLKSTOP_MAC4 (21) 701 702 static u32 ast2600_configure_mac12_clk(struct ast2600_scu *scu, struct udevice *dev) 703 { 704 union mac_delay_1g reg_1g; 705 union mac_delay_100_10 reg_100, reg_10; 706 struct mac_delay_config mac1_cfg, mac2_cfg; 707 int ret; 708 709 reg_1g.w = (readl(&scu->mac12_clk_delay) & ~GENMASK(25, 0)) | 710 MAC_DEF_DELAY_1G; 711 reg_100.w = MAC_DEF_DELAY_100M; 712 reg_10.w = MAC_DEF_DELAY_10M; 713 714 ret = dev_read_u32_array(dev, "mac0-clk-delay", (u32 *)&mac1_cfg, sizeof(mac1_cfg) / sizeof(u32)); 715 if (!ret) { 716 reg_1g.b.tx_delay_1 = mac1_cfg.tx_delay_1000; 717 reg_1g.b.rx_delay_1 = mac1_cfg.rx_delay_1000; 718 reg_100.b.tx_delay_1 = mac1_cfg.tx_delay_100; 719 reg_100.b.rx_delay_1 = mac1_cfg.rx_delay_100; 720 reg_10.b.tx_delay_1 = mac1_cfg.tx_delay_10; 721 reg_10.b.rx_delay_1 = mac1_cfg.rx_delay_10; 722 } 723 724 ret = dev_read_u32_array(dev, "mac1-clk-delay", (u32 *)&mac2_cfg, sizeof(mac2_cfg) / sizeof(u32)); 725 if (!ret) { 726 reg_1g.b.tx_delay_2 = mac2_cfg.tx_delay_1000; 727 reg_1g.b.rx_delay_2 = mac2_cfg.rx_delay_1000; 728 reg_100.b.tx_delay_2 = mac2_cfg.tx_delay_100; 729 reg_100.b.rx_delay_2 = mac2_cfg.rx_delay_100; 730 reg_10.b.tx_delay_2 = mac2_cfg.tx_delay_10; 731 reg_10.b.rx_delay_2 = mac2_cfg.rx_delay_10; 732 } 733 734 writel(reg_1g.w, &scu->mac12_clk_delay); 735 writel(reg_100.w, &scu->mac12_clk_delay_100M); 736 writel(reg_10.w, &scu->mac12_clk_delay_10M); 737 738 /* MAC AHB = HPLL / 6 */ 739 clrsetbits_le32(&scu->clk_sel1, GENMASK(18, 16), (0x2 << 16)); 740 741 return 0; 742 } 743 744 static u32 ast2600_configure_mac34_clk(struct ast2600_scu *scu, struct udevice *dev) 745 { 746 union mac_delay_1g reg_1g; 747 union mac_delay_100_10 reg_100, reg_10; 748 struct mac_delay_config mac3_cfg, mac4_cfg; 749 int ret; 750 751 /* 752 * scu350[31] RGMII 125M source: 0 = from IO pin 753 * scu350[25:0] MAC 1G delay 754 */ 755 reg_1g.w = (readl(&scu->mac34_clk_delay) & ~GENMASK(25, 0)) | 756 MAC34_DEF_DELAY_1G; 757 reg_1g.b.rgmii_125m_o_sel = 0; 758 reg_100.w = MAC34_DEF_DELAY_100M; 759 reg_10.w = MAC34_DEF_DELAY_10M; 760 761 ret = dev_read_u32_array(dev, "mac2-clk-delay", (u32 *)&mac3_cfg, sizeof(mac3_cfg) / sizeof(u32)); 762 if (!ret) { 763 reg_1g.b.tx_delay_1 = mac3_cfg.tx_delay_1000; 764 reg_1g.b.rx_delay_1 = mac3_cfg.rx_delay_1000; 765 reg_100.b.tx_delay_1 = mac3_cfg.tx_delay_100; 766 reg_100.b.rx_delay_1 = mac3_cfg.rx_delay_100; 767 reg_10.b.tx_delay_1 = mac3_cfg.tx_delay_10; 768 reg_10.b.rx_delay_1 = mac3_cfg.rx_delay_10; 769 } 770 771 ret = dev_read_u32_array(dev, "mac3-clk-delay", (u32 *)&mac4_cfg, sizeof(mac4_cfg) / sizeof(u32)); 772 if (!ret) { 773 reg_1g.b.tx_delay_2 = mac4_cfg.tx_delay_1000; 774 reg_1g.b.rx_delay_2 = mac4_cfg.rx_delay_1000; 775 reg_100.b.tx_delay_2 = mac4_cfg.tx_delay_100; 776 reg_100.b.rx_delay_2 = mac4_cfg.rx_delay_100; 777 reg_10.b.tx_delay_2 = mac4_cfg.tx_delay_10; 778 reg_10.b.rx_delay_2 = mac4_cfg.rx_delay_10; 779 } 780 781 writel(reg_1g.w, &scu->mac34_clk_delay); 782 writel(reg_100.w, &scu->mac34_clk_delay_100M); 783 writel(reg_10.w, &scu->mac34_clk_delay_10M); 784 785 /* 786 * clock source seletion and divider 787 * scu310[26:24] : MAC AHB bus clock = HCLK / 2 788 * scu310[18:16] : RMII 50M = HCLK_200M / 4 789 */ 790 clrsetbits_le32(&scu->clk_sel4, (GENMASK(26, 24) | GENMASK(18, 16)), 791 ((0x0 << 24) | (0x3 << 16))); 792 793 /* 794 * set driving strength 795 * scu458[3:2] : MAC4 driving strength 796 * scu458[1:0] : MAC3 driving strength 797 */ 798 clrsetbits_le32(&scu->pinmux_ctrl16, GENMASK(3, 0), 799 (0x3 << 2) | (0x3 << 0)); 800 801 return 0; 802 } 803 804 /** 805 * ast2600 RGMII clock source tree 806 * 125M from external PAD -------->|\ 807 * HPLL -->|\ | |---->RGMII 125M for MAC#1 & MAC#2 808 * | |---->| divider |---->|/ + 809 * EPLL -->|/ | 810 * | 811 * +---------<-----------|RGMIICK PAD output enable|<-------------+ 812 * | 813 * +--------------------------->|\ 814 * | |----> RGMII 125M for MAC#3 & MAC#4 815 * HCLK 200M ---->|divider|---->|/ 816 * To simplify the control flow: 817 * 1. RGMII 1/2 always use EPLL as the internal clock source 818 * 2. RGMII 3/4 always use RGMIICK pad as the RGMII 125M source 819 * 125M from external PAD -------->|\ 820 * | |---->RGMII 125M for MAC#1 & MAC#2 821 * EPLL---->| divider |--->|/ + 822 * | 823 * +<--------------------|RGMIICK PAD output enable|<-------------+ 824 * | 825 * +--------------------------->RGMII 125M for MAC#3 & MAC#4 826 */ 827 #define RGMIICK_SRC_PAD 0 828 #define RGMIICK_SRC_EPLL 1 /* recommended */ 829 #define RGMIICK_SRC_HPLL 2 830 831 #define RGMIICK_DIV2 1 832 #define RGMIICK_DIV3 2 833 #define RGMIICK_DIV4 3 834 #define RGMIICK_DIV5 4 835 #define RGMIICK_DIV6 5 836 #define RGMIICK_DIV7 6 837 #define RGMIICK_DIV8 7 /* recommended */ 838 839 #define RMIICK_DIV4 0 840 #define RMIICK_DIV8 1 841 #define RMIICK_DIV12 2 842 #define RMIICK_DIV16 3 843 #define RMIICK_DIV20 4 /* recommended */ 844 #define RMIICK_DIV24 5 845 #define RMIICK_DIV28 6 846 #define RMIICK_DIV32 7 847 848 struct ast2600_mac_clk_div { 849 u32 src; /* 0=external PAD, 1=internal PLL */ 850 u32 fin; /* divider input speed */ 851 u32 n; /* 0=div2, 1=div2, 2=div3, 3=div4,...,7=div8 */ 852 u32 fout; /* fout = fin / n */ 853 }; 854 855 struct ast2600_mac_clk_div rgmii_clk_defconfig = { 856 .src = ASPEED_CLK_EPLL, 857 .fin = 1000000000, 858 .n = RGMIICK_DIV8, 859 .fout = 125000000, 860 }; 861 862 struct ast2600_mac_clk_div rmii_clk_defconfig = { 863 .src = ASPEED_CLK_EPLL, 864 .fin = 1000000000, 865 .n = RMIICK_DIV20, 866 .fout = 50000000, 867 }; 868 869 static void ast2600_init_mac_pll(struct ast2600_scu *p_scu, 870 struct ast2600_mac_clk_div *p_cfg) 871 { 872 struct ast2600_pll_desc pll; 873 874 pll.in = AST2600_CLK_IN; 875 pll.out = p_cfg->fin; 876 if (ast2600_search_clock_config(&pll) == false) { 877 pr_err("unable to find valid ETHNET MAC clock setting\n"); 878 debug("%s: pll cfg = 0x%08x 0x%08x\n", __func__, pll.cfg.reg.w, 879 pll.cfg.ext_reg); 880 debug("%s: pll cfg = %02x %02x %02x\n", __func__, 881 pll.cfg.reg.b.m, pll.cfg.reg.b.n, pll.cfg.reg.b.p); 882 return; 883 } 884 ast2600_configure_pll(p_scu, &pll.cfg, p_cfg->src); 885 } 886 887 static void ast2600_init_rgmii_clk(struct ast2600_scu *p_scu, 888 struct ast2600_mac_clk_div *p_cfg) 889 { 890 u32 reg_304 = readl(&p_scu->clk_sel2); 891 u32 reg_340 = readl(&p_scu->mac12_clk_delay); 892 u32 reg_350 = readl(&p_scu->mac34_clk_delay); 893 894 reg_340 &= ~GENMASK(31, 29); 895 /* scu340[28]: RGMIICK PAD output enable (to MAC 3/4) */ 896 reg_340 |= BIT(28); 897 if (p_cfg->src == ASPEED_CLK_EPLL || p_cfg->src == ASPEED_CLK_HPLL) { 898 /* 899 * re-init PLL if the current PLL output frequency doesn't match 900 * the divider setting 901 */ 902 if (p_cfg->fin != ast2600_get_pll_rate(p_scu, p_cfg->src)) 903 ast2600_init_mac_pll(p_scu, p_cfg); 904 /* scu340[31]: select RGMII 125M from internal source */ 905 reg_340 |= BIT(31); 906 } 907 908 reg_304 &= ~GENMASK(23, 20); 909 910 /* set clock divider */ 911 reg_304 |= (p_cfg->n & 0x7) << 20; 912 913 /* select internal clock source */ 914 if (p_cfg->src == ASPEED_CLK_HPLL) 915 reg_304 |= BIT(23); 916 917 /* RGMII 3/4 clock source select */ 918 reg_350 &= ~BIT(31); 919 920 writel(reg_304, &p_scu->clk_sel2); 921 writel(reg_340, &p_scu->mac12_clk_delay); 922 writel(reg_350, &p_scu->mac34_clk_delay); 923 } 924 925 /** 926 * ast2600 RMII/NCSI clock source tree 927 * HPLL -->|\ 928 * | |---->| divider |----> RMII 50M for MAC#1 & MAC#2 929 * EPLL -->|/ 930 * HCLK(SCLICLK)---->| divider |----> RMII 50M for MAC#3 & MAC#4 931 */ 932 static void ast2600_init_rmii_clk(struct ast2600_scu *p_scu, 933 struct ast2600_mac_clk_div *p_cfg) 934 { 935 u32 reg_304; 936 u32 reg_310; 937 938 if (p_cfg->src == ASPEED_CLK_EPLL || p_cfg->src == ASPEED_CLK_HPLL) { 939 /* 940 * re-init PLL if the current PLL output frequency doesn't match 941 * the divider setting 942 */ 943 if (p_cfg->fin != ast2600_get_pll_rate(p_scu, p_cfg->src)) 944 ast2600_init_mac_pll(p_scu, p_cfg); 945 } 946 947 reg_304 = readl(&p_scu->clk_sel2); 948 reg_310 = readl(&p_scu->clk_sel4); 949 950 reg_304 &= ~GENMASK(19, 16); 951 952 /* set RMII 1/2 clock divider */ 953 reg_304 |= (p_cfg->n & 0x7) << 16; 954 955 /* RMII clock source selection */ 956 if (p_cfg->src == ASPEED_CLK_HPLL) 957 reg_304 |= BIT(19); 958 959 /* set RMII 3/4 clock divider */ 960 reg_310 &= ~GENMASK(18, 16); 961 reg_310 |= (0x3 << 16); 962 963 writel(reg_304, &p_scu->clk_sel2); 964 writel(reg_310, &p_scu->clk_sel4); 965 } 966 967 static u32 ast2600_configure_mac(struct ast2600_scu *scu, int index) 968 { 969 u32 reset_bit; 970 u32 clkstop_bit; 971 972 switch (index) { 973 case 1: 974 reset_bit = BIT(ASPEED_RESET_MAC1); 975 clkstop_bit = BIT(SCU_CLKSTOP_MAC1); 976 writel(reset_bit, &scu->sysreset_ctrl1); 977 udelay(100); 978 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 979 mdelay(10); 980 writel(reset_bit, &scu->sysreset_clr_ctrl1); 981 break; 982 case 2: 983 reset_bit = BIT(ASPEED_RESET_MAC2); 984 clkstop_bit = BIT(SCU_CLKSTOP_MAC2); 985 writel(reset_bit, &scu->sysreset_ctrl1); 986 udelay(100); 987 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 988 mdelay(10); 989 writel(reset_bit, &scu->sysreset_clr_ctrl1); 990 break; 991 case 3: 992 reset_bit = BIT(ASPEED_RESET_MAC3 - 32); 993 clkstop_bit = BIT(SCU_CLKSTOP_MAC3); 994 writel(reset_bit, &scu->sysreset_ctrl2); 995 udelay(100); 996 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 997 mdelay(10); 998 writel(reset_bit, &scu->sysreset_clr_ctrl2); 999 break; 1000 case 4: 1001 reset_bit = BIT(ASPEED_RESET_MAC4 - 32); 1002 clkstop_bit = BIT(SCU_CLKSTOP_MAC4); 1003 writel(reset_bit, &scu->sysreset_ctrl2); 1004 udelay(100); 1005 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 1006 mdelay(10); 1007 writel(reset_bit, &scu->sysreset_clr_ctrl2); 1008 break; 1009 default: 1010 return -EINVAL; 1011 } 1012 1013 return 0; 1014 } 1015 1016 #define SCU_CLK_ECC_RSA_FROM_HPLL_CLK BIT(19) 1017 #define SCU_CLK_ECC_RSA_CLK_MASK GENMASK(27, 26) 1018 #define SCU_CLK_ECC_RSA_CLK_DIV(x) ((x) << 26) 1019 static void ast2600_configure_rsa_ecc_clk(struct ast2600_scu *scu) 1020 { 1021 u32 clk_sel = readl(&scu->clk_sel1); 1022 1023 /* Configure RSA clock = HPLL/4 */ 1024 clk_sel |= SCU_CLK_ECC_RSA_FROM_HPLL_CLK; 1025 clk_sel &= ~SCU_CLK_ECC_RSA_CLK_MASK; 1026 clk_sel |= SCU_CLK_ECC_RSA_CLK_DIV(3); 1027 1028 writel(clk_sel, &scu->clk_sel1); 1029 } 1030 1031 #define SCU_CLKSTOP_SDIO 4 1032 static ulong ast2600_enable_sdclk(struct ast2600_scu *scu) 1033 { 1034 u32 reset_bit; 1035 u32 clkstop_bit; 1036 1037 reset_bit = BIT(ASPEED_RESET_SD - 32); 1038 clkstop_bit = BIT(SCU_CLKSTOP_SDIO); 1039 1040 writel(reset_bit, &scu->sysreset_ctrl2); 1041 1042 udelay(100); 1043 //enable clk 1044 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 1045 mdelay(10); 1046 writel(reset_bit, &scu->sysreset_clr_ctrl2); 1047 1048 return 0; 1049 } 1050 1051 #define SCU_CLKSTOP_EXTSD 31 1052 #define SCU_CLK_SD_MASK (0x7 << 28) 1053 #define SCU_CLK_SD_DIV(x) ((x) << 28) 1054 #define SCU_CLK_SD_FROM_APLL_CLK BIT(8) 1055 1056 static ulong ast2600_enable_extsdclk(struct ast2600_scu *scu) 1057 { 1058 u32 clk_sel = readl(&scu->clk_sel4); 1059 u32 enableclk_bit; 1060 u32 rate = 0; 1061 u32 div = 0; 1062 int i = 0; 1063 1064 enableclk_bit = BIT(SCU_CLKSTOP_EXTSD); 1065 1066 /* ast2600 sd controller max clk is 200Mhz : 1067 * use apll for clock source 800/4 = 200 : controller max is 200mhz 1068 */ 1069 rate = ast2600_get_apll_rate(scu); 1070 for (i = 0; i < 8; i++) { 1071 div = (i + 1) * 2; 1072 if ((rate / div) <= 200000000) 1073 break; 1074 } 1075 clk_sel &= ~SCU_CLK_SD_MASK; 1076 clk_sel |= SCU_CLK_SD_DIV(i) | SCU_CLK_SD_FROM_APLL_CLK; 1077 writel(clk_sel, &scu->clk_sel4); 1078 1079 //enable clk 1080 setbits_le32(&scu->clk_sel4, enableclk_bit); 1081 1082 return 0; 1083 } 1084 1085 #define SCU_CLKSTOP_EMMC 27 1086 static ulong ast2600_enable_emmcclk(struct ast2600_scu *scu) 1087 { 1088 u32 reset_bit; 1089 u32 clkstop_bit; 1090 1091 reset_bit = BIT(ASPEED_RESET_EMMC); 1092 clkstop_bit = BIT(SCU_CLKSTOP_EMMC); 1093 1094 writel(reset_bit, &scu->sysreset_ctrl1); 1095 udelay(100); 1096 //enable clk 1097 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 1098 mdelay(10); 1099 writel(reset_bit, &scu->sysreset_clr_ctrl1); 1100 1101 return 0; 1102 } 1103 1104 #define SCU_CLKSTOP_EXTEMMC 15 1105 #define SCU_CLK_EMMC_MASK (0x7 << 12) 1106 #define SCU_CLK_EMMC_DIV(x) ((x) << 12) 1107 #define SCU_CLK_EMMC_FROM_MPLL_CLK BIT(11) 1108 1109 static ulong ast2600_enable_extemmcclk(struct ast2600_scu *scu) 1110 { 1111 u32 revision_id = readl(&scu->chip_id1); 1112 u32 clk_sel = readl(&scu->clk_sel1); 1113 u32 enableclk_bit = BIT(SCU_CLKSTOP_EXTEMMC); 1114 u32 rate = 0; 1115 u32 div = 0; 1116 int i = 0; 1117 1118 /* 1119 * ast2600 eMMC controller max clk is 200Mhz 1120 * HPll->1/2->|\ 1121 * |->SCU300[11]->SCU300[14:12][1/N] + 1122 * MPLL------>|/ | 1123 * +----------------------------------------------+ 1124 * | 1125 * +---------> EMMC12C[15:8][1/N]-> eMMC clk 1126 */ 1127 if (((revision_id & CHIP_REVISION_ID) >> 16)) { 1128 //AST2600A1 : use mpll to be clk source 1129 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL); 1130 for (i = 0; i < 8; i++) { 1131 div = (i + 1) * 2; 1132 if ((rate / div) <= 200000000) 1133 break; 1134 } 1135 1136 clk_sel &= ~SCU_CLK_EMMC_MASK; 1137 clk_sel |= SCU_CLK_EMMC_DIV(i) | SCU_CLK_EMMC_FROM_MPLL_CLK; 1138 writel(clk_sel, &scu->clk_sel1); 1139 1140 } else { 1141 //AST2600A0 : use hpll to be clk source 1142 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 1143 1144 for (i = 0; i < 8; i++) { 1145 div = (i + 1) * 4; 1146 if ((rate / div) <= 200000000) 1147 break; 1148 } 1149 1150 clk_sel &= ~SCU_CLK_EMMC_MASK; 1151 clk_sel |= SCU_CLK_EMMC_DIV(i); 1152 writel(clk_sel, &scu->clk_sel1); 1153 } 1154 setbits_le32(&scu->clk_sel1, enableclk_bit); 1155 1156 return 0; 1157 } 1158 1159 #define SCU_CLKSTOP_FSICLK 30 1160 1161 static ulong ast2600_enable_fsiclk(struct ast2600_scu *scu) 1162 { 1163 u32 reset_bit; 1164 u32 clkstop_bit; 1165 1166 reset_bit = BIT(ASPEED_RESET_FSI % 32); 1167 clkstop_bit = BIT(SCU_CLKSTOP_FSICLK); 1168 1169 /* The FSI clock is shared between masters. If it's already on 1170 * don't touch it, as that will reset the existing master. 1171 */ 1172 if (!(readl(&scu->clk_stop_ctrl2) & clkstop_bit)) { 1173 debug("%s: already running, not touching it\n", __func__); 1174 return 0; 1175 } 1176 1177 writel(reset_bit, &scu->sysreset_ctrl2); 1178 udelay(100); 1179 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 1180 mdelay(10); 1181 writel(reset_bit, &scu->sysreset_clr_ctrl2); 1182 1183 return 0; 1184 } 1185 1186 static ulong ast2600_enable_usbahclk(struct ast2600_scu *scu) 1187 { 1188 u32 reset_bit; 1189 u32 clkstop_bit; 1190 1191 reset_bit = BIT(ASPEED_RESET_EHCI_P1); 1192 clkstop_bit = BIT(14); 1193 1194 writel(reset_bit, &scu->sysreset_ctrl1); 1195 udelay(100); 1196 writel(clkstop_bit, &scu->clk_stop_ctrl1); 1197 mdelay(20); 1198 writel(reset_bit, &scu->sysreset_clr_ctrl1); 1199 1200 return 0; 1201 } 1202 1203 static ulong ast2600_enable_usbbhclk(struct ast2600_scu *scu) 1204 { 1205 u32 reset_bit; 1206 u32 clkstop_bit; 1207 1208 reset_bit = BIT(ASPEED_RESET_EHCI_P2); 1209 clkstop_bit = BIT(7); 1210 1211 writel(reset_bit, &scu->sysreset_ctrl1); 1212 udelay(100); 1213 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 1214 mdelay(20); 1215 1216 writel(reset_bit, &scu->sysreset_clr_ctrl1); 1217 1218 return 0; 1219 } 1220 1221 /* also known as yclk */ 1222 static ulong ast2600_enable_haceclk(struct ast2600_scu *scu) 1223 { 1224 u32 reset_bit; 1225 u32 clkstop_bit; 1226 1227 reset_bit = BIT(ASPEED_RESET_HACE); 1228 clkstop_bit = BIT(13); 1229 1230 writel(reset_bit, &scu->sysreset_ctrl1); 1231 udelay(100); 1232 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 1233 mdelay(20); 1234 1235 writel(reset_bit, &scu->sysreset_clr_ctrl1); 1236 1237 return 0; 1238 } 1239 1240 static ulong ast2600_enable_rsaeccclk(struct ast2600_scu *scu) 1241 { 1242 u32 clkstop_bit; 1243 1244 clkstop_bit = BIT(24); 1245 1246 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 1247 mdelay(20); 1248 1249 return 0; 1250 } 1251 1252 static int ast2600_clk_enable(struct clk *clk) 1253 { 1254 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 1255 1256 switch (clk->id) { 1257 case ASPEED_CLK_GATE_MAC1CLK: 1258 ast2600_configure_mac(priv->scu, 1); 1259 break; 1260 case ASPEED_CLK_GATE_MAC2CLK: 1261 ast2600_configure_mac(priv->scu, 2); 1262 break; 1263 case ASPEED_CLK_GATE_MAC3CLK: 1264 ast2600_configure_mac(priv->scu, 3); 1265 break; 1266 case ASPEED_CLK_GATE_MAC4CLK: 1267 ast2600_configure_mac(priv->scu, 4); 1268 break; 1269 case ASPEED_CLK_GATE_SDCLK: 1270 ast2600_enable_sdclk(priv->scu); 1271 break; 1272 case ASPEED_CLK_GATE_SDEXTCLK: 1273 ast2600_enable_extsdclk(priv->scu); 1274 break; 1275 case ASPEED_CLK_GATE_EMMCCLK: 1276 ast2600_enable_emmcclk(priv->scu); 1277 break; 1278 case ASPEED_CLK_GATE_EMMCEXTCLK: 1279 ast2600_enable_extemmcclk(priv->scu); 1280 break; 1281 case ASPEED_CLK_GATE_FSICLK: 1282 ast2600_enable_fsiclk(priv->scu); 1283 break; 1284 case ASPEED_CLK_GATE_USBPORT1CLK: 1285 ast2600_enable_usbahclk(priv->scu); 1286 break; 1287 case ASPEED_CLK_GATE_USBPORT2CLK: 1288 ast2600_enable_usbbhclk(priv->scu); 1289 break; 1290 case ASPEED_CLK_GATE_YCLK: 1291 ast2600_enable_haceclk(priv->scu); 1292 break; 1293 case ASPEED_CLK_GATE_RSAECCCLK: 1294 ast2600_enable_rsaeccclk(priv->scu); 1295 break; 1296 default: 1297 pr_err("can't enable clk\n"); 1298 return -ENOENT; 1299 } 1300 1301 return 0; 1302 } 1303 1304 struct clk_ops ast2600_clk_ops = { 1305 .get_rate = ast2600_clk_get_rate, 1306 .set_rate = ast2600_clk_set_rate, 1307 .enable = ast2600_clk_enable, 1308 }; 1309 1310 static int ast2600_clk_probe(struct udevice *dev) 1311 { 1312 struct ast2600_clk_priv *priv = dev_get_priv(dev); 1313 u32 uart_clk_source; 1314 1315 priv->scu = devfdt_get_addr_ptr(dev); 1316 if (IS_ERR(priv->scu)) 1317 return PTR_ERR(priv->scu); 1318 1319 uart_clk_source = dev_read_u32_default(dev, "uart-clk-source", 0x0); 1320 1321 if (uart_clk_source) { 1322 if (uart_clk_source & GENMASK(5, 0)) 1323 setbits_le32(&priv->scu->clk_sel4, 1324 uart_clk_source & GENMASK(5, 0)); 1325 if (uart_clk_source & GENMASK(12, 6)) 1326 setbits_le32(&priv->scu->clk_sel5, 1327 uart_clk_source & GENMASK(12, 6)); 1328 } 1329 1330 ast2600_init_rgmii_clk(priv->scu, &rgmii_clk_defconfig); 1331 ast2600_init_rmii_clk(priv->scu, &rmii_clk_defconfig); 1332 ast2600_configure_mac12_clk(priv->scu, dev); 1333 ast2600_configure_mac34_clk(priv->scu, dev); 1334 ast2600_configure_rsa_ecc_clk(priv->scu); 1335 1336 return 0; 1337 } 1338 1339 static int ast2600_clk_bind(struct udevice *dev) 1340 { 1341 int ret; 1342 1343 /* The reset driver does not have a device node, so bind it here */ 1344 ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev); 1345 if (ret) 1346 debug("Warning: No reset driver: ret=%d\n", ret); 1347 1348 return 0; 1349 } 1350 1351 struct aspeed_clks { 1352 ulong id; 1353 const char *name; 1354 }; 1355 1356 static struct aspeed_clks aspeed_clk_names[] = { 1357 { ASPEED_CLK_HPLL, "hpll" }, { ASPEED_CLK_MPLL, "mpll" }, 1358 { ASPEED_CLK_APLL, "apll" }, { ASPEED_CLK_EPLL, "epll" }, 1359 { ASPEED_CLK_DPLL, "dpll" }, { ASPEED_CLK_AHB, "hclk" }, 1360 { ASPEED_CLK_APB1, "pclk1" }, { ASPEED_CLK_APB2, "pclk2" }, 1361 { ASPEED_CLK_BCLK, "bclk" }, { ASPEED_CLK_UARTX, "uxclk" }, 1362 { ASPEED_CLK_HUARTX, "huxclk" }, 1363 }; 1364 1365 int soc_clk_dump(void) 1366 { 1367 struct udevice *dev; 1368 struct clk clk; 1369 unsigned long rate; 1370 int i, ret; 1371 1372 ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu), 1373 &dev); 1374 if (ret) 1375 return ret; 1376 1377 printf("Clk\t\tHz\n"); 1378 1379 for (i = 0; i < ARRAY_SIZE(aspeed_clk_names); i++) { 1380 clk.id = aspeed_clk_names[i].id; 1381 ret = clk_request(dev, &clk); 1382 if (ret < 0) { 1383 debug("%s clk_request() failed: %d\n", __func__, ret); 1384 continue; 1385 } 1386 1387 ret = clk_get_rate(&clk); 1388 rate = ret; 1389 1390 clk_free(&clk); 1391 1392 if (ret == -ENOTSUPP) { 1393 printf("clk ID %lu not supported yet\n", 1394 aspeed_clk_names[i].id); 1395 continue; 1396 } 1397 if (ret < 0) { 1398 printf("%s %lu: get_rate err: %d\n", __func__, 1399 aspeed_clk_names[i].id, ret); 1400 continue; 1401 } 1402 1403 printf("%s(%3lu):\t%lu\n", aspeed_clk_names[i].name, 1404 aspeed_clk_names[i].id, rate); 1405 } 1406 1407 return 0; 1408 } 1409 1410 static const struct udevice_id ast2600_clk_ids[] = { 1411 { 1412 .compatible = "aspeed,ast2600-scu", 1413 }, 1414 {} 1415 }; 1416 1417 U_BOOT_DRIVER(aspeed_scu) = { 1418 .name = "aspeed_scu", 1419 .id = UCLASS_CLK, 1420 .of_match = ast2600_clk_ids, 1421 .priv_auto_alloc_size = sizeof(struct ast2600_clk_priv), 1422 .ops = &ast2600_clk_ops, 1423 .bind = ast2600_clk_bind, 1424 .probe = ast2600_clk_probe, 1425 }; 1426