1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 */ 5 6 #include <common.h> 7 #include <clk-uclass.h> 8 #include <dm.h> 9 #include <asm/io.h> 10 #include <dm/lists.h> 11 #include <asm/arch/scu_ast2600.h> 12 #include <dt-bindings/clock/ast2600-clock.h> 13 #include <dt-bindings/reset/ast2600-reset.h> 14 15 /* 16 * MAC Clock Delay settings 17 */ 18 #define RGMII_TXCLK_ODLY 8 19 #define RMII_RXCLK_IDLY 2 20 21 #define MAC_DEF_DELAY_1G 0x0041b75d 22 #define MAC_DEF_DELAY_100M 0x00417410 23 #define MAC_DEF_DELAY_10M 0x00417410 24 25 #define MAC34_DEF_DELAY_1G 0x0010438a 26 #define MAC34_DEF_DELAY_100M 0x00104208 27 #define MAC34_DEF_DELAY_10M 0x00104208 28 29 /* 30 * TGMII Clock Duty constants, taken from Aspeed SDK 31 */ 32 #define RGMII2_TXCK_DUTY 0x66 33 #define RGMII1_TXCK_DUTY 0x64 34 35 #define D2PLL_DEFAULT_RATE (250 * 1000 * 1000) 36 37 #define CHIP_REVISION_ID GENMASK(23, 16) 38 39 DECLARE_GLOBAL_DATA_PTR; 40 41 /* 42 * Clock divider/multiplier configuration struct. 43 * For H-PLL and M-PLL the formula is 44 * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1) 45 * M - Numerator 46 * N - Denumerator 47 * P - Post Divider 48 * They have the same layout in their control register. 49 * 50 * D-PLL and D2-PLL have extra divider (OD + 1), which is not 51 * yet needed and ignored by clock configurations. 52 */ 53 union ast2600_pll_reg { 54 unsigned int w; 55 struct { 56 unsigned int m : 13; /* bit[12:0] */ 57 unsigned int n : 6; /* bit[18:13] */ 58 unsigned int p : 4; /* bit[22:19] */ 59 unsigned int off : 1; /* bit[23] */ 60 unsigned int bypass : 1; /* bit[24] */ 61 unsigned int reset : 1; /* bit[25] */ 62 unsigned int reserved : 6; /* bit[31:26] */ 63 } b; 64 }; 65 66 struct ast2600_pll_cfg { 67 union ast2600_pll_reg reg; 68 unsigned int ext_reg; 69 }; 70 71 struct ast2600_pll_desc { 72 u32 in; 73 u32 out; 74 struct ast2600_pll_cfg cfg; 75 }; 76 77 static const struct ast2600_pll_desc ast2600_pll_lookup[] = { 78 { 79 .in = AST2600_CLK_IN, .out = 400000000, 80 .cfg.reg.b.m = 95, .cfg.reg.b.n = 2, .cfg.reg.b.p = 1, 81 .cfg.ext_reg = 0x31, 82 },{ 83 .in = AST2600_CLK_IN, .out = 200000000, 84 .cfg.reg.b.m = 127, .cfg.reg.b.n = 0, .cfg.reg.b.p = 15, 85 .cfg.ext_reg = 0x3f 86 },{ 87 .in = AST2600_CLK_IN, .out = 334000000, 88 .cfg.reg.b.m = 667, .cfg.reg.b.n = 4, .cfg.reg.b.p = 9, 89 .cfg.ext_reg = 0x14d 90 },{ 91 .in = AST2600_CLK_IN, .out = 1000000000, 92 .cfg.reg.b.m = 119, .cfg.reg.b.n = 2, .cfg.reg.b.p = 0, 93 .cfg.ext_reg = 0x3d 94 },{ 95 .in = AST2600_CLK_IN, .out = 50000000, 96 .cfg.reg.b.m = 95, .cfg.reg.b.n = 2, .cfg.reg.b.p = 15, 97 .cfg.ext_reg = 0x31 98 }, 99 }; 100 101 extern u32 ast2600_get_pll_rate(struct ast2600_scu *scu, int pll_idx) 102 { 103 u32 clkin = AST2600_CLK_IN; 104 u32 pll_reg = 0; 105 unsigned int mult, div = 1; 106 107 switch(pll_idx) { 108 case ASPEED_CLK_HPLL: 109 pll_reg = readl(&scu->h_pll_param); 110 break; 111 case ASPEED_CLK_MPLL: 112 pll_reg = readl(&scu->m_pll_param); 113 break; 114 case ASPEED_CLK_DPLL: 115 pll_reg = readl(&scu->d_pll_param); 116 break; 117 case ASPEED_CLK_EPLL: 118 pll_reg = readl(&scu->e_pll_param); 119 break; 120 } 121 if (pll_reg & BIT(24)) { 122 /* Pass through mode */ 123 mult = div = 1; 124 } else { 125 /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) */ 126 union ast2600_pll_reg reg; 127 reg.w = pll_reg; 128 if(pll_idx == ASPEED_CLK_HPLL) { 129 /* 130 HPLL Numerator (M) = fix 0x5F when SCU500[10]=1 131 fix 0xBF when SCU500[10]=0 and SCU500[8]=1 132 SCU200[12:0] (default 0x8F) when SCU510[10]=0 and SCU510[8]=0 133 HPLL Denumerator (N) = SCU200[18:13] (default 0x2) 134 HPLL Divider (P) = SCU200[22:19] (default 0x0) 135 HPLL Bandwidth Adj (NB) = fix 0x2F when SCU500[10]=1 136 fix 0x5F when SCU500[10]=0 and SCU500[8]=1 137 SCU204[11:0] (default 0x31) when SCU500[10]=0 and SCU500[8]=0 138 */ 139 u32 hwstrap1 = readl(&scu->hwstrap1.hwstrap); 140 if(hwstrap1 & BIT(10)) 141 reg.b.m = 0x5F; 142 else { 143 if(hwstrap1 & BIT(8)) 144 reg.b.m = 0xBF; 145 /* Otherwise keep default 0x8F */ 146 } 147 } 148 mult = (reg.b.m + 1) / (reg.b.n + 1); 149 div = (reg.b.p + 1); 150 } 151 152 return ((clkin * mult)/div); 153 } 154 155 extern u32 ast2600_get_apll_rate(struct ast2600_scu *scu) 156 { 157 u32 hw_rev = readl(&scu->chip_id1); 158 u32 clkin = AST2600_CLK_IN; 159 u32 apll_reg = readl(&scu->a_pll_param); 160 unsigned int mult, div = 1; 161 162 if (((hw_rev & CHIP_REVISION_ID) >> 16) >= 3) { 163 //after A2 version 164 if (apll_reg & BIT(24)) { 165 /* Pass through mode */ 166 mult = div = 1; 167 } else { 168 /* F = 25Mhz * [(m + 1) / (n + 1)] / (p + 1) */ 169 u32 m = apll_reg & 0x1fff; 170 u32 n = (apll_reg >> 13) & 0x3f; 171 u32 p = (apll_reg >> 19) & 0xf; 172 173 mult = (m + 1); 174 div = (n + 1) * (p + 1); 175 } 176 177 } else { 178 if (apll_reg & BIT(20)) { 179 /* Pass through mode */ 180 mult = div = 1; 181 } else { 182 /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */ 183 u32 m = (apll_reg >> 5) & 0x3f; 184 u32 od = (apll_reg >> 4) & 0x1; 185 u32 n = apll_reg & 0xf; 186 187 mult = (2 - od) * (m + 2); 188 div = n + 1; 189 } 190 } 191 192 return ((clkin * mult)/div); 193 } 194 195 static u32 ast2600_a0_axi_ahb_div_table[] = { 196 2, 2, 3, 4, 197 }; 198 199 static u32 ast2600_a1_axi_ahb_div0_table[] = { 200 3, 2, 3, 4, 201 }; 202 203 static u32 ast2600_a1_axi_ahb_div1_table[] = { 204 3, 4, 6, 8, 205 }; 206 207 static u32 ast2600_a1_axi_ahb_default_table[] = { 208 3, 4, 3, 4, 2, 2, 2, 2, 209 }; 210 211 static u32 ast2600_get_hclk(struct ast2600_scu *scu) 212 { 213 u32 hw_rev = readl(&scu->chip_id1); 214 u32 hwstrap1 = readl(&scu->hwstrap1.hwstrap); 215 u32 axi_div = 1; 216 u32 ahb_div = 0; 217 u32 rate = 0; 218 219 if ((hw_rev & CHIP_REVISION_ID) >> 16) { 220 //After A0 221 if(hwstrap1 & BIT(16)) { 222 ast2600_a1_axi_ahb_div1_table[0] = 223 ast2600_a1_axi_ahb_default_table[(hwstrap1 >> 8) & 0x3]; 224 axi_div = 1; 225 ahb_div = ast2600_a1_axi_ahb_div1_table[(hwstrap1 >> 11) & 0x3]; 226 } else { 227 ast2600_a1_axi_ahb_div0_table[0] = 228 ast2600_a1_axi_ahb_default_table[(hwstrap1 >> 8) & 0x3]; 229 axi_div = 2; 230 ahb_div = ast2600_a1_axi_ahb_div0_table[(hwstrap1 >> 11) & 0x3]; 231 } 232 } else { 233 //A0 : fix axi = hpll / 2 234 axi_div = 2; 235 ahb_div = ast2600_a0_axi_ahb_div_table[(hwstrap1 >> 11) & 0x3]; 236 } 237 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 238 239 return (rate / axi_div / ahb_div); 240 } 241 242 static u32 ast2600_get_bclk_rate(struct ast2600_scu *scu) 243 { 244 u32 rate; 245 u32 bclk_sel = (readl(&scu->clk_sel1) >> 20) & 0x7; 246 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 247 248 return (rate /((bclk_sel + 1) * 4)); 249 } 250 251 static u32 ast2600_hpll_pclk1_div_table[] = { 252 4, 8, 12, 16, 20, 24, 28, 32, 253 }; 254 255 static u32 ast2600_hpll_pclk2_div_table[] = { 256 2, 4, 6, 8, 10, 12, 14, 16, 257 }; 258 259 static u32 ast2600_get_pclk1(struct ast2600_scu *scu) 260 { 261 u32 clk_sel1 = readl(&scu->clk_sel1); 262 u32 apb_div = ast2600_hpll_pclk1_div_table[((clk_sel1 >> 23) & 0x7)]; 263 u32 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 264 265 return (rate / apb_div); 266 } 267 268 static u32 ast2600_get_pclk2(struct ast2600_scu *scu) 269 { 270 u32 clk_sel4 = readl(&scu->clk_sel4); 271 u32 apb_div = ast2600_hpll_pclk2_div_table[((clk_sel4 >> 9) & 0x7)]; 272 u32 rate = ast2600_get_hclk(scu); 273 274 return (rate / apb_div); 275 } 276 277 static u32 ast2600_get_uxclk_in_rate(struct ast2600_scu *scu) 278 { 279 u32 clk_in = 0; 280 u32 uxclk_sel = readl(&scu->clk_sel5); 281 282 uxclk_sel &= 0x3; 283 switch(uxclk_sel) { 284 case 0: 285 clk_in = ast2600_get_apll_rate(scu) / 4; 286 break; 287 case 1: 288 clk_in = ast2600_get_apll_rate(scu) / 2; 289 break; 290 case 2: 291 clk_in = ast2600_get_apll_rate(scu); 292 break; 293 case 3: 294 clk_in = ast2600_get_hclk(scu); 295 break; 296 } 297 298 return clk_in; 299 } 300 301 static u32 ast2600_get_huxclk_in_rate(struct ast2600_scu *scu) 302 { 303 u32 clk_in = 0; 304 u32 huclk_sel = readl(&scu->clk_sel5); 305 306 huclk_sel = ((huclk_sel >> 3) & 0x3); 307 switch(huclk_sel) { 308 case 0: 309 clk_in = ast2600_get_apll_rate(scu) / 4; 310 break; 311 case 1: 312 clk_in = ast2600_get_apll_rate(scu) / 2; 313 break; 314 case 2: 315 clk_in = ast2600_get_apll_rate(scu); 316 break; 317 case 3: 318 clk_in = ast2600_get_hclk(scu); 319 break; 320 } 321 322 return clk_in; 323 } 324 325 static u32 ast2600_get_uart_uxclk_rate(struct ast2600_scu *scu) 326 { 327 u32 clk_in = ast2600_get_uxclk_in_rate(scu); 328 u32 div_reg = readl(&scu->uart_24m_ref_uxclk); 329 unsigned int mult, div; 330 331 u32 n = (div_reg >> 8) & 0x3ff; 332 u32 r = div_reg & 0xff; 333 334 mult = r; 335 div = (n * 2); 336 return (clk_in * mult)/div; 337 } 338 339 static u32 ast2600_get_uart_huxclk_rate(struct ast2600_scu *scu) 340 { 341 u32 clk_in = ast2600_get_huxclk_in_rate(scu); 342 u32 div_reg = readl(&scu->uart_24m_ref_huxclk); 343 344 unsigned int mult, div; 345 346 u32 n = (div_reg >> 8) & 0x3ff; 347 u32 r = div_reg & 0xff; 348 349 mult = r; 350 div = (n * 2); 351 return (clk_in * mult)/div; 352 } 353 354 static u32 ast2600_get_sdio_clk_rate(struct ast2600_scu *scu) 355 { 356 u32 clkin = 0; 357 u32 clk_sel = readl(&scu->clk_sel4); 358 u32 div = (clk_sel >> 28) & 0x7; 359 360 if(clk_sel & BIT(8)) { 361 clkin = ast2600_get_apll_rate(scu); 362 } else { 363 clkin = ast2600_get_hclk(scu); 364 } 365 div = (div + 1) << 1; 366 367 return (clkin / div); 368 } 369 370 static u32 ast2600_get_emmc_clk_rate(struct ast2600_scu *scu) 371 { 372 u32 clkin = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 373 u32 clk_sel = readl(&scu->clk_sel1); 374 u32 div = (clk_sel >> 12) & 0x7; 375 376 div = (div + 1) << 2; 377 378 return (clkin / div); 379 } 380 381 static u32 ast2600_get_uart_clk_rate(struct ast2600_scu *scu, int uart_idx) 382 { 383 u32 uart_sel = readl(&scu->clk_sel4); 384 u32 uart_sel5 = readl(&scu->clk_sel5); 385 ulong uart_clk = 0; 386 387 switch(uart_idx) { 388 case 1: 389 case 2: 390 case 3: 391 case 4: 392 case 6: 393 if(uart_sel & BIT(uart_idx - 1)) 394 uart_clk = ast2600_get_uart_huxclk_rate(scu) ; 395 else 396 uart_clk = ast2600_get_uart_uxclk_rate(scu) ; 397 break; 398 case 5: //24mhz is come form usb phy 48Mhz 399 { 400 u8 uart5_clk_sel = 0; 401 //high bit 402 if (readl(&scu->misc_ctrl1) & BIT(12)) 403 uart5_clk_sel = 0x2; 404 else 405 uart5_clk_sel = 0x0; 406 407 if (readl(&scu->clk_sel2) & BIT(14)) 408 uart5_clk_sel |= 0x1; 409 410 switch(uart5_clk_sel) { 411 case 0: 412 uart_clk = 24000000; 413 break; 414 case 1: 415 uart_clk = 192000000; 416 break; 417 case 2: 418 uart_clk = 24000000/13; 419 break; 420 case 3: 421 uart_clk = 192000000/13; 422 break; 423 } 424 } 425 break; 426 case 7: 427 case 8: 428 case 9: 429 case 10: 430 case 11: 431 case 12: 432 case 13: 433 if(uart_sel5 & BIT(uart_idx - 1)) 434 uart_clk = ast2600_get_uart_huxclk_rate(scu); 435 else 436 uart_clk = ast2600_get_uart_uxclk_rate(scu); 437 break; 438 } 439 440 return uart_clk; 441 } 442 443 static ulong ast2600_clk_get_rate(struct clk *clk) 444 { 445 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 446 ulong rate = 0; 447 448 switch (clk->id) { 449 case ASPEED_CLK_HPLL: 450 case ASPEED_CLK_EPLL: 451 case ASPEED_CLK_DPLL: 452 case ASPEED_CLK_MPLL: 453 rate = ast2600_get_pll_rate(priv->scu, clk->id); 454 break; 455 case ASPEED_CLK_AHB: 456 rate = ast2600_get_hclk(priv->scu); 457 break; 458 case ASPEED_CLK_APB1: 459 rate = ast2600_get_pclk1(priv->scu); 460 break; 461 case ASPEED_CLK_APB2: 462 rate = ast2600_get_pclk2(priv->scu); 463 break; 464 case ASPEED_CLK_APLL: 465 rate = ast2600_get_apll_rate(priv->scu); 466 break; 467 case ASPEED_CLK_GATE_UART1CLK: 468 rate = ast2600_get_uart_clk_rate(priv->scu, 1); 469 break; 470 case ASPEED_CLK_GATE_UART2CLK: 471 rate = ast2600_get_uart_clk_rate(priv->scu, 2); 472 break; 473 case ASPEED_CLK_GATE_UART3CLK: 474 rate = ast2600_get_uart_clk_rate(priv->scu, 3); 475 break; 476 case ASPEED_CLK_GATE_UART4CLK: 477 rate = ast2600_get_uart_clk_rate(priv->scu, 4); 478 break; 479 case ASPEED_CLK_GATE_UART5CLK: 480 rate = ast2600_get_uart_clk_rate(priv->scu, 5); 481 break; 482 case ASPEED_CLK_BCLK: 483 rate = ast2600_get_bclk_rate(priv->scu); 484 break; 485 case ASPEED_CLK_SDIO: 486 rate = ast2600_get_sdio_clk_rate(priv->scu); 487 break; 488 case ASPEED_CLK_EMMC: 489 rate = ast2600_get_emmc_clk_rate(priv->scu); 490 break; 491 case ASPEED_CLK_UARTX: 492 rate = ast2600_get_uart_uxclk_rate(priv->scu); 493 break; 494 case ASPEED_CLK_HUARTX: 495 rate = ast2600_get_uart_huxclk_rate(priv->scu); 496 break; 497 default: 498 pr_debug("can't get clk rate \n"); 499 return -ENOENT; 500 break; 501 } 502 503 return rate; 504 } 505 506 /** 507 * @brief lookup PLL divider config by input/output rate 508 * @param[in] *pll - PLL descriptor 509 * @return true - if PLL divider config is found, false - else 510 * 511 * The function caller shall fill "pll->in" and "pll->out", 512 * then this function will search the lookup table 513 * to find a valid PLL divider configuration. 514 */ 515 static bool ast2600_search_clock_config(struct ast2600_pll_desc *pll) 516 { 517 u32 i; 518 bool is_found = false; 519 520 for (i = 0; i < ARRAY_SIZE(ast2600_pll_lookup); i++) { 521 const struct ast2600_pll_desc *def_cfg = &ast2600_pll_lookup[i]; 522 if ((def_cfg->in == pll->in) && (def_cfg->out == pll->out)) { 523 is_found = true; 524 pll->cfg.reg.w = def_cfg->cfg.reg.w; 525 pll->cfg.ext_reg = def_cfg->cfg.ext_reg; 526 break; 527 } 528 } 529 return is_found; 530 } 531 static u32 ast2600_configure_pll(struct ast2600_scu *scu, 532 struct ast2600_pll_cfg *p_cfg, int pll_idx) 533 { 534 u32 addr, addr_ext; 535 u32 reg; 536 537 switch (pll_idx) { 538 case ASPEED_CLK_HPLL: 539 addr = (u32)(&scu->h_pll_param); 540 addr_ext = (u32)(&scu->h_pll_ext_param); 541 break; 542 case ASPEED_CLK_MPLL: 543 addr = (u32)(&scu->m_pll_param); 544 addr_ext = (u32)(&scu->m_pll_ext_param); 545 break; 546 case ASPEED_CLK_DPLL: 547 addr = (u32)(&scu->d_pll_param); 548 addr_ext = (u32)(&scu->d_pll_ext_param); 549 break; 550 case ASPEED_CLK_EPLL: 551 addr = (u32)(&scu->e_pll_param); 552 addr_ext = (u32)(&scu->e_pll_ext_param); 553 break; 554 default: 555 debug("unknown PLL index\n"); 556 return 1; 557 } 558 559 p_cfg->reg.b.bypass = 0; 560 p_cfg->reg.b.off = 1; 561 p_cfg->reg.b.reset = 1; 562 563 reg = readl(addr); 564 reg &= ~GENMASK(25, 0); 565 reg |= p_cfg->reg.w; 566 writel(reg, addr); 567 568 /* write extend parameter */ 569 writel(p_cfg->ext_reg, addr_ext); 570 udelay(100); 571 p_cfg->reg.b.off = 0; 572 p_cfg->reg.b.reset = 0; 573 reg &= ~GENMASK(25, 0); 574 reg |= p_cfg->reg.w; 575 writel(reg, addr); 576 577 /* polling PLL lock status */ 578 while(0 == (readl(addr_ext) & BIT(31))); 579 580 return 0; 581 } 582 static u32 ast2600_configure_ddr(struct ast2600_scu *scu, ulong rate) 583 { 584 struct ast2600_pll_desc mpll; 585 586 mpll.in = AST2600_CLK_IN; 587 mpll.out = rate; 588 if (false == ast2600_search_clock_config(&mpll)) { 589 printf("error!! unable to find valid DDR clock setting\n"); 590 return 0; 591 } 592 ast2600_configure_pll(scu, &(mpll.cfg), ASPEED_CLK_MPLL); 593 594 return ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL); 595 } 596 597 static ulong ast2600_clk_set_rate(struct clk *clk, ulong rate) 598 { 599 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 600 601 ulong new_rate; 602 switch (clk->id) { 603 case ASPEED_CLK_MPLL: 604 new_rate = ast2600_configure_ddr(priv->scu, rate); 605 break; 606 default: 607 return -ENOENT; 608 } 609 610 return new_rate; 611 } 612 613 #define SCU_CLKSTOP_MAC1 (20) 614 #define SCU_CLKSTOP_MAC2 (21) 615 #define SCU_CLKSTOP_MAC3 (20) 616 #define SCU_CLKSTOP_MAC4 (21) 617 618 static u32 ast2600_configure_mac12_clk(struct ast2600_scu *scu) 619 { 620 /* scu340[25:0]: 1G default delay */ 621 clrsetbits_le32(&scu->mac12_clk_delay, GENMASK(25, 0), 622 MAC_DEF_DELAY_1G); 623 624 /* set 100M/10M default delay */ 625 writel(MAC_DEF_DELAY_100M, &scu->mac12_clk_delay_100M); 626 writel(MAC_DEF_DELAY_10M, &scu->mac12_clk_delay_10M); 627 628 /* MAC AHB = HPLL / 6 */ 629 clrsetbits_le32(&scu->clk_sel1, GENMASK(18, 16), (0x2 << 16)); 630 631 return 0; 632 } 633 634 static u32 ast2600_configure_mac34_clk(struct ast2600_scu *scu) 635 { 636 637 /* 638 * scu350[31] RGMII 125M source: 0 = from IO pin 639 * scu350[25:0] MAC 1G delay 640 */ 641 clrsetbits_le32(&scu->mac34_clk_delay, (BIT(31) | GENMASK(25, 0)), 642 MAC34_DEF_DELAY_1G); 643 writel(MAC34_DEF_DELAY_100M, &scu->mac34_clk_delay_100M); 644 writel(MAC34_DEF_DELAY_10M, &scu->mac34_clk_delay_10M); 645 646 /* 647 * clock source seletion and divider 648 * scu310[26:24] : MAC AHB bus clock = HCLK / 2 649 * scu310[18:16] : RMII 50M = HCLK_200M / 4 650 */ 651 clrsetbits_le32(&scu->clk_sel4, (GENMASK(26, 24) | GENMASK(18, 16)), 652 ((0x0 << 24) | (0x3 << 16))); 653 654 /* 655 * set driving strength 656 * scu458[3:2] : MAC4 driving strength 657 * scu458[1:0] : MAC3 driving strength 658 */ 659 clrsetbits_le32(&scu->pinmux_ctrl16, GENMASK(3, 0), 660 (0x3 << 2) | (0x3 << 0)); 661 662 return 0; 663 } 664 665 /** 666 * ast2600 RGMII clock source tree 667 * 668 * 125M from external PAD -------->|\ 669 * HPLL -->|\ | |---->RGMII 125M for MAC#1 & MAC#2 670 * | |---->| divider |---->|/ + 671 * EPLL -->|/ | 672 * | 673 * +---------<-----------|RGMIICK PAD output enable|<-------------+ 674 * | 675 * +--------------------------->|\ 676 * | |----> RGMII 125M for MAC#3 & MAC#4 677 * HCLK 200M ---->|divider|---->|/ 678 * 679 * To simplify the control flow: 680 * 1. RGMII 1/2 always use EPLL as the internal clock source 681 * 2. RGMII 3/4 always use RGMIICK pad as the RGMII 125M source 682 * 683 * 125M from external PAD -------->|\ 684 * | |---->RGMII 125M for MAC#1 & MAC#2 685 * EPLL---->| divider |--->|/ + 686 * | 687 * +<--------------------|RGMIICK PAD output enable|<-------------+ 688 * | 689 * +--------------------------->RGMII 125M for MAC#3 & MAC#4 690 */ 691 #define RGMIICK_SRC_PAD 0 692 #define RGMIICK_SRC_EPLL 1 /* recommended */ 693 #define RGMIICK_SRC_HPLL 2 694 695 #define RGMIICK_DIV2 1 696 #define RGMIICK_DIV3 2 697 #define RGMIICK_DIV4 3 698 #define RGMIICK_DIV5 4 699 #define RGMIICK_DIV6 5 700 #define RGMIICK_DIV7 6 701 #define RGMIICK_DIV8 7 /* recommended */ 702 703 #define RMIICK_DIV4 0 704 #define RMIICK_DIV8 1 705 #define RMIICK_DIV12 2 706 #define RMIICK_DIV16 3 707 #define RMIICK_DIV20 4 /* recommended */ 708 #define RMIICK_DIV24 5 709 #define RMIICK_DIV28 6 710 #define RMIICK_DIV32 7 711 712 struct ast2600_mac_clk_div { 713 u32 src; /* 0=external PAD, 1=internal PLL */ 714 u32 fin; /* divider input speed */ 715 u32 n; /* 0=div2, 1=div2, 2=div3, 3=div4,...,7=div8 */ 716 u32 fout; /* fout = fin / n */ 717 }; 718 719 struct ast2600_mac_clk_div rgmii_clk_defconfig = { 720 .src = ASPEED_CLK_EPLL, 721 .fin = 1000000000, 722 .n = RGMIICK_DIV8, 723 .fout = 125000000, 724 }; 725 726 struct ast2600_mac_clk_div rmii_clk_defconfig = { 727 .src = ASPEED_CLK_EPLL, 728 .fin = 1000000000, 729 .n = RMIICK_DIV20, 730 .fout = 50000000, 731 }; 732 static void ast2600_init_mac_pll(struct ast2600_scu *p_scu, 733 struct ast2600_mac_clk_div *p_cfg) 734 { 735 struct ast2600_pll_desc pll; 736 737 pll.in = AST2600_CLK_IN; 738 pll.out = p_cfg->fin; 739 if (false == ast2600_search_clock_config(&pll)) { 740 printf("error!! unable to find valid ETHNET MAC clock " 741 "setting\n"); 742 debug("%s: pll cfg = 0x%08x 0x%08x\n", __func__, pll.cfg.reg.w, 743 pll.cfg.ext_reg); 744 debug("%s: pll cfg = %02x %02x %02x\n", __func__, 745 pll.cfg.reg.b.m, pll.cfg.reg.b.n, pll.cfg.reg.b.p); 746 return; 747 } 748 ast2600_configure_pll(p_scu, &(pll.cfg), p_cfg->src); 749 } 750 751 static void ast2600_init_rgmii_clk(struct ast2600_scu *p_scu, 752 struct ast2600_mac_clk_div *p_cfg) 753 { 754 u32 reg_304 = readl(&p_scu->clk_sel2); 755 u32 reg_340 = readl(&p_scu->mac12_clk_delay); 756 u32 reg_350 = readl(&p_scu->mac34_clk_delay); 757 758 reg_340 &= ~GENMASK(31, 29); 759 /* scu340[28]: RGMIICK PAD output enable (to MAC 3/4) */ 760 reg_340 |= BIT(28); 761 if ((p_cfg->src == ASPEED_CLK_EPLL) || 762 (p_cfg->src == ASPEED_CLK_HPLL)) { 763 /* 764 * re-init PLL if the current PLL output frequency doesn't match 765 * the divider setting 766 */ 767 if (p_cfg->fin != ast2600_get_pll_rate(p_scu, p_cfg->src)) { 768 ast2600_init_mac_pll(p_scu, p_cfg); 769 } 770 /* scu340[31]: select RGMII 125M from internal source */ 771 reg_340 |= BIT(31); 772 } 773 774 reg_304 &= ~GENMASK(23, 20); 775 776 /* set clock divider */ 777 reg_304 |= (p_cfg->n & 0x7) << 20; 778 779 /* select internal clock source */ 780 if (ASPEED_CLK_HPLL == p_cfg->src) { 781 reg_304 |= BIT(23); 782 } 783 784 /* RGMII 3/4 clock source select */ 785 reg_350 &= ~BIT(31); 786 787 writel(reg_304, &p_scu->clk_sel2); 788 writel(reg_340, &p_scu->mac12_clk_delay); 789 writel(reg_350, &p_scu->mac34_clk_delay); 790 } 791 792 /** 793 * ast2600 RMII/NCSI clock source tree 794 * 795 * HPLL -->|\ 796 * | |---->| divider |----> RMII 50M for MAC#1 & MAC#2 797 * EPLL -->|/ 798 * 799 * HCLK(SCLICLK)---->| divider |----> RMII 50M for MAC#3 & MAC#4 800 */ 801 static void ast2600_init_rmii_clk(struct ast2600_scu *p_scu, 802 struct ast2600_mac_clk_div *p_cfg) 803 { 804 u32 reg_304; 805 u32 reg_310; 806 807 if ((p_cfg->src == ASPEED_CLK_EPLL) || 808 (p_cfg->src == ASPEED_CLK_HPLL)) { 809 /* 810 * re-init PLL if the current PLL output frequency doesn't match 811 * the divider setting 812 */ 813 if (p_cfg->fin != ast2600_get_pll_rate(p_scu, p_cfg->src)) { 814 ast2600_init_mac_pll(p_scu, p_cfg); 815 } 816 } 817 818 reg_304 = readl(&p_scu->clk_sel2); 819 reg_310 = readl(&p_scu->clk_sel4); 820 821 reg_304 &= ~GENMASK(19, 16); 822 823 /* set RMII 1/2 clock divider */ 824 reg_304 |= (p_cfg->n & 0x7) << 16; 825 826 /* RMII clock source selection */ 827 if (ASPEED_CLK_HPLL == p_cfg->src) { 828 reg_304 |= BIT(19); 829 } 830 831 /* set RMII 3/4 clock divider */ 832 reg_310 &= ~GENMASK(18, 16); 833 reg_310 |= (0x3 << 16); 834 835 writel(reg_304, &p_scu->clk_sel2); 836 writel(reg_310, &p_scu->clk_sel4); 837 } 838 839 static u32 ast2600_configure_mac(struct ast2600_scu *scu, int index) 840 { 841 u32 reset_bit; 842 u32 clkstop_bit; 843 844 switch (index) { 845 case 1: 846 reset_bit = BIT(ASPEED_RESET_MAC1); 847 clkstop_bit = BIT(SCU_CLKSTOP_MAC1); 848 writel(reset_bit, &scu->sysreset_ctrl1); 849 udelay(100); 850 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 851 mdelay(10); 852 writel(reset_bit, &scu->sysreset_clr_ctrl1); 853 854 break; 855 case 2: 856 reset_bit = BIT(ASPEED_RESET_MAC2); 857 clkstop_bit = BIT(SCU_CLKSTOP_MAC2); 858 writel(reset_bit, &scu->sysreset_ctrl1); 859 udelay(100); 860 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 861 mdelay(10); 862 writel(reset_bit, &scu->sysreset_clr_ctrl1); 863 break; 864 case 3: 865 reset_bit = BIT(ASPEED_RESET_MAC3 - 32); 866 clkstop_bit = BIT(SCU_CLKSTOP_MAC3); 867 writel(reset_bit, &scu->sysreset_ctrl2); 868 udelay(100); 869 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 870 mdelay(10); 871 writel(reset_bit, &scu->sysreset_clr_ctrl2); 872 break; 873 case 4: 874 reset_bit = BIT(ASPEED_RESET_MAC4 - 32); 875 clkstop_bit = BIT(SCU_CLKSTOP_MAC4); 876 writel(reset_bit, &scu->sysreset_ctrl2); 877 udelay(100); 878 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 879 mdelay(10); 880 writel(reset_bit, &scu->sysreset_clr_ctrl2); 881 break; 882 default: 883 return -EINVAL; 884 } 885 886 return 0; 887 } 888 889 #define SCU_CLK_ECC_RSA_FROM_HPLL_CLK BIT(19) 890 #define SCU_CLK_ECC_RSA_CLK_MASK GENMASK(27, 26) 891 #define SCU_CLK_ECC_RSA_CLK_DIV(x) (x << 26) 892 static void ast2600_configure_rsa_ecc_clk(struct ast2600_scu *scu) 893 { 894 u32 clk_sel = readl(&scu->clk_sel1); 895 896 /* Configure RSA clock = HPLL/3 */ 897 clk_sel |= SCU_CLK_ECC_RSA_FROM_HPLL_CLK; 898 clk_sel &= ~SCU_CLK_ECC_RSA_CLK_MASK; 899 clk_sel |= SCU_CLK_ECC_RSA_CLK_DIV(2); 900 901 writel(clk_sel, &scu->clk_sel1); 902 } 903 904 #define SCU_CLKSTOP_SDIO 4 905 static ulong ast2600_enable_sdclk(struct ast2600_scu *scu) 906 { 907 u32 reset_bit; 908 u32 clkstop_bit; 909 910 reset_bit = BIT(ASPEED_RESET_SD - 32); 911 clkstop_bit = BIT(SCU_CLKSTOP_SDIO); 912 913 writel(reset_bit, &scu->sysreset_ctrl2); 914 915 udelay(100); 916 //enable clk 917 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 918 mdelay(10); 919 writel(reset_bit, &scu->sysreset_clr_ctrl2); 920 921 return 0; 922 } 923 924 #define SCU_CLKSTOP_EXTSD 31 925 #define SCU_CLK_SD_MASK (0x7 << 28) 926 #define SCU_CLK_SD_DIV(x) (x << 28) 927 #define SCU_CLK_SD_FROM_APLL_CLK BIT(8) 928 929 static ulong ast2600_enable_extsdclk(struct ast2600_scu *scu) 930 { 931 u32 clk_sel = readl(&scu->clk_sel4); 932 u32 enableclk_bit; 933 u32 rate = 0; 934 u32 div = 0; 935 int i = 0; 936 937 enableclk_bit = BIT(SCU_CLKSTOP_EXTSD); 938 939 /* ast2600 sd controller max clk is 200Mhz : 940 * use apll for clock source 800/4 = 200 : controller max is 200mhz 941 */ 942 rate = ast2600_get_apll_rate(scu); 943 for(i = 0; i < 8; i++) { 944 div = (i + 1) * 2; 945 if ((rate / div) <= 200000000) 946 break; 947 } 948 clk_sel &= ~SCU_CLK_SD_MASK; 949 clk_sel |= SCU_CLK_SD_DIV(i) | SCU_CLK_SD_FROM_APLL_CLK; 950 writel(clk_sel, &scu->clk_sel4); 951 952 //enable clk 953 setbits_le32(&scu->clk_sel4, enableclk_bit); 954 955 return 0; 956 } 957 958 #define SCU_CLKSTOP_EMMC 27 959 static ulong ast2600_enable_emmcclk(struct ast2600_scu *scu) 960 { 961 u32 reset_bit; 962 u32 clkstop_bit; 963 964 reset_bit = BIT(ASPEED_RESET_EMMC); 965 clkstop_bit = BIT(SCU_CLKSTOP_EMMC); 966 967 writel(reset_bit, &scu->sysreset_ctrl1); 968 udelay(100); 969 //enable clk 970 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 971 mdelay(10); 972 writel(reset_bit, &scu->sysreset_clr_ctrl1); 973 974 return 0; 975 } 976 977 #define SCU_CLKSTOP_EXTEMMC 15 978 #define SCU_CLK_EMMC_MASK (0x7 << 12) 979 #define SCU_CLK_EMMC_DIV(x) (x << 12) 980 #define SCU_CLK_EMMC_FROM_MPLL_CLK BIT(11) 981 982 static ulong ast2600_enable_extemmcclk(struct ast2600_scu *scu) 983 { 984 u32 revision_id = readl(&scu->chip_id1); 985 u32 clk_sel = readl(&scu->clk_sel1); 986 u32 enableclk_bit; 987 u32 rate = 0; 988 u32 div = 0; 989 int i = 0; 990 991 enableclk_bit = BIT(SCU_CLKSTOP_EXTEMMC); 992 993 //ast2600 eMMC controller max clk is 200Mhz 994 /* 995 HPll->1/2-> 996 \ 997 ->SCU300[11]->SCU300[14:12][1/N]->EMMC12C[15:8][1/N]-> eMMC clk 998 / 999 MPLL------> 1000 */ 1001 if(((revision_id & CHIP_REVISION_ID) >> 16)) { 1002 //AST2600A1 : use mpll to be clk source 1003 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL); 1004 for(i = 0; i < 8; i++) { 1005 div = (i + 1) * 2; 1006 if ((rate / div) <= 200000000) 1007 break; 1008 } 1009 1010 clk_sel &= ~SCU_CLK_EMMC_MASK; 1011 clk_sel |= SCU_CLK_EMMC_DIV(i) | SCU_CLK_EMMC_FROM_MPLL_CLK; 1012 writel(clk_sel, &scu->clk_sel1); 1013 1014 } else { 1015 //AST2600A0 : use hpll to be clk source 1016 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 1017 1018 for(i = 0; i < 8; i++) { 1019 div = (i + 1) * 4; 1020 if ((rate / div) <= 200000000) 1021 break; 1022 } 1023 1024 clk_sel &= ~SCU_CLK_EMMC_MASK; 1025 clk_sel |= SCU_CLK_EMMC_DIV(i); 1026 writel(clk_sel, &scu->clk_sel1); 1027 } 1028 setbits_le32(&scu->clk_sel1, enableclk_bit); 1029 1030 return 0; 1031 } 1032 1033 #define SCU_CLKSTOP_FSICLK 30 1034 1035 static ulong ast2600_enable_fsiclk(struct ast2600_scu *scu) 1036 { 1037 u32 reset_bit; 1038 u32 clkstop_bit; 1039 1040 reset_bit = BIT(ASPEED_RESET_FSI % 32); 1041 clkstop_bit = BIT(SCU_CLKSTOP_FSICLK); 1042 1043 /* The FSI clock is shared between masters. If it's already on 1044 * don't touch it, as that will reset the existing master. */ 1045 if (!(readl(&scu->clk_stop_ctrl2) & clkstop_bit)) { 1046 debug("%s: already running, not touching it\n", __func__); 1047 return 0; 1048 } 1049 1050 writel(reset_bit, &scu->sysreset_ctrl2); 1051 udelay(100); 1052 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 1053 mdelay(10); 1054 writel(reset_bit, &scu->sysreset_clr_ctrl2); 1055 1056 return 0; 1057 } 1058 1059 static ulong ast2600_enable_usbahclk(struct ast2600_scu *scu) 1060 { 1061 u32 reset_bit; 1062 u32 clkstop_bit; 1063 1064 reset_bit = BIT(ASPEED_RESET_EHCI_P1); 1065 clkstop_bit = BIT(14); 1066 1067 writel(reset_bit, &scu->sysreset_ctrl1); 1068 udelay(100); 1069 writel(clkstop_bit, &scu->clk_stop_ctrl1); 1070 mdelay(20); 1071 writel(reset_bit, &scu->sysreset_clr_ctrl1); 1072 1073 return 0; 1074 } 1075 1076 static ulong ast2600_enable_usbbhclk(struct ast2600_scu *scu) 1077 { 1078 u32 reset_bit; 1079 u32 clkstop_bit; 1080 1081 reset_bit = BIT(ASPEED_RESET_EHCI_P2); 1082 clkstop_bit = BIT(7); 1083 1084 writel(reset_bit, &scu->sysreset_ctrl1); 1085 udelay(100); 1086 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 1087 mdelay(20); 1088 1089 writel(reset_bit, &scu->sysreset_clr_ctrl1); 1090 1091 return 0; 1092 } 1093 1094 static int ast2600_clk_enable(struct clk *clk) 1095 { 1096 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 1097 1098 switch (clk->id) { 1099 case ASPEED_CLK_GATE_MAC1CLK: 1100 ast2600_configure_mac(priv->scu, 1); 1101 break; 1102 case ASPEED_CLK_GATE_MAC2CLK: 1103 ast2600_configure_mac(priv->scu, 2); 1104 break; 1105 case ASPEED_CLK_GATE_MAC3CLK: 1106 ast2600_configure_mac(priv->scu, 3); 1107 break; 1108 case ASPEED_CLK_GATE_MAC4CLK: 1109 ast2600_configure_mac(priv->scu, 4); 1110 break; 1111 case ASPEED_CLK_GATE_SDCLK: 1112 ast2600_enable_sdclk(priv->scu); 1113 break; 1114 case ASPEED_CLK_GATE_SDEXTCLK: 1115 ast2600_enable_extsdclk(priv->scu); 1116 break; 1117 case ASPEED_CLK_GATE_EMMCCLK: 1118 ast2600_enable_emmcclk(priv->scu); 1119 break; 1120 case ASPEED_CLK_GATE_EMMCEXTCLK: 1121 ast2600_enable_extemmcclk(priv->scu); 1122 break; 1123 case ASPEED_CLK_GATE_FSICLK: 1124 ast2600_enable_fsiclk(priv->scu); 1125 break; 1126 case ASPEED_CLK_GATE_USBPORT1CLK: 1127 ast2600_enable_usbahclk(priv->scu); 1128 break; 1129 case ASPEED_CLK_GATE_USBPORT2CLK: 1130 ast2600_enable_usbbhclk(priv->scu); 1131 break; 1132 default: 1133 pr_debug("can't enable clk \n"); 1134 return -ENOENT; 1135 break; 1136 } 1137 1138 return 0; 1139 } 1140 1141 struct clk_ops ast2600_clk_ops = { 1142 .get_rate = ast2600_clk_get_rate, 1143 .set_rate = ast2600_clk_set_rate, 1144 .enable = ast2600_clk_enable, 1145 }; 1146 1147 static int ast2600_clk_probe(struct udevice *dev) 1148 { 1149 struct ast2600_clk_priv *priv = dev_get_priv(dev); 1150 u32 uart_clk_source; 1151 1152 priv->scu = devfdt_get_addr_ptr(dev); 1153 if (IS_ERR(priv->scu)) 1154 return PTR_ERR(priv->scu); 1155 1156 uart_clk_source = dev_read_u32_default(dev, "uart-clk-source", 1157 0x0); 1158 1159 if(uart_clk_source) { 1160 if(uart_clk_source & GENMASK(5, 0)) 1161 setbits_le32(&priv->scu->clk_sel4, uart_clk_source & GENMASK(5, 0)); 1162 if(uart_clk_source & GENMASK(12, 6)) 1163 setbits_le32(&priv->scu->clk_sel5, uart_clk_source & GENMASK(12, 6)); 1164 } 1165 1166 ast2600_init_rgmii_clk(priv->scu, &rgmii_clk_defconfig); 1167 ast2600_init_rmii_clk(priv->scu, &rmii_clk_defconfig); 1168 ast2600_configure_mac12_clk(priv->scu); 1169 ast2600_configure_mac34_clk(priv->scu); 1170 ast2600_configure_rsa_ecc_clk(priv->scu); 1171 1172 return 0; 1173 } 1174 1175 static int ast2600_clk_bind(struct udevice *dev) 1176 { 1177 int ret; 1178 1179 /* The reset driver does not have a device node, so bind it here */ 1180 ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev); 1181 if (ret) 1182 debug("Warning: No reset driver: ret=%d\n", ret); 1183 1184 return 0; 1185 } 1186 1187 #if CONFIG_IS_ENABLED(CMD_CLK) 1188 struct aspeed_clks { 1189 ulong id; 1190 const char *name; 1191 }; 1192 1193 static struct aspeed_clks aspeed_clk_names[] = { 1194 { ASPEED_CLK_HPLL, "hpll" }, 1195 { ASPEED_CLK_MPLL, "mpll" }, 1196 { ASPEED_CLK_APLL, "apll" }, 1197 { ASPEED_CLK_EPLL, "epll" }, 1198 { ASPEED_CLK_DPLL, "dpll" }, 1199 { ASPEED_CLK_AHB, "hclk" }, 1200 { ASPEED_CLK_APB1, "pclk1" }, 1201 { ASPEED_CLK_APB2, "pclk2" }, 1202 { ASPEED_CLK_BCLK, "bclk" }, 1203 { ASPEED_CLK_UARTX, "uxclk" }, 1204 { ASPEED_CLK_HUARTX, "huxclk" }, 1205 }; 1206 1207 int soc_clk_dump(void) 1208 { 1209 struct udevice *dev; 1210 struct clk clk; 1211 unsigned long rate; 1212 int i, ret; 1213 1214 ret = uclass_get_device_by_driver(UCLASS_CLK, 1215 DM_GET_DRIVER(aspeed_scu), &dev); 1216 if (ret) 1217 return ret; 1218 1219 printf("Clk\t\tHz\n"); 1220 1221 for (i = 0; i < ARRAY_SIZE(aspeed_clk_names); i++) { 1222 clk.id = aspeed_clk_names[i].id; 1223 ret = clk_request(dev, &clk); 1224 if (ret < 0) { 1225 debug("%s clk_request() failed: %d\n", __func__, ret); 1226 continue; 1227 } 1228 1229 ret = clk_get_rate(&clk); 1230 rate = ret; 1231 1232 clk_free(&clk); 1233 1234 if (ret == -ENOTSUPP) { 1235 printf("clk ID %lu not supported yet\n", 1236 aspeed_clk_names[i].id); 1237 continue; 1238 } 1239 if (ret < 0) { 1240 printf("%s %lu: get_rate err: %d\n", 1241 __func__, aspeed_clk_names[i].id, ret); 1242 continue; 1243 } 1244 1245 printf("%s(%3lu):\t%lu\n", 1246 aspeed_clk_names[i].name, aspeed_clk_names[i].id, rate); 1247 } 1248 1249 return 0; 1250 } 1251 #endif 1252 1253 static const struct udevice_id ast2600_clk_ids[] = { 1254 { .compatible = "aspeed,ast2600-scu", }, 1255 { } 1256 }; 1257 1258 U_BOOT_DRIVER(aspeed_scu) = { 1259 .name = "aspeed_scu", 1260 .id = UCLASS_CLK, 1261 .of_match = ast2600_clk_ids, 1262 .priv_auto_alloc_size = sizeof(struct ast2600_clk_priv), 1263 .ops = &ast2600_clk_ops, 1264 .bind = ast2600_clk_bind, 1265 .probe = ast2600_clk_probe, 1266 }; 1267