1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 */ 5 6 #include <common.h> 7 #include <clk-uclass.h> 8 #include <dm.h> 9 #include <asm/io.h> 10 #include <dm/lists.h> 11 #include <asm/arch/scu_ast2600.h> 12 #include <dt-bindings/clock/ast2600-clock.h> 13 #include <dt-bindings/reset/ast2600-reset.h> 14 15 /* 16 * MAC Clock Delay settings 17 */ 18 #define RGMII_TXCLK_ODLY 8 19 #define RMII_RXCLK_IDLY 2 20 21 #define MAC_DEF_DELAY_1G 0x0041b75d 22 #define MAC_DEF_DELAY_100M 0x00417410 23 #define MAC_DEF_DELAY_10M 0x00417410 24 25 #define MAC34_DEF_DELAY_1G 0x0010438a 26 #define MAC34_DEF_DELAY_100M 0x00104208 27 #define MAC34_DEF_DELAY_10M 0x00104208 28 29 /* 30 * TGMII Clock Duty constants, taken from Aspeed SDK 31 */ 32 #define RGMII2_TXCK_DUTY 0x66 33 #define RGMII1_TXCK_DUTY 0x64 34 #define D2PLL_DEFAULT_RATE (250 * 1000 * 1000) 35 #define CHIP_REVISION_ID GENMASK(23, 16) 36 37 DECLARE_GLOBAL_DATA_PTR; 38 39 /* 40 * Clock divider/multiplier configuration struct. 41 * For H-PLL and M-PLL the formula is 42 * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1) 43 * M - Numerator 44 * N - Denumerator 45 * P - Post Divider 46 * They have the same layout in their control register. 47 * 48 * D-PLL and D2-PLL have extra divider (OD + 1), which is not 49 * yet needed and ignored by clock configurations. 50 */ 51 union ast2600_pll_reg { 52 unsigned int w; 53 struct { 54 unsigned int m : 13; /* bit[12:0] */ 55 unsigned int n : 6; /* bit[18:13] */ 56 unsigned int p : 4; /* bit[22:19] */ 57 unsigned int off : 1; /* bit[23] */ 58 unsigned int bypass : 1; /* bit[24] */ 59 unsigned int reset : 1; /* bit[25] */ 60 unsigned int reserved : 6; /* bit[31:26] */ 61 } b; 62 }; 63 64 struct ast2600_pll_cfg { 65 union ast2600_pll_reg reg; 66 unsigned int ext_reg; 67 }; 68 69 struct ast2600_pll_desc { 70 u32 in; 71 u32 out; 72 struct ast2600_pll_cfg cfg; 73 }; 74 75 static const struct ast2600_pll_desc ast2600_pll_lookup[] = { 76 { 77 .in = AST2600_CLK_IN, 78 .out = 400000000, 79 .cfg.reg.b.m = 95, 80 .cfg.reg.b.n = 2, 81 .cfg.reg.b.p = 1, 82 .cfg.ext_reg = 0x31, 83 }, { 84 .in = AST2600_CLK_IN, 85 .out = 200000000, 86 .cfg.reg.b.m = 127, 87 .cfg.reg.b.n = 0, 88 .cfg.reg.b.p = 15, 89 .cfg.ext_reg = 0x3f, 90 }, { 91 .in = AST2600_CLK_IN, 92 .out = 334000000, 93 .cfg.reg.b.m = 667, 94 .cfg.reg.b.n = 4, 95 .cfg.reg.b.p = 9, 96 .cfg.ext_reg = 0x14d, 97 }, { 98 .in = AST2600_CLK_IN, 99 .out = 1000000000, 100 .cfg.reg.b.m = 119, 101 .cfg.reg.b.n = 2, 102 .cfg.reg.b.p = 0, 103 .cfg.ext_reg = 0x3d, 104 }, { 105 .in = AST2600_CLK_IN, 106 .out = 50000000, 107 .cfg.reg.b.m = 95, 108 .cfg.reg.b.n = 2, 109 .cfg.reg.b.p = 15, 110 .cfg.ext_reg = 0x31, 111 }, 112 }; 113 114 extern u32 ast2600_get_pll_rate(struct ast2600_scu *scu, int pll_idx) 115 { 116 u32 clkin = AST2600_CLK_IN; 117 u32 pll_reg = 0; 118 unsigned int mult, div = 1; 119 120 switch (pll_idx) { 121 case ASPEED_CLK_HPLL: 122 pll_reg = readl(&scu->h_pll_param); 123 break; 124 case ASPEED_CLK_MPLL: 125 pll_reg = readl(&scu->m_pll_param); 126 break; 127 case ASPEED_CLK_DPLL: 128 pll_reg = readl(&scu->d_pll_param); 129 break; 130 case ASPEED_CLK_EPLL: 131 pll_reg = readl(&scu->e_pll_param); 132 break; 133 } 134 if (pll_reg & BIT(24)) { 135 /* Pass through mode */ 136 mult = 1; 137 div = 1; 138 } else { 139 union ast2600_pll_reg reg; 140 /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) 141 * HPLL Numerator (M) = fix 0x5F when SCU500[10]=1 142 * Fixed 0xBF when SCU500[10]=0 and SCU500[8]=1 143 * SCU200[12:0] (default 0x8F) when SCU510[10]=0 and SCU510[8]=0 144 * HPLL Denumerator (N) = SCU200[18:13] (default 0x2) 145 * HPLL Divider (P) = SCU200[22:19] (default 0x0) 146 * HPLL Bandwidth Adj (NB) = fix 0x2F when SCU500[10]=1 147 * Fixed 0x5F when SCU500[10]=0 and SCU500[8]=1 148 * SCU204[11:0] (default 0x31) when SCU500[10]=0 and SCU500[8]=0 149 */ 150 reg.w = pll_reg; 151 if (pll_idx == ASPEED_CLK_HPLL) { 152 u32 hwstrap1 = readl(&scu->hwstrap1.hwstrap); 153 154 if (hwstrap1 & BIT(10)) { 155 reg.b.m = 0x5F; 156 } else { 157 if (hwstrap1 & BIT(8)) 158 reg.b.m = 0xBF; 159 /* Otherwise keep default 0x8F */ 160 } 161 } 162 mult = (reg.b.m + 1) / (reg.b.n + 1); 163 div = (reg.b.p + 1); 164 } 165 166 return ((clkin * mult) / div); 167 } 168 169 extern u32 ast2600_get_apll_rate(struct ast2600_scu *scu) 170 { 171 u32 hw_rev = readl(&scu->chip_id1); 172 u32 clkin = AST2600_CLK_IN; 173 u32 apll_reg = readl(&scu->a_pll_param); 174 unsigned int mult, div = 1; 175 176 if (((hw_rev & CHIP_REVISION_ID) >> 16) >= 3) { 177 //after A2 version 178 if (apll_reg & BIT(24)) { 179 /* Pass through mode */ 180 mult = 1; 181 div = 1; 182 } else { 183 /* F = 25Mhz * [(m + 1) / (n + 1)] / (p + 1) */ 184 u32 m = apll_reg & 0x1fff; 185 u32 n = (apll_reg >> 13) & 0x3f; 186 u32 p = (apll_reg >> 19) & 0xf; 187 188 mult = (m + 1); 189 div = (n + 1) * (p + 1); 190 } 191 192 } else { 193 if (apll_reg & BIT(20)) { 194 /* Pass through mode */ 195 mult = 1; 196 div = 1; 197 } else { 198 /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */ 199 u32 m = (apll_reg >> 5) & 0x3f; 200 u32 od = (apll_reg >> 4) & 0x1; 201 u32 n = apll_reg & 0xf; 202 203 mult = (2 - od) * (m + 2); 204 div = n + 1; 205 } 206 } 207 208 return ((clkin * mult) / div); 209 } 210 211 static u32 ast2600_a0_axi_ahb_div_table[] = { 212 2, 213 2, 214 3, 215 4, 216 }; 217 218 static u32 ast2600_a1_axi_ahb_div0_table[] = { 219 3, 220 2, 221 3, 222 4, 223 }; 224 225 static u32 ast2600_a1_axi_ahb_div1_table[] = { 226 3, 227 4, 228 6, 229 8, 230 }; 231 232 static u32 ast2600_a1_axi_ahb_default_table[] = { 233 3, 4, 3, 4, 2, 2, 2, 2, 234 }; 235 236 static u32 ast2600_get_hclk(struct ast2600_scu *scu) 237 { 238 u32 hw_rev = readl(&scu->chip_id1); 239 u32 hwstrap1 = readl(&scu->hwstrap1.hwstrap); 240 u32 axi_div = 1; 241 u32 ahb_div = 0; 242 u32 rate = 0; 243 244 if ((hw_rev & CHIP_REVISION_ID) >> 16) { 245 //After A0 246 if (hwstrap1 & BIT(16)) { 247 ast2600_a1_axi_ahb_div1_table[0] = 248 ast2600_a1_axi_ahb_default_table[(hwstrap1 >> 8) & 249 0x3]; 250 axi_div = 1; 251 ahb_div = 252 ast2600_a1_axi_ahb_div1_table[(hwstrap1 >> 11) & 253 0x3]; 254 } else { 255 ast2600_a1_axi_ahb_div0_table[0] = 256 ast2600_a1_axi_ahb_default_table[(hwstrap1 >> 8) & 257 0x3]; 258 axi_div = 2; 259 ahb_div = 260 ast2600_a1_axi_ahb_div0_table[(hwstrap1 >> 11) & 261 0x3]; 262 } 263 } else { 264 //A0 : fix axi = hpll / 2 265 axi_div = 2; 266 ahb_div = ast2600_a0_axi_ahb_div_table[(hwstrap1 >> 11) & 0x3]; 267 } 268 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 269 270 return (rate / axi_div / ahb_div); 271 } 272 273 static u32 ast2600_get_bclk_rate(struct ast2600_scu *scu) 274 { 275 u32 rate; 276 u32 bclk_sel = (readl(&scu->clk_sel1) >> 20) & 0x7; 277 278 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 279 280 return (rate / ((bclk_sel + 1) * 4)); 281 } 282 283 static u32 ast2600_hpll_pclk1_div_table[] = { 284 4, 8, 12, 16, 20, 24, 28, 32, 285 }; 286 287 static u32 ast2600_hpll_pclk2_div_table[] = { 288 2, 4, 6, 8, 10, 12, 14, 16, 289 }; 290 291 static u32 ast2600_get_pclk1(struct ast2600_scu *scu) 292 { 293 u32 clk_sel1 = readl(&scu->clk_sel1); 294 u32 apb_div = ast2600_hpll_pclk1_div_table[((clk_sel1 >> 23) & 0x7)]; 295 u32 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 296 297 return (rate / apb_div); 298 } 299 300 static u32 ast2600_get_pclk2(struct ast2600_scu *scu) 301 { 302 u32 clk_sel4 = readl(&scu->clk_sel4); 303 u32 apb_div = ast2600_hpll_pclk2_div_table[((clk_sel4 >> 9) & 0x7)]; 304 u32 rate = ast2600_get_hclk(scu); 305 306 return (rate / apb_div); 307 } 308 309 static u32 ast2600_get_uxclk_in_rate(struct ast2600_scu *scu) 310 { 311 u32 clk_in = 0; 312 u32 uxclk_sel = readl(&scu->clk_sel5); 313 314 uxclk_sel &= 0x3; 315 switch (uxclk_sel) { 316 case 0: 317 clk_in = ast2600_get_apll_rate(scu) / 4; 318 break; 319 case 1: 320 clk_in = ast2600_get_apll_rate(scu) / 2; 321 break; 322 case 2: 323 clk_in = ast2600_get_apll_rate(scu); 324 break; 325 case 3: 326 clk_in = ast2600_get_hclk(scu); 327 break; 328 } 329 330 return clk_in; 331 } 332 333 static u32 ast2600_get_huxclk_in_rate(struct ast2600_scu *scu) 334 { 335 u32 clk_in = 0; 336 u32 huclk_sel = readl(&scu->clk_sel5); 337 338 huclk_sel = ((huclk_sel >> 3) & 0x3); 339 switch (huclk_sel) { 340 case 0: 341 clk_in = ast2600_get_apll_rate(scu) / 4; 342 break; 343 case 1: 344 clk_in = ast2600_get_apll_rate(scu) / 2; 345 break; 346 case 2: 347 clk_in = ast2600_get_apll_rate(scu); 348 break; 349 case 3: 350 clk_in = ast2600_get_hclk(scu); 351 break; 352 } 353 354 return clk_in; 355 } 356 357 static u32 ast2600_get_uart_uxclk_rate(struct ast2600_scu *scu) 358 { 359 u32 clk_in = ast2600_get_uxclk_in_rate(scu); 360 u32 div_reg = readl(&scu->uart_24m_ref_uxclk); 361 unsigned int mult, div; 362 363 u32 n = (div_reg >> 8) & 0x3ff; 364 u32 r = div_reg & 0xff; 365 366 mult = r; 367 div = (n * 2); 368 return (clk_in * mult) / div; 369 } 370 371 static u32 ast2600_get_uart_huxclk_rate(struct ast2600_scu *scu) 372 { 373 u32 clk_in = ast2600_get_huxclk_in_rate(scu); 374 u32 div_reg = readl(&scu->uart_24m_ref_huxclk); 375 376 unsigned int mult, div; 377 378 u32 n = (div_reg >> 8) & 0x3ff; 379 u32 r = div_reg & 0xff; 380 381 mult = r; 382 div = (n * 2); 383 return (clk_in * mult) / div; 384 } 385 386 static u32 ast2600_get_sdio_clk_rate(struct ast2600_scu *scu) 387 { 388 u32 clkin = 0; 389 u32 clk_sel = readl(&scu->clk_sel4); 390 u32 div = (clk_sel >> 28) & 0x7; 391 392 if (clk_sel & BIT(8)) 393 clkin = ast2600_get_apll_rate(scu); 394 else 395 clkin = ast2600_get_hclk(scu); 396 397 div = (div + 1) << 1; 398 399 return (clkin / div); 400 } 401 402 static u32 ast2600_get_emmc_clk_rate(struct ast2600_scu *scu) 403 { 404 u32 clkin = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 405 u32 clk_sel = readl(&scu->clk_sel1); 406 u32 div = (clk_sel >> 12) & 0x7; 407 408 div = (div + 1) << 2; 409 410 return (clkin / div); 411 } 412 413 static u32 ast2600_get_uart_clk_rate(struct ast2600_scu *scu, int uart_idx) 414 { 415 u32 uart_sel = readl(&scu->clk_sel4); 416 u32 uart_sel5 = readl(&scu->clk_sel5); 417 ulong uart_clk = 0; 418 419 switch (uart_idx) { 420 case 1: 421 case 2: 422 case 3: 423 case 4: 424 case 6: 425 if (uart_sel & BIT(uart_idx - 1)) 426 uart_clk = ast2600_get_uart_huxclk_rate(scu); 427 else 428 uart_clk = ast2600_get_uart_uxclk_rate(scu); 429 break; 430 case 5: //24mhz is come form usb phy 48Mhz 431 { 432 u8 uart5_clk_sel = 0; 433 //high bit 434 if (readl(&scu->misc_ctrl1) & BIT(12)) 435 uart5_clk_sel = 0x2; 436 else 437 uart5_clk_sel = 0x0; 438 439 if (readl(&scu->clk_sel2) & BIT(14)) 440 uart5_clk_sel |= 0x1; 441 442 switch (uart5_clk_sel) { 443 case 0: 444 uart_clk = 24000000; 445 break; 446 case 1: 447 uart_clk = 192000000; 448 break; 449 case 2: 450 uart_clk = 24000000 / 13; 451 break; 452 case 3: 453 uart_clk = 192000000 / 13; 454 break; 455 } 456 } break; 457 case 7: 458 case 8: 459 case 9: 460 case 10: 461 case 11: 462 case 12: 463 case 13: 464 if (uart_sel5 & BIT(uart_idx - 1)) 465 uart_clk = ast2600_get_uart_huxclk_rate(scu); 466 else 467 uart_clk = ast2600_get_uart_uxclk_rate(scu); 468 break; 469 } 470 471 return uart_clk; 472 } 473 474 static ulong ast2600_clk_get_rate(struct clk *clk) 475 { 476 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 477 ulong rate = 0; 478 479 switch (clk->id) { 480 case ASPEED_CLK_HPLL: 481 case ASPEED_CLK_EPLL: 482 case ASPEED_CLK_DPLL: 483 case ASPEED_CLK_MPLL: 484 rate = ast2600_get_pll_rate(priv->scu, clk->id); 485 break; 486 case ASPEED_CLK_AHB: 487 rate = ast2600_get_hclk(priv->scu); 488 break; 489 case ASPEED_CLK_APB1: 490 rate = ast2600_get_pclk1(priv->scu); 491 break; 492 case ASPEED_CLK_APB2: 493 rate = ast2600_get_pclk2(priv->scu); 494 break; 495 case ASPEED_CLK_APLL: 496 rate = ast2600_get_apll_rate(priv->scu); 497 break; 498 case ASPEED_CLK_GATE_UART1CLK: 499 rate = ast2600_get_uart_clk_rate(priv->scu, 1); 500 break; 501 case ASPEED_CLK_GATE_UART2CLK: 502 rate = ast2600_get_uart_clk_rate(priv->scu, 2); 503 break; 504 case ASPEED_CLK_GATE_UART3CLK: 505 rate = ast2600_get_uart_clk_rate(priv->scu, 3); 506 break; 507 case ASPEED_CLK_GATE_UART4CLK: 508 rate = ast2600_get_uart_clk_rate(priv->scu, 4); 509 break; 510 case ASPEED_CLK_GATE_UART5CLK: 511 rate = ast2600_get_uart_clk_rate(priv->scu, 5); 512 break; 513 case ASPEED_CLK_BCLK: 514 rate = ast2600_get_bclk_rate(priv->scu); 515 break; 516 case ASPEED_CLK_SDIO: 517 rate = ast2600_get_sdio_clk_rate(priv->scu); 518 break; 519 case ASPEED_CLK_EMMC: 520 rate = ast2600_get_emmc_clk_rate(priv->scu); 521 break; 522 case ASPEED_CLK_UARTX: 523 rate = ast2600_get_uart_uxclk_rate(priv->scu); 524 break; 525 case ASPEED_CLK_HUARTX: 526 rate = ast2600_get_uart_huxclk_rate(priv->scu); 527 break; 528 default: 529 pr_debug("can't get clk rate\n"); 530 return -ENOENT; 531 } 532 533 return rate; 534 } 535 536 /** 537 * @brief lookup PLL divider config by input/output rate 538 * @param[in] *pll - PLL descriptor 539 * @return true - if PLL divider config is found, false - else 540 * The function caller shall fill "pll->in" and "pll->out", 541 * then this function will search the lookup table 542 * to find a valid PLL divider configuration. 543 */ 544 static bool ast2600_search_clock_config(struct ast2600_pll_desc *pll) 545 { 546 u32 i; 547 bool is_found = false; 548 549 for (i = 0; i < ARRAY_SIZE(ast2600_pll_lookup); i++) { 550 const struct ast2600_pll_desc *def_cfg = &ast2600_pll_lookup[i]; 551 552 if (def_cfg->in == pll->in && def_cfg->out == pll->out) { 553 is_found = true; 554 pll->cfg.reg.w = def_cfg->cfg.reg.w; 555 pll->cfg.ext_reg = def_cfg->cfg.ext_reg; 556 break; 557 } 558 } 559 return is_found; 560 } 561 562 static u32 ast2600_configure_pll(struct ast2600_scu *scu, 563 struct ast2600_pll_cfg *p_cfg, int pll_idx) 564 { 565 u32 addr, addr_ext; 566 u32 reg; 567 568 switch (pll_idx) { 569 case ASPEED_CLK_HPLL: 570 addr = (u32)(&scu->h_pll_param); 571 addr_ext = (u32)(&scu->h_pll_ext_param); 572 break; 573 case ASPEED_CLK_MPLL: 574 addr = (u32)(&scu->m_pll_param); 575 addr_ext = (u32)(&scu->m_pll_ext_param); 576 break; 577 case ASPEED_CLK_DPLL: 578 addr = (u32)(&scu->d_pll_param); 579 addr_ext = (u32)(&scu->d_pll_ext_param); 580 break; 581 case ASPEED_CLK_EPLL: 582 addr = (u32)(&scu->e_pll_param); 583 addr_ext = (u32)(&scu->e_pll_ext_param); 584 break; 585 default: 586 debug("unknown PLL index\n"); 587 return 1; 588 } 589 590 p_cfg->reg.b.bypass = 0; 591 p_cfg->reg.b.off = 1; 592 p_cfg->reg.b.reset = 1; 593 594 reg = readl(addr); 595 reg &= ~GENMASK(25, 0); 596 reg |= p_cfg->reg.w; 597 writel(reg, addr); 598 599 /* write extend parameter */ 600 writel(p_cfg->ext_reg, addr_ext); 601 udelay(100); 602 p_cfg->reg.b.off = 0; 603 p_cfg->reg.b.reset = 0; 604 reg &= ~GENMASK(25, 0); 605 reg |= p_cfg->reg.w; 606 writel(reg, addr); 607 while (!(readl(addr_ext) & BIT(31))) 608 ; 609 610 return 0; 611 } 612 613 static u32 ast2600_configure_ddr(struct ast2600_scu *scu, ulong rate) 614 { 615 struct ast2600_pll_desc mpll; 616 617 mpll.in = AST2600_CLK_IN; 618 mpll.out = rate; 619 if (ast2600_search_clock_config(&mpll) == false) { 620 printf("error!! unable to find valid DDR clock setting\n"); 621 return 0; 622 } 623 ast2600_configure_pll(scu, &mpll.cfg, ASPEED_CLK_MPLL); 624 625 return ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL); 626 } 627 628 static ulong ast2600_clk_set_rate(struct clk *clk, ulong rate) 629 { 630 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 631 ulong new_rate; 632 633 switch (clk->id) { 634 case ASPEED_CLK_MPLL: 635 new_rate = ast2600_configure_ddr(priv->scu, rate); 636 break; 637 default: 638 return -ENOENT; 639 } 640 641 return new_rate; 642 } 643 644 #define SCU_CLKSTOP_MAC1 (20) 645 #define SCU_CLKSTOP_MAC2 (21) 646 #define SCU_CLKSTOP_MAC3 (20) 647 #define SCU_CLKSTOP_MAC4 (21) 648 649 static u32 ast2600_configure_mac12_clk(struct ast2600_scu *scu) 650 { 651 /* scu340[25:0]: 1G default delay */ 652 clrsetbits_le32(&scu->mac12_clk_delay, GENMASK(25, 0), 653 MAC_DEF_DELAY_1G); 654 655 /* set 100M/10M default delay */ 656 writel(MAC_DEF_DELAY_100M, &scu->mac12_clk_delay_100M); 657 writel(MAC_DEF_DELAY_10M, &scu->mac12_clk_delay_10M); 658 659 /* MAC AHB = HPLL / 6 */ 660 clrsetbits_le32(&scu->clk_sel1, GENMASK(18, 16), (0x2 << 16)); 661 662 return 0; 663 } 664 665 static u32 ast2600_configure_mac34_clk(struct ast2600_scu *scu) 666 { 667 /* 668 * scu350[31] RGMII 125M source: 0 = from IO pin 669 * scu350[25:0] MAC 1G delay 670 */ 671 clrsetbits_le32(&scu->mac34_clk_delay, (BIT(31) | GENMASK(25, 0)), 672 MAC34_DEF_DELAY_1G); 673 writel(MAC34_DEF_DELAY_100M, &scu->mac34_clk_delay_100M); 674 writel(MAC34_DEF_DELAY_10M, &scu->mac34_clk_delay_10M); 675 676 /* 677 * clock source seletion and divider 678 * scu310[26:24] : MAC AHB bus clock = HCLK / 2 679 * scu310[18:16] : RMII 50M = HCLK_200M / 4 680 */ 681 clrsetbits_le32(&scu->clk_sel4, (GENMASK(26, 24) | GENMASK(18, 16)), 682 ((0x0 << 24) | (0x3 << 16))); 683 684 /* 685 * set driving strength 686 * scu458[3:2] : MAC4 driving strength 687 * scu458[1:0] : MAC3 driving strength 688 */ 689 clrsetbits_le32(&scu->pinmux_ctrl16, GENMASK(3, 0), 690 (0x3 << 2) | (0x3 << 0)); 691 692 return 0; 693 } 694 695 /** 696 * ast2600 RGMII clock source tree 697 * 125M from external PAD -------->|\ 698 * HPLL -->|\ | |---->RGMII 125M for MAC#1 & MAC#2 699 * | |---->| divider |---->|/ + 700 * EPLL -->|/ | 701 * | 702 * +---------<-----------|RGMIICK PAD output enable|<-------------+ 703 * | 704 * +--------------------------->|\ 705 * | |----> RGMII 125M for MAC#3 & MAC#4 706 * HCLK 200M ---->|divider|---->|/ 707 * To simplify the control flow: 708 * 1. RGMII 1/2 always use EPLL as the internal clock source 709 * 2. RGMII 3/4 always use RGMIICK pad as the RGMII 125M source 710 * 125M from external PAD -------->|\ 711 * | |---->RGMII 125M for MAC#1 & MAC#2 712 * EPLL---->| divider |--->|/ + 713 * | 714 * +<--------------------|RGMIICK PAD output enable|<-------------+ 715 * | 716 * +--------------------------->RGMII 125M for MAC#3 & MAC#4 717 */ 718 #define RGMIICK_SRC_PAD 0 719 #define RGMIICK_SRC_EPLL 1 /* recommended */ 720 #define RGMIICK_SRC_HPLL 2 721 722 #define RGMIICK_DIV2 1 723 #define RGMIICK_DIV3 2 724 #define RGMIICK_DIV4 3 725 #define RGMIICK_DIV5 4 726 #define RGMIICK_DIV6 5 727 #define RGMIICK_DIV7 6 728 #define RGMIICK_DIV8 7 /* recommended */ 729 730 #define RMIICK_DIV4 0 731 #define RMIICK_DIV8 1 732 #define RMIICK_DIV12 2 733 #define RMIICK_DIV16 3 734 #define RMIICK_DIV20 4 /* recommended */ 735 #define RMIICK_DIV24 5 736 #define RMIICK_DIV28 6 737 #define RMIICK_DIV32 7 738 739 struct ast2600_mac_clk_div { 740 u32 src; /* 0=external PAD, 1=internal PLL */ 741 u32 fin; /* divider input speed */ 742 u32 n; /* 0=div2, 1=div2, 2=div3, 3=div4,...,7=div8 */ 743 u32 fout; /* fout = fin / n */ 744 }; 745 746 struct ast2600_mac_clk_div rgmii_clk_defconfig = { 747 .src = ASPEED_CLK_EPLL, 748 .fin = 1000000000, 749 .n = RGMIICK_DIV8, 750 .fout = 125000000, 751 }; 752 753 struct ast2600_mac_clk_div rmii_clk_defconfig = { 754 .src = ASPEED_CLK_EPLL, 755 .fin = 1000000000, 756 .n = RMIICK_DIV20, 757 .fout = 50000000, 758 }; 759 760 static void ast2600_init_mac_pll(struct ast2600_scu *p_scu, 761 struct ast2600_mac_clk_div *p_cfg) 762 { 763 struct ast2600_pll_desc pll; 764 765 pll.in = AST2600_CLK_IN; 766 pll.out = p_cfg->fin; 767 if (ast2600_search_clock_config(&pll) == false) { 768 pr_err("unable to find valid ETHNET MAC clock setting\n"); 769 debug("%s: pll cfg = 0x%08x 0x%08x\n", __func__, pll.cfg.reg.w, 770 pll.cfg.ext_reg); 771 debug("%s: pll cfg = %02x %02x %02x\n", __func__, 772 pll.cfg.reg.b.m, pll.cfg.reg.b.n, pll.cfg.reg.b.p); 773 return; 774 } 775 ast2600_configure_pll(p_scu, &pll.cfg, p_cfg->src); 776 } 777 778 static void ast2600_init_rgmii_clk(struct ast2600_scu *p_scu, 779 struct ast2600_mac_clk_div *p_cfg) 780 { 781 u32 reg_304 = readl(&p_scu->clk_sel2); 782 u32 reg_340 = readl(&p_scu->mac12_clk_delay); 783 u32 reg_350 = readl(&p_scu->mac34_clk_delay); 784 785 reg_340 &= ~GENMASK(31, 29); 786 /* scu340[28]: RGMIICK PAD output enable (to MAC 3/4) */ 787 reg_340 |= BIT(28); 788 if (p_cfg->src == ASPEED_CLK_EPLL || p_cfg->src == ASPEED_CLK_HPLL) { 789 /* 790 * re-init PLL if the current PLL output frequency doesn't match 791 * the divider setting 792 */ 793 if (p_cfg->fin != ast2600_get_pll_rate(p_scu, p_cfg->src)) 794 ast2600_init_mac_pll(p_scu, p_cfg); 795 /* scu340[31]: select RGMII 125M from internal source */ 796 reg_340 |= BIT(31); 797 } 798 799 reg_304 &= ~GENMASK(23, 20); 800 801 /* set clock divider */ 802 reg_304 |= (p_cfg->n & 0x7) << 20; 803 804 /* select internal clock source */ 805 if (p_cfg->src == ASPEED_CLK_HPLL) 806 reg_304 |= BIT(23); 807 808 /* RGMII 3/4 clock source select */ 809 reg_350 &= ~BIT(31); 810 811 writel(reg_304, &p_scu->clk_sel2); 812 writel(reg_340, &p_scu->mac12_clk_delay); 813 writel(reg_350, &p_scu->mac34_clk_delay); 814 } 815 816 /** 817 * ast2600 RMII/NCSI clock source tree 818 * HPLL -->|\ 819 * | |---->| divider |----> RMII 50M for MAC#1 & MAC#2 820 * EPLL -->|/ 821 * HCLK(SCLICLK)---->| divider |----> RMII 50M for MAC#3 & MAC#4 822 */ 823 static void ast2600_init_rmii_clk(struct ast2600_scu *p_scu, 824 struct ast2600_mac_clk_div *p_cfg) 825 { 826 u32 reg_304; 827 u32 reg_310; 828 829 if (p_cfg->src == ASPEED_CLK_EPLL || p_cfg->src == ASPEED_CLK_HPLL) { 830 /* 831 * re-init PLL if the current PLL output frequency doesn't match 832 * the divider setting 833 */ 834 if (p_cfg->fin != ast2600_get_pll_rate(p_scu, p_cfg->src)) 835 ast2600_init_mac_pll(p_scu, p_cfg); 836 } 837 838 reg_304 = readl(&p_scu->clk_sel2); 839 reg_310 = readl(&p_scu->clk_sel4); 840 841 reg_304 &= ~GENMASK(19, 16); 842 843 /* set RMII 1/2 clock divider */ 844 reg_304 |= (p_cfg->n & 0x7) << 16; 845 846 /* RMII clock source selection */ 847 if (p_cfg->src == ASPEED_CLK_HPLL) 848 reg_304 |= BIT(19); 849 850 /* set RMII 3/4 clock divider */ 851 reg_310 &= ~GENMASK(18, 16); 852 reg_310 |= (0x3 << 16); 853 854 writel(reg_304, &p_scu->clk_sel2); 855 writel(reg_310, &p_scu->clk_sel4); 856 } 857 858 static u32 ast2600_configure_mac(struct ast2600_scu *scu, int index) 859 { 860 u32 reset_bit; 861 u32 clkstop_bit; 862 863 switch (index) { 864 case 1: 865 reset_bit = BIT(ASPEED_RESET_MAC1); 866 clkstop_bit = BIT(SCU_CLKSTOP_MAC1); 867 writel(reset_bit, &scu->sysreset_ctrl1); 868 udelay(100); 869 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 870 mdelay(10); 871 writel(reset_bit, &scu->sysreset_clr_ctrl1); 872 break; 873 case 2: 874 reset_bit = BIT(ASPEED_RESET_MAC2); 875 clkstop_bit = BIT(SCU_CLKSTOP_MAC2); 876 writel(reset_bit, &scu->sysreset_ctrl1); 877 udelay(100); 878 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 879 mdelay(10); 880 writel(reset_bit, &scu->sysreset_clr_ctrl1); 881 break; 882 case 3: 883 reset_bit = BIT(ASPEED_RESET_MAC3 - 32); 884 clkstop_bit = BIT(SCU_CLKSTOP_MAC3); 885 writel(reset_bit, &scu->sysreset_ctrl2); 886 udelay(100); 887 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 888 mdelay(10); 889 writel(reset_bit, &scu->sysreset_clr_ctrl2); 890 break; 891 case 4: 892 reset_bit = BIT(ASPEED_RESET_MAC4 - 32); 893 clkstop_bit = BIT(SCU_CLKSTOP_MAC4); 894 writel(reset_bit, &scu->sysreset_ctrl2); 895 udelay(100); 896 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 897 mdelay(10); 898 writel(reset_bit, &scu->sysreset_clr_ctrl2); 899 break; 900 default: 901 return -EINVAL; 902 } 903 904 return 0; 905 } 906 907 #define SCU_CLK_ECC_RSA_FROM_HPLL_CLK BIT(19) 908 #define SCU_CLK_ECC_RSA_CLK_MASK GENMASK(27, 26) 909 #define SCU_CLK_ECC_RSA_CLK_DIV(x) ((x) << 26) 910 static void ast2600_configure_rsa_ecc_clk(struct ast2600_scu *scu) 911 { 912 u32 clk_sel = readl(&scu->clk_sel1); 913 914 /* Configure RSA clock = HPLL/3 */ 915 clk_sel |= SCU_CLK_ECC_RSA_FROM_HPLL_CLK; 916 clk_sel &= ~SCU_CLK_ECC_RSA_CLK_MASK; 917 clk_sel |= SCU_CLK_ECC_RSA_CLK_DIV(2); 918 919 writel(clk_sel, &scu->clk_sel1); 920 } 921 922 #define SCU_CLKSTOP_SDIO 4 923 static ulong ast2600_enable_sdclk(struct ast2600_scu *scu) 924 { 925 u32 reset_bit; 926 u32 clkstop_bit; 927 928 reset_bit = BIT(ASPEED_RESET_SD - 32); 929 clkstop_bit = BIT(SCU_CLKSTOP_SDIO); 930 931 writel(reset_bit, &scu->sysreset_ctrl2); 932 933 udelay(100); 934 //enable clk 935 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 936 mdelay(10); 937 writel(reset_bit, &scu->sysreset_clr_ctrl2); 938 939 return 0; 940 } 941 942 #define SCU_CLKSTOP_EXTSD 31 943 #define SCU_CLK_SD_MASK (0x7 << 28) 944 #define SCU_CLK_SD_DIV(x) ((x) << 28) 945 #define SCU_CLK_SD_FROM_APLL_CLK BIT(8) 946 947 static ulong ast2600_enable_extsdclk(struct ast2600_scu *scu) 948 { 949 u32 clk_sel = readl(&scu->clk_sel4); 950 u32 enableclk_bit; 951 u32 rate = 0; 952 u32 div = 0; 953 int i = 0; 954 955 enableclk_bit = BIT(SCU_CLKSTOP_EXTSD); 956 957 /* ast2600 sd controller max clk is 200Mhz : 958 * use apll for clock source 800/4 = 200 : controller max is 200mhz 959 */ 960 rate = ast2600_get_apll_rate(scu); 961 for (i = 0; i < 8; i++) { 962 div = (i + 1) * 2; 963 if ((rate / div) <= 200000000) 964 break; 965 } 966 clk_sel &= ~SCU_CLK_SD_MASK; 967 clk_sel |= SCU_CLK_SD_DIV(i) | SCU_CLK_SD_FROM_APLL_CLK; 968 writel(clk_sel, &scu->clk_sel4); 969 970 //enable clk 971 setbits_le32(&scu->clk_sel4, enableclk_bit); 972 973 return 0; 974 } 975 976 #define SCU_CLKSTOP_EMMC 27 977 static ulong ast2600_enable_emmcclk(struct ast2600_scu *scu) 978 { 979 u32 reset_bit; 980 u32 clkstop_bit; 981 982 reset_bit = BIT(ASPEED_RESET_EMMC); 983 clkstop_bit = BIT(SCU_CLKSTOP_EMMC); 984 985 writel(reset_bit, &scu->sysreset_ctrl1); 986 udelay(100); 987 //enable clk 988 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 989 mdelay(10); 990 writel(reset_bit, &scu->sysreset_clr_ctrl1); 991 992 return 0; 993 } 994 995 #define SCU_CLKSTOP_EXTEMMC 15 996 #define SCU_CLK_EMMC_MASK (0x7 << 12) 997 #define SCU_CLK_EMMC_DIV(x) ((x) << 12) 998 #define SCU_CLK_EMMC_FROM_MPLL_CLK BIT(11) 999 1000 static ulong ast2600_enable_extemmcclk(struct ast2600_scu *scu) 1001 { 1002 u32 revision_id = readl(&scu->chip_id1); 1003 u32 clk_sel = readl(&scu->clk_sel1); 1004 u32 enableclk_bit = BIT(SCU_CLKSTOP_EXTEMMC); 1005 u32 rate = 0; 1006 u32 div = 0; 1007 int i = 0; 1008 1009 /* 1010 * ast2600 eMMC controller max clk is 200Mhz 1011 * HPll->1/2->|\ 1012 * |->SCU300[11]->SCU300[14:12][1/N] + 1013 * MPLL------>|/ | 1014 * +----------------------------------------------+ 1015 * | 1016 * +---------> EMMC12C[15:8][1/N]-> eMMC clk 1017 */ 1018 if (((revision_id & CHIP_REVISION_ID) >> 16)) { 1019 //AST2600A1 : use mpll to be clk source 1020 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL); 1021 for (i = 0; i < 8; i++) { 1022 div = (i + 1) * 2; 1023 if ((rate / div) <= 200000000) 1024 break; 1025 } 1026 1027 clk_sel &= ~SCU_CLK_EMMC_MASK; 1028 clk_sel |= SCU_CLK_EMMC_DIV(i) | SCU_CLK_EMMC_FROM_MPLL_CLK; 1029 writel(clk_sel, &scu->clk_sel1); 1030 1031 } else { 1032 //AST2600A0 : use hpll to be clk source 1033 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 1034 1035 for (i = 0; i < 8; i++) { 1036 div = (i + 1) * 4; 1037 if ((rate / div) <= 200000000) 1038 break; 1039 } 1040 1041 clk_sel &= ~SCU_CLK_EMMC_MASK; 1042 clk_sel |= SCU_CLK_EMMC_DIV(i); 1043 writel(clk_sel, &scu->clk_sel1); 1044 } 1045 setbits_le32(&scu->clk_sel1, enableclk_bit); 1046 1047 return 0; 1048 } 1049 1050 #define SCU_CLKSTOP_FSICLK 30 1051 1052 static ulong ast2600_enable_fsiclk(struct ast2600_scu *scu) 1053 { 1054 u32 reset_bit; 1055 u32 clkstop_bit; 1056 1057 reset_bit = BIT(ASPEED_RESET_FSI % 32); 1058 clkstop_bit = BIT(SCU_CLKSTOP_FSICLK); 1059 1060 /* The FSI clock is shared between masters. If it's already on 1061 * don't touch it, as that will reset the existing master. 1062 */ 1063 if (!(readl(&scu->clk_stop_ctrl2) & clkstop_bit)) { 1064 debug("%s: already running, not touching it\n", __func__); 1065 return 0; 1066 } 1067 1068 writel(reset_bit, &scu->sysreset_ctrl2); 1069 udelay(100); 1070 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 1071 mdelay(10); 1072 writel(reset_bit, &scu->sysreset_clr_ctrl2); 1073 1074 return 0; 1075 } 1076 1077 static ulong ast2600_enable_usbahclk(struct ast2600_scu *scu) 1078 { 1079 u32 reset_bit; 1080 u32 clkstop_bit; 1081 1082 reset_bit = BIT(ASPEED_RESET_EHCI_P1); 1083 clkstop_bit = BIT(14); 1084 1085 writel(reset_bit, &scu->sysreset_ctrl1); 1086 udelay(100); 1087 writel(clkstop_bit, &scu->clk_stop_ctrl1); 1088 mdelay(20); 1089 writel(reset_bit, &scu->sysreset_clr_ctrl1); 1090 1091 return 0; 1092 } 1093 1094 static ulong ast2600_enable_usbbhclk(struct ast2600_scu *scu) 1095 { 1096 u32 reset_bit; 1097 u32 clkstop_bit; 1098 1099 reset_bit = BIT(ASPEED_RESET_EHCI_P2); 1100 clkstop_bit = BIT(7); 1101 1102 writel(reset_bit, &scu->sysreset_ctrl1); 1103 udelay(100); 1104 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 1105 mdelay(20); 1106 1107 writel(reset_bit, &scu->sysreset_clr_ctrl1); 1108 1109 return 0; 1110 } 1111 1112 static int ast2600_clk_enable(struct clk *clk) 1113 { 1114 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 1115 1116 switch (clk->id) { 1117 case ASPEED_CLK_GATE_MAC1CLK: 1118 ast2600_configure_mac(priv->scu, 1); 1119 break; 1120 case ASPEED_CLK_GATE_MAC2CLK: 1121 ast2600_configure_mac(priv->scu, 2); 1122 break; 1123 case ASPEED_CLK_GATE_MAC3CLK: 1124 ast2600_configure_mac(priv->scu, 3); 1125 break; 1126 case ASPEED_CLK_GATE_MAC4CLK: 1127 ast2600_configure_mac(priv->scu, 4); 1128 break; 1129 case ASPEED_CLK_GATE_SDCLK: 1130 ast2600_enable_sdclk(priv->scu); 1131 break; 1132 case ASPEED_CLK_GATE_SDEXTCLK: 1133 ast2600_enable_extsdclk(priv->scu); 1134 break; 1135 case ASPEED_CLK_GATE_EMMCCLK: 1136 ast2600_enable_emmcclk(priv->scu); 1137 break; 1138 case ASPEED_CLK_GATE_EMMCEXTCLK: 1139 ast2600_enable_extemmcclk(priv->scu); 1140 break; 1141 case ASPEED_CLK_GATE_FSICLK: 1142 ast2600_enable_fsiclk(priv->scu); 1143 break; 1144 case ASPEED_CLK_GATE_USBPORT1CLK: 1145 ast2600_enable_usbahclk(priv->scu); 1146 break; 1147 case ASPEED_CLK_GATE_USBPORT2CLK: 1148 ast2600_enable_usbbhclk(priv->scu); 1149 break; 1150 default: 1151 pr_err("can't enable clk\n"); 1152 return -ENOENT; 1153 } 1154 1155 return 0; 1156 } 1157 1158 struct clk_ops ast2600_clk_ops = { 1159 .get_rate = ast2600_clk_get_rate, 1160 .set_rate = ast2600_clk_set_rate, 1161 .enable = ast2600_clk_enable, 1162 }; 1163 1164 static int ast2600_clk_probe(struct udevice *dev) 1165 { 1166 struct ast2600_clk_priv *priv = dev_get_priv(dev); 1167 u32 uart_clk_source; 1168 1169 priv->scu = devfdt_get_addr_ptr(dev); 1170 if (IS_ERR(priv->scu)) 1171 return PTR_ERR(priv->scu); 1172 1173 uart_clk_source = dev_read_u32_default(dev, "uart-clk-source", 0x0); 1174 1175 if (uart_clk_source) { 1176 if (uart_clk_source & GENMASK(5, 0)) 1177 setbits_le32(&priv->scu->clk_sel4, 1178 uart_clk_source & GENMASK(5, 0)); 1179 if (uart_clk_source & GENMASK(12, 6)) 1180 setbits_le32(&priv->scu->clk_sel5, 1181 uart_clk_source & GENMASK(12, 6)); 1182 } 1183 1184 ast2600_init_rgmii_clk(priv->scu, &rgmii_clk_defconfig); 1185 ast2600_init_rmii_clk(priv->scu, &rmii_clk_defconfig); 1186 ast2600_configure_mac12_clk(priv->scu); 1187 ast2600_configure_mac34_clk(priv->scu); 1188 ast2600_configure_rsa_ecc_clk(priv->scu); 1189 1190 return 0; 1191 } 1192 1193 static int ast2600_clk_bind(struct udevice *dev) 1194 { 1195 int ret; 1196 1197 /* The reset driver does not have a device node, so bind it here */ 1198 ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev); 1199 if (ret) 1200 debug("Warning: No reset driver: ret=%d\n", ret); 1201 1202 return 0; 1203 } 1204 1205 struct aspeed_clks { 1206 ulong id; 1207 const char *name; 1208 }; 1209 1210 static struct aspeed_clks aspeed_clk_names[] = { 1211 { ASPEED_CLK_HPLL, "hpll" }, { ASPEED_CLK_MPLL, "mpll" }, 1212 { ASPEED_CLK_APLL, "apll" }, { ASPEED_CLK_EPLL, "epll" }, 1213 { ASPEED_CLK_DPLL, "dpll" }, { ASPEED_CLK_AHB, "hclk" }, 1214 { ASPEED_CLK_APB1, "pclk1" }, { ASPEED_CLK_APB2, "pclk2" }, 1215 { ASPEED_CLK_BCLK, "bclk" }, { ASPEED_CLK_UARTX, "uxclk" }, 1216 { ASPEED_CLK_HUARTX, "huxclk" }, 1217 }; 1218 1219 int soc_clk_dump(void) 1220 { 1221 struct udevice *dev; 1222 struct clk clk; 1223 unsigned long rate; 1224 int i, ret; 1225 1226 ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu), 1227 &dev); 1228 if (ret) 1229 return ret; 1230 1231 printf("Clk\t\tHz\n"); 1232 1233 for (i = 0; i < ARRAY_SIZE(aspeed_clk_names); i++) { 1234 clk.id = aspeed_clk_names[i].id; 1235 ret = clk_request(dev, &clk); 1236 if (ret < 0) { 1237 debug("%s clk_request() failed: %d\n", __func__, ret); 1238 continue; 1239 } 1240 1241 ret = clk_get_rate(&clk); 1242 rate = ret; 1243 1244 clk_free(&clk); 1245 1246 if (ret == -ENOTSUPP) { 1247 printf("clk ID %lu not supported yet\n", 1248 aspeed_clk_names[i].id); 1249 continue; 1250 } 1251 if (ret < 0) { 1252 printf("%s %lu: get_rate err: %d\n", __func__, 1253 aspeed_clk_names[i].id, ret); 1254 continue; 1255 } 1256 1257 printf("%s(%3lu):\t%lu\n", aspeed_clk_names[i].name, 1258 aspeed_clk_names[i].id, rate); 1259 } 1260 1261 return 0; 1262 } 1263 1264 static const struct udevice_id ast2600_clk_ids[] = { 1265 { 1266 .compatible = "aspeed,ast2600-scu", 1267 }, 1268 {} 1269 }; 1270 1271 U_BOOT_DRIVER(aspeed_scu) = { 1272 .name = "aspeed_scu", 1273 .id = UCLASS_CLK, 1274 .of_match = ast2600_clk_ids, 1275 .priv_auto_alloc_size = sizeof(struct ast2600_clk_priv), 1276 .ops = &ast2600_clk_ops, 1277 .bind = ast2600_clk_bind, 1278 .probe = ast2600_clk_probe, 1279 }; 1280