1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 */ 5 6 #include <common.h> 7 #include <linux/bitfield.h> 8 #include <linux/bitops.h> 9 #include <linux/iopoll.h> 10 #include <clk-uclass.h> 11 #include <dm.h> 12 #include <asm/io.h> 13 #include <dm/lists.h> 14 #include <asm/arch/scu_ast2600.h> 15 #include <dt-bindings/clock/ast2600-clock.h> 16 #include <dt-bindings/reset/ast2600-reset.h> 17 18 /* 19 * SCU 80 & 90 clock stop control for MAC controllers 20 */ 21 #define SCU_CLKSTOP_MAC1 (20) 22 #define SCU_CLKSTOP_MAC2 (21) 23 #define SCU_CLKSTOP_MAC3 (20) 24 #define SCU_CLKSTOP_MAC4 (21) 25 26 /* 27 * MAC Clock Delay settings 28 */ 29 #define MAC_CLK_RGMII_125M_SRC_SEL BIT(31) 30 #define MAC_CLK_RGMII_125M_SRC_PAD_RGMIICK 0 31 #define MAC_CLK_RGMII_125M_SRC_PLL 1 32 #define MAC_CLK_RMII2_50M_RCLK_O_CTRL BIT(30) 33 #define MAC_CLK_RMII2_50M_RCLK_O_DIS 0 34 #define MAC_CLK_RMII2_50M_RCLK_O_EN 1 35 #define MAC_CLK_RMII1_50M_RCLK_O_CTRL BIT(29) 36 #define MAC_CLK_RMII1_5M_RCLK_O_DIS 0 37 #define MAC_CLK_RMII1_5M_RCLK_O_EN 1 38 #define MAC_CLK_RGMIICK_PAD_DIR BIT(28) 39 #define MAC_CLK_RGMIICK_PAD_DIR_INPUT 0 40 #define MAC_CLK_RGMIICK_PAD_DIR_OUTPUT 1 41 #define MAC_CLK_RMII_TXD_FALLING_2 BIT(27) 42 #define MAC_CLK_RMII_TXD_FALLING_1 BIT(26) 43 #define MAC_CLK_RXCLK_INV_2 BIT(25) 44 #define MAC_CLK_RXCLK_INV_1 BIT(24) 45 #define MAC_CLK_1G_INPUT_DELAY_2 GENMASK(23, 18) 46 #define MAC_CLK_1G_INPUT_DELAY_1 GENMASK(17, 12) 47 #define MAC_CLK_1G_OUTPUT_DELAY_2 GENMASK(11, 6) 48 #define MAC_CLK_1G_OUTPUT_DELAY_1 GENMASK(5, 0) 49 50 #define MAC_CLK_100M_10M_RESERVED GENMASK(31, 26) 51 #define MAC_CLK_100M_10M_RXCLK_INV_2 BIT(25) 52 #define MAC_CLK_100M_10M_RXCLK_INV_1 BIT(24) 53 #define MAC_CLK_100M_10M_INPUT_DELAY_2 GENMASK(23, 18) 54 #define MAC_CLK_100M_10M_INPUT_DELAY_1 GENMASK(17, 12) 55 #define MAC_CLK_100M_10M_OUTPUT_DELAY_2 GENMASK(11, 6) 56 #define MAC_CLK_100M_10M_OUTPUT_DELAY_1 GENMASK(5, 0) 57 58 #define RGMII12_CLK_OUTPUT_DELAY_PS 1000 59 #define RGMII34_CLK_OUTPUT_DELAY_PS 1600 60 61 #define MAC_DEF_DELAY_1G FIELD_PREP(MAC_CLK_1G_OUTPUT_DELAY_1, 16) | \ 62 FIELD_PREP(MAC_CLK_1G_INPUT_DELAY_1, 10) | \ 63 FIELD_PREP(MAC_CLK_1G_OUTPUT_DELAY_2, 16) | \ 64 FIELD_PREP(MAC_CLK_1G_INPUT_DELAY_2, 10) 65 #define MAC_DEF_DELAY_100M FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_1, 16) | \ 66 FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_1, 16) | \ 67 FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_2, 16) | \ 68 FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_2, 16) 69 #define MAC_DEF_DELAY_10M FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_1, 16) | \ 70 FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_1, 16) | \ 71 FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_2, 16) | \ 72 FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_2, 16) 73 #define MAC34_DEF_DELAY_1G FIELD_PREP(MAC_CLK_1G_OUTPUT_DELAY_1, 8) | \ 74 FIELD_PREP(MAC_CLK_1G_INPUT_DELAY_1, 4) | \ 75 FIELD_PREP(MAC_CLK_1G_OUTPUT_DELAY_2, 8) | \ 76 FIELD_PREP(MAC_CLK_1G_INPUT_DELAY_2, 4) 77 #define MAC34_DEF_DELAY_100M FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_1, 8) | \ 78 FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_1, 4) | \ 79 FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_2, 8) | \ 80 FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_2, 4) 81 #define MAC34_DEF_DELAY_10M FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_1, 8) | \ 82 FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_1, 4) | \ 83 FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_2, 8) | \ 84 FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_2, 4) 85 86 /* 87 * SCU 320 & 330 Frequency counters 88 */ 89 #define FREQC_CTRL_RESERVED GENMASK(31, 30) 90 #define FREQC_CTRL_RESULT GENMASK(29, 16) 91 #define FREQC_CTRL_RING_STAGE GENMASK(15, 9) 92 #define FREQC_CTRL_PIN_O_CTRL BIT(8) 93 #define FREQC_CTRL_PIN_O_DIS 0 94 #define FREQC_CTRL_PIN_O_EN 1 95 #define FREQC_CTRL_CMP_RESULT BIT(7) 96 #define FREQC_CTRL_CMP_RESULT_FAIL 0 97 #define FREQC_CTRL_CMP_RESULT_PASS 1 98 #define FREQC_CTRL_STATUS BIT(6) 99 #define FREQC_CTRL_STATUS_NOT_FINISHED 0 100 #define FREQC_CTRL_STATUS_FINISHED 1 101 #define FREQC_CTRL_SRC_SEL GENMASK(5, 2) 102 #define FREQC_CTRL_SRC_SEL_HCLK_DIE0 9 103 #define FREQC_CTRL_SRC_SEL_DLY32_DIE0 3 104 #define FREQC_CTRL_SRC_SEL_HCLK_DIE1 1 105 #define FREQC_CTRL_SRC_SEL_DLY32_DIE1 7 106 #define FREQC_CTRL_OSC_CTRL BIT(1) 107 #define FREQC_CTRL_OSC_DIS 0 108 #define FREQC_CTRL_OSC_EN 1 109 #define FREQC_CTRL_RING_CTRL BIT(0) 110 #define FREQC_CTRL_RING_DIS 0 111 #define FREQC_CTRL_RING_EN 1 112 113 #define FREQC_RANGE_RESERVED0 GENMASK(31, 30) 114 #define FREQC_RANGE_LOWER GENMASK(29, 16) 115 #define FREQC_RANGE_RESERVED1 GENMASK(15, 14) 116 #define FREQC_RANGE_UPPER GENMASK(13, 0) 117 118 #define DLY32_NUM_OF_TAPS 32 119 #define DLY32_AVERAGE_COUNT_LOG2 4 120 #define DLY32_AVERAGE_COUNT BIT(DLY32_AVERAGE_COUNT_LOG2) 121 122 /* 123 * TGMII Clock Duty constants, taken from Aspeed SDK 124 */ 125 #define RGMII2_TXCK_DUTY 0x66 126 #define RGMII1_TXCK_DUTY 0x64 127 #define D2PLL_DEFAULT_RATE (250 * 1000 * 1000) 128 #define CHIP_REVISION_ID GENMASK(23, 16) 129 130 DECLARE_GLOBAL_DATA_PTR; 131 132 /* 133 * Clock divider/multiplier configuration struct. 134 * For H-PLL and M-PLL the formula is 135 * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1) 136 * M - Numerator 137 * N - Denumerator 138 * P - Post Divider 139 * They have the same layout in their control register. 140 * 141 * D-PLL and D2-PLL have extra divider (OD + 1), which is not 142 * yet needed and ignored by clock configurations. 143 */ 144 union ast2600_pll_reg { 145 u32 w; 146 struct { 147 unsigned int m : 13; /* bit[12:0] */ 148 unsigned int n : 6; /* bit[18:13] */ 149 unsigned int p : 4; /* bit[22:19] */ 150 unsigned int off : 1; /* bit[23] */ 151 unsigned int bypass : 1; /* bit[24] */ 152 unsigned int reset : 1; /* bit[25] */ 153 unsigned int reserved : 6; /* bit[31:26] */ 154 } b; 155 }; 156 157 struct ast2600_pll_cfg { 158 union ast2600_pll_reg reg; 159 u32 ext_reg; 160 }; 161 162 struct ast2600_pll_desc { 163 u32 in; 164 u32 out; 165 struct ast2600_pll_cfg cfg; 166 }; 167 168 static const struct ast2600_pll_desc ast2600_pll_lookup[] = { 169 { 170 .in = AST2600_CLK_IN, 171 .out = 400000000, 172 .cfg.reg.b.m = 95, 173 .cfg.reg.b.n = 2, 174 .cfg.reg.b.p = 1, 175 .cfg.ext_reg = 0x31, 176 }, { 177 .in = AST2600_CLK_IN, 178 .out = 200000000, 179 .cfg.reg.b.m = 127, 180 .cfg.reg.b.n = 0, 181 .cfg.reg.b.p = 15, 182 .cfg.ext_reg = 0x3f, 183 }, { 184 .in = AST2600_CLK_IN, 185 .out = 334000000, 186 .cfg.reg.b.m = 667, 187 .cfg.reg.b.n = 4, 188 .cfg.reg.b.p = 9, 189 .cfg.ext_reg = 0x14d, 190 }, { 191 .in = AST2600_CLK_IN, 192 .out = 1000000000, 193 .cfg.reg.b.m = 119, 194 .cfg.reg.b.n = 2, 195 .cfg.reg.b.p = 0, 196 .cfg.ext_reg = 0x3d, 197 }, { 198 .in = AST2600_CLK_IN, 199 .out = 50000000, 200 .cfg.reg.b.m = 95, 201 .cfg.reg.b.n = 2, 202 .cfg.reg.b.p = 15, 203 .cfg.ext_reg = 0x31, 204 }, 205 }; 206 207 struct mac_delay_config { 208 u32 tx_delay_1000; 209 u32 rx_delay_1000; 210 u32 tx_delay_100; 211 u32 rx_delay_100; 212 u32 tx_delay_10; 213 u32 rx_delay_10; 214 }; 215 216 extern u32 ast2600_get_pll_rate(struct ast2600_scu *scu, int pll_idx) 217 { 218 u32 clkin = AST2600_CLK_IN; 219 u32 pll_reg = 0; 220 unsigned int mult, div = 1; 221 222 switch (pll_idx) { 223 case ASPEED_CLK_HPLL: 224 pll_reg = readl(&scu->h_pll_param); 225 break; 226 case ASPEED_CLK_MPLL: 227 pll_reg = readl(&scu->m_pll_param); 228 break; 229 case ASPEED_CLK_DPLL: 230 pll_reg = readl(&scu->d_pll_param); 231 break; 232 case ASPEED_CLK_EPLL: 233 pll_reg = readl(&scu->e_pll_param); 234 break; 235 } 236 if (pll_reg & BIT(24)) { 237 /* Pass through mode */ 238 mult = 1; 239 div = 1; 240 } else { 241 union ast2600_pll_reg reg; 242 /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) 243 * HPLL Numerator (M) = fix 0x5F when SCU500[10]=1 244 * Fixed 0xBF when SCU500[10]=0 and SCU500[8]=1 245 * SCU200[12:0] (default 0x8F) when SCU510[10]=0 and SCU510[8]=0 246 * HPLL Denumerator (N) = SCU200[18:13] (default 0x2) 247 * HPLL Divider (P) = SCU200[22:19] (default 0x0) 248 * HPLL Bandwidth Adj (NB) = fix 0x2F when SCU500[10]=1 249 * Fixed 0x5F when SCU500[10]=0 and SCU500[8]=1 250 * SCU204[11:0] (default 0x31) when SCU500[10]=0 and SCU500[8]=0 251 */ 252 reg.w = pll_reg; 253 if (pll_idx == ASPEED_CLK_HPLL) { 254 u32 hwstrap1 = readl(&scu->hwstrap1.hwstrap); 255 256 if (hwstrap1 & BIT(10)) { 257 reg.b.m = 0x5F; 258 } else { 259 if (hwstrap1 & BIT(8)) 260 reg.b.m = 0xBF; 261 /* Otherwise keep default 0x8F */ 262 } 263 } 264 mult = (reg.b.m + 1) / (reg.b.n + 1); 265 div = (reg.b.p + 1); 266 } 267 268 return ((clkin * mult) / div); 269 } 270 271 extern u32 ast2600_get_apll_rate(struct ast2600_scu *scu) 272 { 273 u32 hw_rev = readl(&scu->chip_id1); 274 u32 clkin = AST2600_CLK_IN; 275 u32 apll_reg = readl(&scu->a_pll_param); 276 unsigned int mult, div = 1; 277 278 if (((hw_rev & CHIP_REVISION_ID) >> 16) >= 2) { 279 //after A2 version 280 if (apll_reg & BIT(24)) { 281 /* Pass through mode */ 282 mult = 1; 283 div = 1; 284 } else { 285 /* F = 25Mhz * [(m + 1) / (n + 1)] / (p + 1) */ 286 u32 m = apll_reg & 0x1fff; 287 u32 n = (apll_reg >> 13) & 0x3f; 288 u32 p = (apll_reg >> 19) & 0xf; 289 290 mult = (m + 1); 291 div = (n + 1) * (p + 1); 292 } 293 } else { 294 if (apll_reg & BIT(20)) { 295 /* Pass through mode */ 296 mult = 1; 297 div = 1; 298 } else { 299 /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */ 300 u32 m = (apll_reg >> 5) & 0x3f; 301 u32 od = (apll_reg >> 4) & 0x1; 302 u32 n = apll_reg & 0xf; 303 304 mult = (2 - od) * (m + 2); 305 div = n + 1; 306 } 307 } 308 309 return ((clkin * mult) / div); 310 } 311 312 static u32 ast2600_a0_axi_ahb_div_table[] = { 313 2, 314 2, 315 3, 316 4, 317 }; 318 319 static u32 ast2600_a1_axi_ahb_div0_table[] = { 320 3, 321 2, 322 3, 323 4, 324 }; 325 326 static u32 ast2600_a1_axi_ahb_div1_table[] = { 327 3, 328 4, 329 6, 330 8, 331 }; 332 333 static u32 ast2600_a1_axi_ahb_default_table[] = { 334 3, 4, 3, 4, 2, 2, 2, 2, 335 }; 336 337 static u32 ast2600_get_hclk(struct ast2600_scu *scu) 338 { 339 u32 hw_rev = readl(&scu->chip_id1); 340 u32 hwstrap1 = readl(&scu->hwstrap1.hwstrap); 341 u32 axi_div = 1; 342 u32 ahb_div = 0; 343 u32 rate = 0; 344 345 if ((hw_rev & CHIP_REVISION_ID) >> 16) { 346 //After A0 347 if (hwstrap1 & BIT(16)) { 348 ast2600_a1_axi_ahb_div1_table[0] = 349 ast2600_a1_axi_ahb_default_table[(hwstrap1 >> 8) & 350 0x7] * 2; 351 axi_div = 1; 352 ahb_div = 353 ast2600_a1_axi_ahb_div1_table[(hwstrap1 >> 11) & 354 0x3]; 355 } else { 356 ast2600_a1_axi_ahb_div0_table[0] = 357 ast2600_a1_axi_ahb_default_table[(hwstrap1 >> 8) & 358 0x7]; 359 axi_div = 2; 360 ahb_div = 361 ast2600_a1_axi_ahb_div0_table[(hwstrap1 >> 11) & 362 0x3]; 363 } 364 } else { 365 //A0 : fix axi = hpll / 2 366 axi_div = 2; 367 ahb_div = ast2600_a0_axi_ahb_div_table[(hwstrap1 >> 11) & 0x3]; 368 } 369 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 370 371 return (rate / axi_div / ahb_div); 372 } 373 374 static u32 ast2600_get_bclk_rate(struct ast2600_scu *scu) 375 { 376 u32 rate; 377 u32 bclk_sel = (readl(&scu->clk_sel1) >> 20) & 0x7; 378 379 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 380 381 return (rate / ((bclk_sel + 1) * 4)); 382 } 383 384 static u32 ast2600_hpll_pclk1_div_table[] = { 385 4, 8, 12, 16, 20, 24, 28, 32, 386 }; 387 388 static u32 ast2600_hpll_pclk2_div_table[] = { 389 2, 4, 6, 8, 10, 12, 14, 16, 390 }; 391 392 static u32 ast2600_get_pclk1(struct ast2600_scu *scu) 393 { 394 u32 clk_sel1 = readl(&scu->clk_sel1); 395 u32 apb_div = ast2600_hpll_pclk1_div_table[((clk_sel1 >> 23) & 0x7)]; 396 u32 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 397 398 return (rate / apb_div); 399 } 400 401 static u32 ast2600_get_pclk2(struct ast2600_scu *scu) 402 { 403 u32 clk_sel4 = readl(&scu->clk_sel4); 404 u32 apb_div = ast2600_hpll_pclk2_div_table[((clk_sel4 >> 9) & 0x7)]; 405 u32 rate = ast2600_get_hclk(scu); 406 407 return (rate / apb_div); 408 } 409 410 static u32 ast2600_get_uxclk_in_rate(struct ast2600_scu *scu) 411 { 412 u32 clk_in = 0; 413 u32 uxclk_sel = readl(&scu->clk_sel5); 414 415 uxclk_sel &= 0x3; 416 switch (uxclk_sel) { 417 case 0: 418 clk_in = ast2600_get_apll_rate(scu) / 4; 419 break; 420 case 1: 421 clk_in = ast2600_get_apll_rate(scu) / 2; 422 break; 423 case 2: 424 clk_in = ast2600_get_apll_rate(scu); 425 break; 426 case 3: 427 clk_in = ast2600_get_hclk(scu); 428 break; 429 } 430 431 return clk_in; 432 } 433 434 static u32 ast2600_get_huxclk_in_rate(struct ast2600_scu *scu) 435 { 436 u32 clk_in = 0; 437 u32 huclk_sel = readl(&scu->clk_sel5); 438 439 huclk_sel = ((huclk_sel >> 3) & 0x3); 440 switch (huclk_sel) { 441 case 0: 442 clk_in = ast2600_get_apll_rate(scu) / 4; 443 break; 444 case 1: 445 clk_in = ast2600_get_apll_rate(scu) / 2; 446 break; 447 case 2: 448 clk_in = ast2600_get_apll_rate(scu); 449 break; 450 case 3: 451 clk_in = ast2600_get_hclk(scu); 452 break; 453 } 454 455 return clk_in; 456 } 457 458 static u32 ast2600_get_uart_uxclk_rate(struct ast2600_scu *scu) 459 { 460 u32 clk_in = ast2600_get_uxclk_in_rate(scu); 461 u32 div_reg = readl(&scu->uart_24m_ref_uxclk); 462 unsigned int mult, div; 463 464 u32 n = (div_reg >> 8) & 0x3ff; 465 u32 r = div_reg & 0xff; 466 467 mult = r; 468 div = (n * 2); 469 return (clk_in * mult) / div; 470 } 471 472 static u32 ast2600_get_uart_huxclk_rate(struct ast2600_scu *scu) 473 { 474 u32 clk_in = ast2600_get_huxclk_in_rate(scu); 475 u32 div_reg = readl(&scu->uart_24m_ref_huxclk); 476 477 unsigned int mult, div; 478 479 u32 n = (div_reg >> 8) & 0x3ff; 480 u32 r = div_reg & 0xff; 481 482 mult = r; 483 div = (n * 2); 484 return (clk_in * mult) / div; 485 } 486 487 static u32 ast2600_get_sdio_clk_rate(struct ast2600_scu *scu) 488 { 489 u32 clkin = 0; 490 u32 clk_sel = readl(&scu->clk_sel4); 491 u32 div = (clk_sel >> 28) & 0x7; 492 u32 hw_rev = readl(&scu->chip_id1); 493 494 if (clk_sel & BIT(8)) 495 clkin = ast2600_get_apll_rate(scu); 496 else 497 clkin = ast2600_get_hclk(scu); 498 499 div = (1 + div) * 2; 500 if (((hw_rev & GENMASK(23, 16)) >> 16) >= 2) 501 div = (div & 0xf) ? div : 1; 502 503 return (clkin / div); 504 } 505 506 static u32 ast2600_get_emmc_clk_rate(struct ast2600_scu *scu) 507 { 508 u32 mmc_clk_src = readl(&scu->clk_sel1); 509 u32 clkin; 510 u32 clk_sel = readl(&scu->clk_sel1); 511 u32 div = (clk_sel >> 12) & 0x7; 512 513 if (mmc_clk_src & BIT(11)) { 514 /* emmc clock comes from MPLL */ 515 clkin = ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL); 516 div = (div + 1) * 2; 517 } else { 518 clkin = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 519 div = (div + 1) << 2; 520 } 521 522 return (clkin / div); 523 } 524 525 static u32 ast2600_get_uart_clk_rate(struct ast2600_scu *scu, int uart_idx) 526 { 527 u32 hicr9 = readl(0x1e789098); 528 u32 uart_sel = readl(&scu->clk_sel4); 529 u32 uart_sel5 = readl(&scu->clk_sel5); 530 ulong uart_clk = 0; 531 532 switch (uart_idx) { 533 case 1: 534 case 2: 535 case 3: 536 case 4: 537 hicr9 &= ~(BIT(uart_idx + 3)); 538 writel(hicr9, 0x1e789098); 539 case 6: 540 if (uart_sel & BIT(uart_idx - 1)) 541 uart_clk = ast2600_get_uart_huxclk_rate(scu); 542 else 543 uart_clk = ast2600_get_uart_uxclk_rate(scu); 544 break; 545 case 5: //24mhz is come form usb phy 48Mhz 546 { 547 u8 uart5_clk_sel = 0; 548 //high bit 549 if (readl(&scu->misc_ctrl1) & BIT(12)) 550 uart5_clk_sel = 0x2; 551 else 552 uart5_clk_sel = 0x0; 553 554 if (readl(&scu->clk_sel2) & BIT(14)) 555 uart5_clk_sel |= 0x1; 556 557 switch (uart5_clk_sel) { 558 case 0: 559 uart_clk = 24000000; 560 break; 561 case 1: 562 uart_clk = 192000000; 563 break; 564 case 2: 565 uart_clk = 24000000 / 13; 566 break; 567 case 3: 568 uart_clk = 192000000 / 13; 569 break; 570 } 571 } break; 572 case 7: 573 case 8: 574 case 9: 575 case 10: 576 case 11: 577 case 12: 578 case 13: 579 if (uart_sel5 & BIT(uart_idx - 1)) 580 uart_clk = ast2600_get_uart_huxclk_rate(scu); 581 else 582 uart_clk = ast2600_get_uart_uxclk_rate(scu); 583 break; 584 } 585 586 return uart_clk; 587 } 588 589 static ulong ast2600_clk_get_rate(struct clk *clk) 590 { 591 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 592 ulong rate = 0; 593 594 switch (clk->id) { 595 case ASPEED_CLK_HPLL: 596 case ASPEED_CLK_EPLL: 597 case ASPEED_CLK_DPLL: 598 case ASPEED_CLK_MPLL: 599 rate = ast2600_get_pll_rate(priv->scu, clk->id); 600 break; 601 case ASPEED_CLK_AHB: 602 rate = ast2600_get_hclk(priv->scu); 603 break; 604 case ASPEED_CLK_APB1: 605 rate = ast2600_get_pclk1(priv->scu); 606 break; 607 case ASPEED_CLK_APB2: 608 rate = ast2600_get_pclk2(priv->scu); 609 break; 610 case ASPEED_CLK_APLL: 611 rate = ast2600_get_apll_rate(priv->scu); 612 break; 613 case ASPEED_CLK_GATE_UART1CLK: 614 rate = ast2600_get_uart_clk_rate(priv->scu, 1); 615 break; 616 case ASPEED_CLK_GATE_UART2CLK: 617 rate = ast2600_get_uart_clk_rate(priv->scu, 2); 618 break; 619 case ASPEED_CLK_GATE_UART3CLK: 620 rate = ast2600_get_uart_clk_rate(priv->scu, 3); 621 break; 622 case ASPEED_CLK_GATE_UART4CLK: 623 rate = ast2600_get_uart_clk_rate(priv->scu, 4); 624 break; 625 case ASPEED_CLK_GATE_UART5CLK: 626 rate = ast2600_get_uart_clk_rate(priv->scu, 5); 627 break; 628 case ASPEED_CLK_BCLK: 629 rate = ast2600_get_bclk_rate(priv->scu); 630 break; 631 case ASPEED_CLK_SDIO: 632 rate = ast2600_get_sdio_clk_rate(priv->scu); 633 break; 634 case ASPEED_CLK_EMMC: 635 rate = ast2600_get_emmc_clk_rate(priv->scu); 636 break; 637 case ASPEED_CLK_UARTX: 638 rate = ast2600_get_uart_uxclk_rate(priv->scu); 639 break; 640 case ASPEED_CLK_HUARTX: 641 rate = ast2600_get_uart_huxclk_rate(priv->scu); 642 break; 643 default: 644 pr_debug("can't get clk rate\n"); 645 return -ENOENT; 646 } 647 648 return rate; 649 } 650 651 /** 652 * @brief lookup PLL divider config by input/output rate 653 * @param[in] *pll - PLL descriptor 654 * @return true - if PLL divider config is found, false - else 655 * The function caller shall fill "pll->in" and "pll->out", 656 * then this function will search the lookup table 657 * to find a valid PLL divider configuration. 658 */ 659 static bool ast2600_search_clock_config(struct ast2600_pll_desc *pll) 660 { 661 u32 i; 662 bool is_found = false; 663 664 for (i = 0; i < ARRAY_SIZE(ast2600_pll_lookup); i++) { 665 const struct ast2600_pll_desc *def_cfg = &ast2600_pll_lookup[i]; 666 667 if (def_cfg->in == pll->in && def_cfg->out == pll->out) { 668 is_found = true; 669 pll->cfg.reg.w = def_cfg->cfg.reg.w; 670 pll->cfg.ext_reg = def_cfg->cfg.ext_reg; 671 break; 672 } 673 } 674 return is_found; 675 } 676 677 static u32 ast2600_configure_pll(struct ast2600_scu *scu, 678 struct ast2600_pll_cfg *p_cfg, int pll_idx) 679 { 680 u32 addr, addr_ext; 681 u32 reg; 682 683 switch (pll_idx) { 684 case ASPEED_CLK_HPLL: 685 addr = (u32)(&scu->h_pll_param); 686 addr_ext = (u32)(&scu->h_pll_ext_param); 687 break; 688 case ASPEED_CLK_MPLL: 689 addr = (u32)(&scu->m_pll_param); 690 addr_ext = (u32)(&scu->m_pll_ext_param); 691 break; 692 case ASPEED_CLK_DPLL: 693 addr = (u32)(&scu->d_pll_param); 694 addr_ext = (u32)(&scu->d_pll_ext_param); 695 break; 696 case ASPEED_CLK_EPLL: 697 addr = (u32)(&scu->e_pll_param); 698 addr_ext = (u32)(&scu->e_pll_ext_param); 699 break; 700 default: 701 debug("unknown PLL index\n"); 702 return 1; 703 } 704 705 p_cfg->reg.b.bypass = 0; 706 p_cfg->reg.b.off = 1; 707 p_cfg->reg.b.reset = 1; 708 709 reg = readl(addr); 710 reg &= ~GENMASK(25, 0); 711 reg |= p_cfg->reg.w; 712 writel(reg, addr); 713 714 /* write extend parameter */ 715 writel(p_cfg->ext_reg, addr_ext); 716 udelay(100); 717 p_cfg->reg.b.off = 0; 718 p_cfg->reg.b.reset = 0; 719 reg &= ~GENMASK(25, 0); 720 reg |= p_cfg->reg.w; 721 writel(reg, addr); 722 while (!(readl(addr_ext) & BIT(31))) 723 ; 724 725 return 0; 726 } 727 728 static u32 ast2600_configure_ddr(struct ast2600_scu *scu, ulong rate) 729 { 730 struct ast2600_pll_desc mpll; 731 732 mpll.in = AST2600_CLK_IN; 733 mpll.out = rate; 734 if (ast2600_search_clock_config(&mpll) == false) { 735 printf("error!! unable to find valid DDR clock setting\n"); 736 return 0; 737 } 738 ast2600_configure_pll(scu, &mpll.cfg, ASPEED_CLK_MPLL); 739 740 return ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL); 741 } 742 743 static ulong ast2600_clk_set_rate(struct clk *clk, ulong rate) 744 { 745 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 746 ulong new_rate; 747 748 switch (clk->id) { 749 case ASPEED_CLK_MPLL: 750 new_rate = ast2600_configure_ddr(priv->scu, rate); 751 break; 752 default: 753 return -ENOENT; 754 } 755 756 return new_rate; 757 } 758 759 static int ast2600_calc_dly32_time(struct ast2600_scu *scu, int die_id, int stage) 760 { 761 int ret, i; 762 u64 sum = 0; 763 u32 base, value, reset_sel, dly32_sel; 764 765 if (die_id) { 766 base = (u32)&scu->freq_counter_ctrl2; 767 reset_sel = FREQC_CTRL_SRC_SEL_HCLK_DIE1; 768 dly32_sel = FREQC_CTRL_SRC_SEL_DLY32_DIE1; 769 } else { 770 base = (u32)&scu->freq_counter_ctrl1; 771 reset_sel = FREQC_CTRL_SRC_SEL_HCLK_DIE0; 772 dly32_sel = FREQC_CTRL_SRC_SEL_DLY32_DIE0; 773 } 774 775 for (i = 0; i < DLY32_AVERAGE_COUNT; i++) { 776 /* reset frequency-counter */ 777 writel(FIELD_PREP(FREQC_CTRL_SRC_SEL, reset_sel), base); 778 ret = readl_poll_timeout(base, value, !(value & FREQC_CTRL_RESULT), 1000); 779 if (ret) 780 return -1; 781 782 /* start frequency counter */ 783 value = FIELD_PREP(FREQC_CTRL_RING_STAGE, stage) 784 | FIELD_PREP(FREQC_CTRL_SRC_SEL, dly32_sel) 785 | FIELD_PREP(FREQC_CTRL_RING_CTRL, FREQC_CTRL_RING_EN); 786 writel(value, base); 787 788 /* delay for a while for settling down */ 789 udelay(100); 790 791 /* enable osc for measurement */ 792 value |= FIELD_PREP(FREQC_CTRL_OSC_CTRL, FREQC_CTRL_OSC_EN); 793 writel(value, base); 794 ret = readl_poll_timeout(base, value, value & FREQC_CTRL_STATUS, 1000); 795 if (ret) 796 return -1; 797 798 /* the result is represented in T count, will translate to pico-second later */ 799 sum += FIELD_GET(FREQC_CTRL_RESULT, value); 800 } 801 802 /* return the DLY32 value in pico-second */ 803 return (2560000 / (int)(sum >> DLY32_AVERAGE_COUNT_LOG2)); 804 } 805 806 static void ast2600_init_dly32_lookup(struct ast2600_clk_priv *priv) 807 { 808 struct ast2600_scu *scu = priv->scu; 809 int i; 810 811 for (i = 0; i < DLY32_NUM_OF_TAPS; i++) { 812 priv->dly32_lookup[0][i] = ast2600_calc_dly32_time(scu, 0, i); 813 priv->dly32_lookup[1][i] = ast2600_calc_dly32_time(scu, 1, i); 814 } 815 816 #ifdef DEBUG 817 for (i = 0; i < DLY32_NUM_OF_TAPS; i++) 818 printf("28nm DLY32[%d] = %d ps\n", i, priv->dly32_lookup[0][i]); 819 820 for (i = 0; i < DLY32_NUM_OF_TAPS; i++) 821 printf("55nm DLY32[%d] = %d ps\n", i, priv->dly32_lookup[1][i]); 822 #endif 823 } 824 825 /** 826 * @brief find the DLY32 tap number fitting the target delay time 827 * 828 * @param target_pico_sec target delay time in pico-second 829 * @param lookup DLY32 lookup table 830 * @return int DLY32 tap number 831 */ 832 static int ast2600_find_dly32_tap(int target_pico_sec, int *lookup) 833 { 834 int tap = DLY32_NUM_OF_TAPS >> 1; 835 int lower = 0; 836 int upper = DLY32_NUM_OF_TAPS - 1; 837 838 /* binary search for the proper delay tap */ 839 for (;;) { 840 if (tap == 0 || tap == DLY32_NUM_OF_TAPS - 1) 841 return -1; 842 843 if (lookup[tap] >= target_pico_sec && lookup[tap - 1] < target_pico_sec) { 844 return tap; 845 } else if (lookup[tap] > target_pico_sec) { 846 upper = tap; 847 tap = (tap + lower) >> 1; 848 } else if (lookup[tap] < target_pico_sec) { 849 lower = tap; 850 tap = (tap + upper) >> 1; 851 } 852 } 853 } 854 855 static u32 ast2600_configure_mac12_clk(struct ast2600_clk_priv *priv, struct udevice *dev) 856 { 857 struct ast2600_scu *scu = priv->scu; 858 struct mac_delay_config mac1_cfg, mac2_cfg; 859 u32 reg[3]; 860 int ret; 861 862 reg[0] = MAC_DEF_DELAY_1G; 863 reg[1] = MAC_DEF_DELAY_100M; 864 reg[2] = MAC_DEF_DELAY_10M; 865 866 ret = ast2600_find_dly32_tap(RGMII12_CLK_OUTPUT_DELAY_PS, priv->dly32_lookup[0]); 867 if (ret > 0) { 868 debug("suggested tx delay for mac1/2: %d\n", ret); 869 870 reg[0] &= ~(MAC_CLK_1G_OUTPUT_DELAY_1 | MAC_CLK_1G_OUTPUT_DELAY_2); 871 reg[0] |= FIELD_PREP(MAC_CLK_1G_OUTPUT_DELAY_1, ret) | 872 FIELD_PREP(MAC_CLK_1G_OUTPUT_DELAY_2, ret); 873 reg[1] &= ~(MAC_CLK_100M_10M_OUTPUT_DELAY_1 | MAC_CLK_100M_10M_OUTPUT_DELAY_2); 874 reg[1] |= FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_1, ret) | 875 FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_2, ret); 876 reg[2] &= ~(MAC_CLK_100M_10M_OUTPUT_DELAY_1 | MAC_CLK_100M_10M_OUTPUT_DELAY_2); 877 reg[2] |= FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_1, ret) | 878 FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_2, ret); 879 } 880 ret = dev_read_u32_array(dev, "mac0-clk-delay", (u32 *)&mac1_cfg, 881 sizeof(mac1_cfg) / sizeof(u32)); 882 if (!ret) { 883 reg[0] &= ~(MAC_CLK_1G_INPUT_DELAY_1 | MAC_CLK_1G_OUTPUT_DELAY_1); 884 reg[0] |= FIELD_PREP(MAC_CLK_1G_INPUT_DELAY_1, mac1_cfg.rx_delay_1000) | 885 FIELD_PREP(MAC_CLK_1G_OUTPUT_DELAY_1, mac1_cfg.tx_delay_1000); 886 887 reg[1] &= ~(MAC_CLK_100M_10M_INPUT_DELAY_1 | MAC_CLK_100M_10M_OUTPUT_DELAY_1); 888 reg[1] |= FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_1, mac1_cfg.rx_delay_100) | 889 FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_1, mac1_cfg.tx_delay_100); 890 891 reg[2] &= ~(MAC_CLK_100M_10M_INPUT_DELAY_1 | MAC_CLK_100M_10M_OUTPUT_DELAY_1); 892 reg[2] |= FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_1, mac1_cfg.rx_delay_10) | 893 FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_1, mac1_cfg.tx_delay_10); 894 } 895 896 ret = dev_read_u32_array(dev, "mac1-clk-delay", (u32 *)&mac2_cfg, 897 sizeof(mac2_cfg) / sizeof(u32)); 898 if (!ret) { 899 reg[0] &= ~(MAC_CLK_1G_INPUT_DELAY_2 | MAC_CLK_1G_OUTPUT_DELAY_2); 900 reg[0] |= FIELD_PREP(MAC_CLK_1G_INPUT_DELAY_2, mac2_cfg.rx_delay_1000) | 901 FIELD_PREP(MAC_CLK_1G_OUTPUT_DELAY_2, mac2_cfg.tx_delay_1000); 902 903 reg[1] &= ~(MAC_CLK_100M_10M_INPUT_DELAY_2 | MAC_CLK_100M_10M_OUTPUT_DELAY_2); 904 reg[1] |= FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_2, mac2_cfg.rx_delay_100) | 905 FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_2, mac2_cfg.tx_delay_100); 906 907 reg[2] &= ~(MAC_CLK_100M_10M_INPUT_DELAY_2 | MAC_CLK_100M_10M_OUTPUT_DELAY_2); 908 reg[2] |= FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_2, mac2_cfg.rx_delay_10) | 909 FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_2, mac2_cfg.tx_delay_10); 910 } 911 912 reg[0] |= (readl(&scu->mac12_clk_delay) & ~GENMASK(25, 0)); 913 writel(reg[0], &scu->mac12_clk_delay); 914 writel(reg[1], &scu->mac12_clk_delay_100M); 915 writel(reg[2], &scu->mac12_clk_delay_10M); 916 917 /* MAC AHB = HPLL / 6 */ 918 clrsetbits_le32(&scu->clk_sel1, GENMASK(18, 16), (0x2 << 16)); 919 920 return 0; 921 } 922 923 static u32 ast2600_configure_mac34_clk(struct ast2600_clk_priv *priv, struct udevice *dev) 924 { 925 struct ast2600_scu *scu = priv->scu; 926 struct mac_delay_config mac3_cfg, mac4_cfg; 927 u32 reg[3]; 928 int ret; 929 930 reg[0] = MAC34_DEF_DELAY_1G; 931 reg[1] = MAC34_DEF_DELAY_100M; 932 reg[2] = MAC34_DEF_DELAY_10M; 933 934 ret = ast2600_find_dly32_tap(RGMII34_CLK_OUTPUT_DELAY_PS, priv->dly32_lookup[1]); 935 if (ret > 0) { 936 debug("suggested tx delay for mac3/4: %d\n", ret); 937 938 reg[0] &= ~(MAC_CLK_1G_OUTPUT_DELAY_1 | MAC_CLK_1G_OUTPUT_DELAY_2); 939 reg[0] |= FIELD_PREP(MAC_CLK_1G_OUTPUT_DELAY_1, ret) | 940 FIELD_PREP(MAC_CLK_1G_OUTPUT_DELAY_2, ret); 941 reg[1] &= ~(MAC_CLK_100M_10M_OUTPUT_DELAY_1 | MAC_CLK_100M_10M_OUTPUT_DELAY_2); 942 reg[1] |= FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_1, ret) | 943 FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_2, ret); 944 reg[2] &= ~(MAC_CLK_100M_10M_OUTPUT_DELAY_1 | MAC_CLK_100M_10M_OUTPUT_DELAY_2); 945 reg[2] |= FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_1, ret) | 946 FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_2, ret); 947 } 948 949 ret = dev_read_u32_array(dev, "mac2-clk-delay", (u32 *)&mac3_cfg, sizeof(mac3_cfg) / sizeof(u32)); 950 if (!ret) { 951 reg[0] &= ~(MAC_CLK_1G_INPUT_DELAY_1 | MAC_CLK_1G_OUTPUT_DELAY_1); 952 reg[0] |= FIELD_PREP(MAC_CLK_1G_INPUT_DELAY_1, mac3_cfg.rx_delay_1000) | 953 FIELD_PREP(MAC_CLK_1G_OUTPUT_DELAY_1, mac3_cfg.tx_delay_1000); 954 955 reg[1] &= ~(MAC_CLK_100M_10M_INPUT_DELAY_1 | MAC_CLK_100M_10M_OUTPUT_DELAY_1); 956 reg[1] |= FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_1, mac3_cfg.rx_delay_100) | 957 FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_1, mac3_cfg.tx_delay_100); 958 959 reg[2] &= ~(MAC_CLK_100M_10M_INPUT_DELAY_1 | MAC_CLK_100M_10M_OUTPUT_DELAY_1); 960 reg[2] |= FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_1, mac3_cfg.rx_delay_10) | 961 FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_1, mac3_cfg.tx_delay_10); 962 } 963 964 ret = dev_read_u32_array(dev, "mac3-clk-delay", (u32 *)&mac4_cfg, sizeof(mac4_cfg) / sizeof(u32)); 965 if (!ret) { 966 reg[0] &= ~(MAC_CLK_1G_INPUT_DELAY_2 | MAC_CLK_1G_OUTPUT_DELAY_2); 967 reg[0] |= FIELD_PREP(MAC_CLK_1G_INPUT_DELAY_2, mac4_cfg.rx_delay_1000) | 968 FIELD_PREP(MAC_CLK_1G_OUTPUT_DELAY_2, mac4_cfg.tx_delay_1000); 969 970 reg[1] &= ~(MAC_CLK_100M_10M_INPUT_DELAY_2 | MAC_CLK_100M_10M_OUTPUT_DELAY_2); 971 reg[1] |= FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_2, mac4_cfg.rx_delay_100) | 972 FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_2, mac4_cfg.tx_delay_100); 973 974 reg[2] &= ~(MAC_CLK_100M_10M_INPUT_DELAY_2 | MAC_CLK_100M_10M_OUTPUT_DELAY_2); 975 reg[2] |= FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_2, mac4_cfg.rx_delay_10) | 976 FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_2, mac4_cfg.tx_delay_10); 977 } 978 979 reg[0] |= (readl(&scu->mac34_clk_delay) & ~GENMASK(25, 0)); 980 reg[0] &= ~MAC_CLK_RGMII_125M_SRC_SEL; 981 reg[0] |= FIELD_PREP(MAC_CLK_RGMII_125M_SRC_SEL, MAC_CLK_RGMII_125M_SRC_PAD_RGMIICK); 982 writel(reg[0], &scu->mac34_clk_delay); 983 writel(reg[1], &scu->mac34_clk_delay_100M); 984 writel(reg[2], &scu->mac34_clk_delay_10M); 985 986 /* 987 * clock source seletion and divider 988 * scu310[26:24] : MAC AHB bus clock = HCLK / 2 989 * scu310[18:16] : RMII 50M = HCLK_200M / 4 990 */ 991 clrsetbits_le32(&scu->clk_sel4, (GENMASK(26, 24) | GENMASK(18, 16)), 992 ((0x0 << 24) | (0x3 << 16))); 993 994 /* 995 * set driving strength 996 * scu458[3:2] : MAC4 driving strength 997 * scu458[1:0] : MAC3 driving strength 998 */ 999 clrsetbits_le32(&scu->pinmux_ctrl16, GENMASK(3, 0), 1000 (0x3 << 2) | (0x3 << 0)); 1001 1002 return 0; 1003 } 1004 1005 /** 1006 * ast2600 RGMII clock source tree 1007 * 125M from external PAD -------->|\ 1008 * HPLL -->|\ | |---->RGMII 125M for MAC#1 & MAC#2 1009 * | |---->| divider |---->|/ + 1010 * EPLL -->|/ | 1011 * | 1012 * +---------<-----------|RGMIICK PAD output enable|<-------------+ 1013 * | 1014 * +--------------------------->|\ 1015 * | |----> RGMII 125M for MAC#3 & MAC#4 1016 * HCLK 200M ---->|divider|---->|/ 1017 * To simplify the control flow: 1018 * 1. RGMII 1/2 always use EPLL as the internal clock source 1019 * 2. RGMII 3/4 always use RGMIICK pad as the RGMII 125M source 1020 * 125M from external PAD -------->|\ 1021 * | |---->RGMII 125M for MAC#1 & MAC#2 1022 * EPLL---->| divider |--->|/ + 1023 * | 1024 * +<--------------------|RGMIICK PAD output enable|<-------------+ 1025 * | 1026 * +--------------------------->RGMII 125M for MAC#3 & MAC#4 1027 */ 1028 #define RGMIICK_SRC_PAD 0 1029 #define RGMIICK_SRC_EPLL 1 /* recommended */ 1030 #define RGMIICK_SRC_HPLL 2 1031 1032 #define RGMIICK_DIV2 1 1033 #define RGMIICK_DIV3 2 1034 #define RGMIICK_DIV4 3 1035 #define RGMIICK_DIV5 4 1036 #define RGMIICK_DIV6 5 1037 #define RGMIICK_DIV7 6 1038 #define RGMIICK_DIV8 7 /* recommended */ 1039 1040 #define RMIICK_DIV4 0 1041 #define RMIICK_DIV8 1 1042 #define RMIICK_DIV12 2 1043 #define RMIICK_DIV16 3 1044 #define RMIICK_DIV20 4 /* recommended */ 1045 #define RMIICK_DIV24 5 1046 #define RMIICK_DIV28 6 1047 #define RMIICK_DIV32 7 1048 1049 struct ast2600_mac_clk_div { 1050 u32 src; /* 0=external PAD, 1=internal PLL */ 1051 u32 fin; /* divider input speed */ 1052 u32 n; /* 0=div2, 1=div2, 2=div3, 3=div4,...,7=div8 */ 1053 u32 fout; /* fout = fin / n */ 1054 }; 1055 1056 struct ast2600_mac_clk_div rgmii_clk_defconfig = { 1057 .src = ASPEED_CLK_EPLL, 1058 .fin = 1000000000, 1059 .n = RGMIICK_DIV8, 1060 .fout = 125000000, 1061 }; 1062 1063 struct ast2600_mac_clk_div rmii_clk_defconfig = { 1064 .src = ASPEED_CLK_EPLL, 1065 .fin = 1000000000, 1066 .n = RMIICK_DIV20, 1067 .fout = 50000000, 1068 }; 1069 1070 static void ast2600_init_mac_pll(struct ast2600_scu *p_scu, 1071 struct ast2600_mac_clk_div *p_cfg) 1072 { 1073 struct ast2600_pll_desc pll; 1074 1075 pll.in = AST2600_CLK_IN; 1076 pll.out = p_cfg->fin; 1077 if (ast2600_search_clock_config(&pll) == false) { 1078 pr_err("unable to find valid ETHNET MAC clock setting\n"); 1079 debug("%s: pll cfg = 0x%08x 0x%08x\n", __func__, pll.cfg.reg.w, 1080 pll.cfg.ext_reg); 1081 debug("%s: pll cfg = %02x %02x %02x\n", __func__, 1082 pll.cfg.reg.b.m, pll.cfg.reg.b.n, pll.cfg.reg.b.p); 1083 return; 1084 } 1085 ast2600_configure_pll(p_scu, &pll.cfg, p_cfg->src); 1086 } 1087 1088 static void ast2600_init_rgmii_clk(struct ast2600_scu *p_scu, 1089 struct ast2600_mac_clk_div *p_cfg) 1090 { 1091 u32 reg_304 = readl(&p_scu->clk_sel2); 1092 u32 reg_340 = readl(&p_scu->mac12_clk_delay); 1093 u32 reg_350 = readl(&p_scu->mac34_clk_delay); 1094 1095 reg_340 &= ~(MAC_CLK_RGMII_125M_SRC_SEL | MAC_CLK_RMII2_50M_RCLK_O_CTRL | 1096 MAC_CLK_RMII1_50M_RCLK_O_CTRL | MAC_CLK_RGMIICK_PAD_DIR); 1097 /* RGMIICK PAD output enable (to MAC 3/4) */ 1098 reg_340 |= FIELD_PREP(MAC_CLK_RGMIICK_PAD_DIR, MAC_CLK_RGMIICK_PAD_DIR_OUTPUT); 1099 if (p_cfg->src == ASPEED_CLK_EPLL || p_cfg->src == ASPEED_CLK_HPLL) { 1100 /* 1101 * re-init PLL if the current PLL output frequency doesn't match 1102 * the divider setting 1103 */ 1104 if (p_cfg->fin != ast2600_get_pll_rate(p_scu, p_cfg->src)) 1105 ast2600_init_mac_pll(p_scu, p_cfg); 1106 /* select RGMII 125M from internal source */ 1107 reg_340 |= FIELD_PREP(MAC_CLK_RGMII_125M_SRC_SEL, MAC_CLK_RGMII_125M_SRC_PLL); 1108 } 1109 1110 reg_304 &= ~GENMASK(23, 20); 1111 1112 /* set clock divider */ 1113 reg_304 |= (p_cfg->n & 0x7) << 20; 1114 1115 /* select internal clock source */ 1116 if (p_cfg->src == ASPEED_CLK_HPLL) 1117 reg_304 |= BIT(23); 1118 1119 /* RGMII 3/4 clock source select */ 1120 reg_350 &= ~BIT(31); 1121 1122 writel(reg_304, &p_scu->clk_sel2); 1123 writel(reg_340, &p_scu->mac12_clk_delay); 1124 writel(reg_350, &p_scu->mac34_clk_delay); 1125 } 1126 1127 /** 1128 * ast2600 RMII/NCSI clock source tree 1129 * HPLL -->|\ 1130 * | |---->| divider |----> RMII 50M for MAC#1 & MAC#2 1131 * EPLL -->|/ 1132 * HCLK(SCLICLK)---->| divider |----> RMII 50M for MAC#3 & MAC#4 1133 */ 1134 static void ast2600_init_rmii_clk(struct ast2600_scu *p_scu, 1135 struct ast2600_mac_clk_div *p_cfg) 1136 { 1137 u32 reg_304; 1138 u32 reg_310; 1139 1140 if (p_cfg->src == ASPEED_CLK_EPLL || p_cfg->src == ASPEED_CLK_HPLL) { 1141 /* 1142 * re-init PLL if the current PLL output frequency doesn't match 1143 * the divider setting 1144 */ 1145 if (p_cfg->fin != ast2600_get_pll_rate(p_scu, p_cfg->src)) 1146 ast2600_init_mac_pll(p_scu, p_cfg); 1147 } 1148 1149 reg_304 = readl(&p_scu->clk_sel2); 1150 reg_310 = readl(&p_scu->clk_sel4); 1151 1152 reg_304 &= ~GENMASK(19, 16); 1153 1154 /* set RMII 1/2 clock divider */ 1155 reg_304 |= (p_cfg->n & 0x7) << 16; 1156 1157 /* RMII clock source selection */ 1158 if (p_cfg->src == ASPEED_CLK_HPLL) 1159 reg_304 |= BIT(19); 1160 1161 /* set RMII 3/4 clock divider */ 1162 reg_310 &= ~GENMASK(18, 16); 1163 reg_310 |= (0x3 << 16); 1164 1165 writel(reg_304, &p_scu->clk_sel2); 1166 writel(reg_310, &p_scu->clk_sel4); 1167 } 1168 1169 static u32 ast2600_configure_mac(struct ast2600_scu *scu, int index) 1170 { 1171 u32 reset_bit; 1172 u32 clkstop_bit; 1173 1174 switch (index) { 1175 case 1: 1176 reset_bit = BIT(ASPEED_RESET_MAC1); 1177 clkstop_bit = BIT(SCU_CLKSTOP_MAC1); 1178 writel(reset_bit, &scu->sysreset_ctrl1); 1179 udelay(100); 1180 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 1181 mdelay(10); 1182 writel(reset_bit, &scu->sysreset_clr_ctrl1); 1183 break; 1184 case 2: 1185 reset_bit = BIT(ASPEED_RESET_MAC2); 1186 clkstop_bit = BIT(SCU_CLKSTOP_MAC2); 1187 writel(reset_bit, &scu->sysreset_ctrl1); 1188 udelay(100); 1189 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 1190 mdelay(10); 1191 writel(reset_bit, &scu->sysreset_clr_ctrl1); 1192 break; 1193 case 3: 1194 reset_bit = BIT(ASPEED_RESET_MAC3 - 32); 1195 clkstop_bit = BIT(SCU_CLKSTOP_MAC3); 1196 writel(reset_bit, &scu->sysreset_ctrl2); 1197 udelay(100); 1198 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 1199 mdelay(10); 1200 writel(reset_bit, &scu->sysreset_clr_ctrl2); 1201 break; 1202 case 4: 1203 reset_bit = BIT(ASPEED_RESET_MAC4 - 32); 1204 clkstop_bit = BIT(SCU_CLKSTOP_MAC4); 1205 writel(reset_bit, &scu->sysreset_ctrl2); 1206 udelay(100); 1207 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 1208 mdelay(10); 1209 writel(reset_bit, &scu->sysreset_clr_ctrl2); 1210 break; 1211 default: 1212 return -EINVAL; 1213 } 1214 1215 return 0; 1216 } 1217 1218 #define SCU_CLK_ECC_RSA_FROM_HPLL_CLK BIT(19) 1219 #define SCU_CLK_ECC_RSA_CLK_MASK GENMASK(27, 26) 1220 #define SCU_CLK_ECC_RSA_CLK_DIV(x) ((x) << 26) 1221 static void ast2600_configure_rsa_ecc_clk(struct ast2600_scu *scu) 1222 { 1223 u32 clk_sel = readl(&scu->clk_sel1); 1224 1225 /* Configure RSA clock = HPLL/4 */ 1226 clk_sel |= SCU_CLK_ECC_RSA_FROM_HPLL_CLK; 1227 clk_sel &= ~SCU_CLK_ECC_RSA_CLK_MASK; 1228 clk_sel |= SCU_CLK_ECC_RSA_CLK_DIV(3); 1229 1230 writel(clk_sel, &scu->clk_sel1); 1231 } 1232 1233 #define SCU_CLKSTOP_SDIO 4 1234 static ulong ast2600_enable_sdclk(struct ast2600_scu *scu) 1235 { 1236 u32 reset_bit; 1237 u32 clkstop_bit; 1238 1239 reset_bit = BIT(ASPEED_RESET_SD - 32); 1240 clkstop_bit = BIT(SCU_CLKSTOP_SDIO); 1241 1242 writel(reset_bit, &scu->sysreset_ctrl2); 1243 1244 udelay(100); 1245 //enable clk 1246 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 1247 mdelay(10); 1248 writel(reset_bit, &scu->sysreset_clr_ctrl2); 1249 1250 return 0; 1251 } 1252 1253 #define SCU_CLKSTOP_EXTSD 31 1254 #define SCU_CLK_SD_MASK (0x7 << 28) 1255 #define SCU_CLK_SD_DIV(x) ((x) << 28) 1256 #define SCU_CLK_SD_FROM_APLL_CLK BIT(8) 1257 1258 static ulong ast2600_enable_extsdclk(struct ast2600_scu *scu) 1259 { 1260 u32 clk_sel = readl(&scu->clk_sel4); 1261 u32 enableclk_bit; 1262 u32 rate = 0; 1263 u32 div = 0; 1264 int i = 0; 1265 1266 enableclk_bit = BIT(SCU_CLKSTOP_EXTSD); 1267 1268 /* ast2600 sd controller max clk is 200Mhz : 1269 * use apll for clock source 800/4 = 200 : controller max is 200mhz 1270 */ 1271 rate = ast2600_get_apll_rate(scu); 1272 for (i = 0; i < 8; i++) { 1273 div = (i + 1) * 2; 1274 if ((rate / div) <= 200000000) 1275 break; 1276 } 1277 clk_sel &= ~SCU_CLK_SD_MASK; 1278 clk_sel |= SCU_CLK_SD_DIV(i) | SCU_CLK_SD_FROM_APLL_CLK; 1279 writel(clk_sel, &scu->clk_sel4); 1280 1281 //enable clk 1282 setbits_le32(&scu->clk_sel4, enableclk_bit); 1283 1284 return 0; 1285 } 1286 1287 #define SCU_CLKSTOP_EMMC 27 1288 static ulong ast2600_enable_emmcclk(struct ast2600_scu *scu) 1289 { 1290 u32 reset_bit; 1291 u32 clkstop_bit; 1292 1293 reset_bit = BIT(ASPEED_RESET_EMMC); 1294 clkstop_bit = BIT(SCU_CLKSTOP_EMMC); 1295 1296 writel(reset_bit, &scu->sysreset_ctrl1); 1297 udelay(100); 1298 //enable clk 1299 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 1300 mdelay(10); 1301 writel(reset_bit, &scu->sysreset_clr_ctrl1); 1302 1303 return 0; 1304 } 1305 1306 #define SCU_CLKSTOP_EXTEMMC 15 1307 #define SCU_CLK_EMMC_MASK (0x7 << 12) 1308 #define SCU_CLK_EMMC_DIV(x) ((x) << 12) 1309 #define SCU_CLK_EMMC_FROM_MPLL_CLK BIT(11) 1310 1311 static ulong ast2600_enable_extemmcclk(struct ast2600_scu *scu) 1312 { 1313 u32 revision_id = readl(&scu->chip_id1); 1314 u32 clk_sel = readl(&scu->clk_sel1); 1315 u32 enableclk_bit = BIT(SCU_CLKSTOP_EXTEMMC); 1316 u32 rate = 0; 1317 u32 div = 0; 1318 int i = 0; 1319 1320 /* 1321 * ast2600 eMMC controller max clk is 200Mhz 1322 * HPll->1/2->|\ 1323 * |->SCU300[11]->SCU300[14:12][1/N] + 1324 * MPLL------>|/ | 1325 * +----------------------------------------------+ 1326 * | 1327 * +---------> EMMC12C[15:8][1/N]-> eMMC clk 1328 */ 1329 if (((revision_id & CHIP_REVISION_ID) >> 16)) { 1330 //AST2600A1 : use mpll to be clk source 1331 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL); 1332 for (i = 0; i < 8; i++) { 1333 div = (i + 1) * 2; 1334 if ((rate / div) <= 200000000) 1335 break; 1336 } 1337 1338 clk_sel &= ~SCU_CLK_EMMC_MASK; 1339 clk_sel |= SCU_CLK_EMMC_DIV(i) | SCU_CLK_EMMC_FROM_MPLL_CLK; 1340 writel(clk_sel, &scu->clk_sel1); 1341 1342 } else { 1343 //AST2600A0 : use hpll to be clk source 1344 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 1345 1346 for (i = 0; i < 8; i++) { 1347 div = (i + 1) * 4; 1348 if ((rate / div) <= 200000000) 1349 break; 1350 } 1351 1352 clk_sel &= ~SCU_CLK_EMMC_MASK; 1353 clk_sel |= SCU_CLK_EMMC_DIV(i); 1354 writel(clk_sel, &scu->clk_sel1); 1355 } 1356 setbits_le32(&scu->clk_sel1, enableclk_bit); 1357 1358 return 0; 1359 } 1360 1361 #define SCU_CLKSTOP_FSICLK 30 1362 1363 static ulong ast2600_enable_fsiclk(struct ast2600_scu *scu) 1364 { 1365 u32 reset_bit; 1366 u32 clkstop_bit; 1367 1368 reset_bit = BIT(ASPEED_RESET_FSI % 32); 1369 clkstop_bit = BIT(SCU_CLKSTOP_FSICLK); 1370 1371 /* The FSI clock is shared between masters. If it's already on 1372 * don't touch it, as that will reset the existing master. 1373 */ 1374 if (!(readl(&scu->clk_stop_ctrl2) & clkstop_bit)) { 1375 debug("%s: already running, not touching it\n", __func__); 1376 return 0; 1377 } 1378 1379 writel(reset_bit, &scu->sysreset_ctrl2); 1380 udelay(100); 1381 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 1382 mdelay(10); 1383 writel(reset_bit, &scu->sysreset_clr_ctrl2); 1384 1385 return 0; 1386 } 1387 1388 static ulong ast2600_enable_usbahclk(struct ast2600_scu *scu) 1389 { 1390 u32 reset_bit; 1391 u32 clkstop_bit; 1392 1393 reset_bit = BIT(ASPEED_RESET_EHCI_P1); 1394 clkstop_bit = BIT(14); 1395 1396 writel(reset_bit, &scu->sysreset_ctrl1); 1397 udelay(100); 1398 writel(clkstop_bit, &scu->clk_stop_ctrl1); 1399 mdelay(20); 1400 writel(reset_bit, &scu->sysreset_clr_ctrl1); 1401 1402 return 0; 1403 } 1404 1405 static ulong ast2600_enable_usbbhclk(struct ast2600_scu *scu) 1406 { 1407 u32 reset_bit; 1408 u32 clkstop_bit; 1409 1410 reset_bit = BIT(ASPEED_RESET_EHCI_P2); 1411 clkstop_bit = BIT(7); 1412 1413 writel(reset_bit, &scu->sysreset_ctrl1); 1414 udelay(100); 1415 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 1416 mdelay(20); 1417 1418 writel(reset_bit, &scu->sysreset_clr_ctrl1); 1419 1420 return 0; 1421 } 1422 1423 /* also known as yclk */ 1424 static ulong ast2600_enable_haceclk(struct ast2600_scu *scu) 1425 { 1426 u32 reset_bit; 1427 u32 clkstop_bit; 1428 1429 reset_bit = BIT(ASPEED_RESET_HACE); 1430 clkstop_bit = BIT(13); 1431 1432 writel(reset_bit, &scu->sysreset_ctrl1); 1433 udelay(100); 1434 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 1435 mdelay(20); 1436 1437 writel(reset_bit, &scu->sysreset_clr_ctrl1); 1438 1439 return 0; 1440 } 1441 1442 static ulong ast2600_enable_rsaeccclk(struct ast2600_scu *scu) 1443 { 1444 u32 clkstop_bit; 1445 1446 clkstop_bit = BIT(24); 1447 1448 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 1449 mdelay(20); 1450 1451 return 0; 1452 } 1453 1454 static int ast2600_clk_enable(struct clk *clk) 1455 { 1456 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 1457 1458 switch (clk->id) { 1459 case ASPEED_CLK_GATE_MAC1CLK: 1460 ast2600_configure_mac(priv->scu, 1); 1461 break; 1462 case ASPEED_CLK_GATE_MAC2CLK: 1463 ast2600_configure_mac(priv->scu, 2); 1464 break; 1465 case ASPEED_CLK_GATE_MAC3CLK: 1466 ast2600_configure_mac(priv->scu, 3); 1467 break; 1468 case ASPEED_CLK_GATE_MAC4CLK: 1469 ast2600_configure_mac(priv->scu, 4); 1470 break; 1471 case ASPEED_CLK_GATE_SDCLK: 1472 ast2600_enable_sdclk(priv->scu); 1473 break; 1474 case ASPEED_CLK_GATE_SDEXTCLK: 1475 ast2600_enable_extsdclk(priv->scu); 1476 break; 1477 case ASPEED_CLK_GATE_EMMCCLK: 1478 ast2600_enable_emmcclk(priv->scu); 1479 break; 1480 case ASPEED_CLK_GATE_EMMCEXTCLK: 1481 ast2600_enable_extemmcclk(priv->scu); 1482 break; 1483 case ASPEED_CLK_GATE_FSICLK: 1484 ast2600_enable_fsiclk(priv->scu); 1485 break; 1486 case ASPEED_CLK_GATE_USBPORT1CLK: 1487 ast2600_enable_usbahclk(priv->scu); 1488 break; 1489 case ASPEED_CLK_GATE_USBPORT2CLK: 1490 ast2600_enable_usbbhclk(priv->scu); 1491 break; 1492 case ASPEED_CLK_GATE_YCLK: 1493 ast2600_enable_haceclk(priv->scu); 1494 break; 1495 case ASPEED_CLK_GATE_RSAECCCLK: 1496 ast2600_enable_rsaeccclk(priv->scu); 1497 break; 1498 default: 1499 pr_err("can't enable clk\n"); 1500 return -ENOENT; 1501 } 1502 1503 return 0; 1504 } 1505 1506 struct clk_ops ast2600_clk_ops = { 1507 .get_rate = ast2600_clk_get_rate, 1508 .set_rate = ast2600_clk_set_rate, 1509 .enable = ast2600_clk_enable, 1510 }; 1511 1512 static int ast2600_clk_probe(struct udevice *dev) 1513 { 1514 struct ast2600_clk_priv *priv = dev_get_priv(dev); 1515 u32 uart_clk_source; 1516 1517 priv->scu = devfdt_get_addr_ptr(dev); 1518 if (IS_ERR(priv->scu)) 1519 return PTR_ERR(priv->scu); 1520 1521 uart_clk_source = dev_read_u32_default(dev, "uart-clk-source", 0x0); 1522 1523 if (uart_clk_source) { 1524 if (uart_clk_source & GENMASK(5, 0)) 1525 setbits_le32(&priv->scu->clk_sel4, 1526 uart_clk_source & GENMASK(5, 0)); 1527 if (uart_clk_source & GENMASK(12, 6)) 1528 setbits_le32(&priv->scu->clk_sel5, 1529 uart_clk_source & GENMASK(12, 6)); 1530 } 1531 1532 ast2600_init_rgmii_clk(priv->scu, &rgmii_clk_defconfig); 1533 ast2600_init_rmii_clk(priv->scu, &rmii_clk_defconfig); 1534 ast2600_init_dly32_lookup(priv); 1535 ast2600_configure_mac12_clk(priv, dev); 1536 ast2600_configure_mac34_clk(priv, dev); 1537 ast2600_configure_rsa_ecc_clk(priv->scu); 1538 1539 return 0; 1540 } 1541 1542 static int ast2600_clk_bind(struct udevice *dev) 1543 { 1544 int ret; 1545 1546 /* The reset driver does not have a device node, so bind it here */ 1547 ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev); 1548 if (ret) 1549 debug("Warning: No reset driver: ret=%d\n", ret); 1550 1551 return 0; 1552 } 1553 1554 struct aspeed_clks { 1555 ulong id; 1556 const char *name; 1557 }; 1558 1559 static struct aspeed_clks aspeed_clk_names[] = { 1560 { ASPEED_CLK_HPLL, "hpll" }, { ASPEED_CLK_MPLL, "mpll" }, 1561 { ASPEED_CLK_APLL, "apll" }, { ASPEED_CLK_EPLL, "epll" }, 1562 { ASPEED_CLK_DPLL, "dpll" }, { ASPEED_CLK_AHB, "hclk" }, 1563 { ASPEED_CLK_APB1, "pclk1" }, { ASPEED_CLK_APB2, "pclk2" }, 1564 { ASPEED_CLK_BCLK, "bclk" }, { ASPEED_CLK_UARTX, "uxclk" }, 1565 { ASPEED_CLK_HUARTX, "huxclk" }, 1566 }; 1567 1568 int soc_clk_dump(void) 1569 { 1570 struct udevice *dev; 1571 struct clk clk; 1572 unsigned long rate; 1573 int i, ret; 1574 1575 ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu), 1576 &dev); 1577 if (ret) 1578 return ret; 1579 1580 printf("Clk\t\tHz\n"); 1581 1582 for (i = 0; i < ARRAY_SIZE(aspeed_clk_names); i++) { 1583 clk.id = aspeed_clk_names[i].id; 1584 ret = clk_request(dev, &clk); 1585 if (ret < 0) { 1586 debug("%s clk_request() failed: %d\n", __func__, ret); 1587 continue; 1588 } 1589 1590 ret = clk_get_rate(&clk); 1591 rate = ret; 1592 1593 clk_free(&clk); 1594 1595 if (ret == -ENOTSUPP) { 1596 printf("clk ID %lu not supported yet\n", 1597 aspeed_clk_names[i].id); 1598 continue; 1599 } 1600 if (ret < 0) { 1601 printf("%s %lu: get_rate err: %d\n", __func__, 1602 aspeed_clk_names[i].id, ret); 1603 continue; 1604 } 1605 1606 printf("%s(%3lu):\t%lu\n", aspeed_clk_names[i].name, 1607 aspeed_clk_names[i].id, rate); 1608 } 1609 1610 return 0; 1611 } 1612 1613 static const struct udevice_id ast2600_clk_ids[] = { 1614 { 1615 .compatible = "aspeed,ast2600-scu", 1616 }, 1617 {} 1618 }; 1619 1620 U_BOOT_DRIVER(aspeed_scu) = { 1621 .name = "aspeed_scu", 1622 .id = UCLASS_CLK, 1623 .of_match = ast2600_clk_ids, 1624 .priv_auto_alloc_size = sizeof(struct ast2600_clk_priv), 1625 .ops = &ast2600_clk_ops, 1626 .bind = ast2600_clk_bind, 1627 .probe = ast2600_clk_probe, 1628 }; 1629