1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 */ 5 6 #include <common.h> 7 #include <clk-uclass.h> 8 #include <dm.h> 9 #include <asm/io.h> 10 #include <dm/lists.h> 11 #include <asm/arch/scu_ast2600.h> 12 #include <dt-bindings/clock/ast2600-clock.h> 13 #include <dt-bindings/reset/ast2600-reset.h> 14 15 /* 16 * MAC Clock Delay settings 17 */ 18 #define RGMII_TXCLK_ODLY 8 19 #define RMII_RXCLK_IDLY 2 20 21 #define MAC_DEF_DELAY_1G 0x0041b75d 22 #define MAC_DEF_DELAY_100M 0x00417410 23 #define MAC_DEF_DELAY_10M 0x00417410 24 25 #define MAC34_DEF_DELAY_1G 0x0010438a 26 #define MAC34_DEF_DELAY_100M 0x00104208 27 #define MAC34_DEF_DELAY_10M 0x00104208 28 29 /* 30 * TGMII Clock Duty constants, taken from Aspeed SDK 31 */ 32 #define RGMII2_TXCK_DUTY 0x66 33 #define RGMII1_TXCK_DUTY 0x64 34 #define D2PLL_DEFAULT_RATE (250 * 1000 * 1000) 35 #define CHIP_REVISION_ID GENMASK(23, 16) 36 37 DECLARE_GLOBAL_DATA_PTR; 38 39 /* 40 * Clock divider/multiplier configuration struct. 41 * For H-PLL and M-PLL the formula is 42 * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1) 43 * M - Numerator 44 * N - Denumerator 45 * P - Post Divider 46 * They have the same layout in their control register. 47 * 48 * D-PLL and D2-PLL have extra divider (OD + 1), which is not 49 * yet needed and ignored by clock configurations. 50 */ 51 union ast2600_pll_reg { 52 unsigned int w; 53 struct { 54 unsigned int m : 13; /* bit[12:0] */ 55 unsigned int n : 6; /* bit[18:13] */ 56 unsigned int p : 4; /* bit[22:19] */ 57 unsigned int off : 1; /* bit[23] */ 58 unsigned int bypass : 1; /* bit[24] */ 59 unsigned int reset : 1; /* bit[25] */ 60 unsigned int reserved : 6; /* bit[31:26] */ 61 } b; 62 }; 63 64 struct ast2600_pll_cfg { 65 union ast2600_pll_reg reg; 66 unsigned int ext_reg; 67 }; 68 69 struct ast2600_pll_desc { 70 u32 in; 71 u32 out; 72 struct ast2600_pll_cfg cfg; 73 }; 74 75 static const struct ast2600_pll_desc ast2600_pll_lookup[] = { 76 { 77 .in = AST2600_CLK_IN, 78 .out = 400000000, 79 .cfg.reg.b.m = 95, 80 .cfg.reg.b.n = 2, 81 .cfg.reg.b.p = 1, 82 .cfg.ext_reg = 0x31, 83 }, 84 { .in = AST2600_CLK_IN, 85 .out = 200000000, 86 .cfg.reg.b.m = 127, 87 .cfg.reg.b.n = 0, 88 .cfg.reg.b.p = 15, 89 .cfg.ext_reg = 0x3f }, 90 { .in = AST2600_CLK_IN, 91 .out = 334000000, 92 .cfg.reg.b.m = 667, 93 .cfg.reg.b.n = 4, 94 .cfg.reg.b.p = 9, 95 .cfg.ext_reg = 0x14d }, 96 { .in = AST2600_CLK_IN, 97 .out = 1000000000, 98 .cfg.reg.b.m = 119, 99 .cfg.reg.b.n = 2, 100 .cfg.reg.b.p = 0, 101 .cfg.ext_reg = 0x3d }, 102 { .in = AST2600_CLK_IN, 103 .out = 50000000, 104 .cfg.reg.b.m = 95, 105 .cfg.reg.b.n = 2, 106 .cfg.reg.b.p = 15, 107 .cfg.ext_reg = 0x31 }, 108 }; 109 110 extern u32 ast2600_get_pll_rate(struct ast2600_scu *scu, int pll_idx) 111 { 112 u32 clkin = AST2600_CLK_IN; 113 u32 pll_reg = 0; 114 unsigned int mult, div = 1; 115 116 switch (pll_idx) { 117 case ASPEED_CLK_HPLL: 118 pll_reg = readl(&scu->h_pll_param); 119 break; 120 case ASPEED_CLK_MPLL: 121 pll_reg = readl(&scu->m_pll_param); 122 break; 123 case ASPEED_CLK_DPLL: 124 pll_reg = readl(&scu->d_pll_param); 125 break; 126 case ASPEED_CLK_EPLL: 127 pll_reg = readl(&scu->e_pll_param); 128 break; 129 } 130 if (pll_reg & BIT(24)) { 131 /* Pass through mode */ 132 mult = div = 1; 133 } else { 134 /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) */ 135 union ast2600_pll_reg reg; 136 reg.w = pll_reg; 137 /* 138 HPLL Numerator (M) = fix 0x5F when SCU500[10]=1 139 fix 0xBF when SCU500[10]=0 and SCU500[8]=1 140 SCU200[12:0] (default 0x8F) when SCU510[10]=0 and SCU510[8]=0 141 HPLL Denumerator (N) = SCU200[18:13] (default 0x2) 142 HPLL Divider (P) = SCU200[22:19] (default 0x0) 143 HPLL Bandwidth Adj (NB) = fix 0x2F when SCU500[10]=1 144 fix 0x5F when SCU500[10]=0 and SCU500[8]=1 145 SCU204[11:0] (default 0x31) when SCU500[10]=0 and SCU500[8]=0 146 */ 147 if (pll_idx == ASPEED_CLK_HPLL) { 148 u32 hwstrap1 = readl(&scu->hwstrap1.hwstrap); 149 if (hwstrap1 & BIT(10)) 150 reg.b.m = 0x5F; 151 else { 152 if (hwstrap1 & BIT(8)) 153 reg.b.m = 0xBF; 154 /* Otherwise keep default 0x8F */ 155 } 156 } 157 mult = (reg.b.m + 1) / (reg.b.n + 1); 158 div = (reg.b.p + 1); 159 } 160 161 return ((clkin * mult) / div); 162 } 163 164 extern u32 ast2600_get_apll_rate(struct ast2600_scu *scu) 165 { 166 u32 hw_rev = readl(&scu->chip_id1); 167 u32 clkin = AST2600_CLK_IN; 168 u32 apll_reg = readl(&scu->a_pll_param); 169 unsigned int mult, div = 1; 170 171 if (((hw_rev & CHIP_REVISION_ID) >> 16) >= 3) { 172 //after A2 version 173 if (apll_reg & BIT(24)) { 174 /* Pass through mode */ 175 mult = div = 1; 176 } else { 177 /* F = 25Mhz * [(m + 1) / (n + 1)] / (p + 1) */ 178 u32 m = apll_reg & 0x1fff; 179 u32 n = (apll_reg >> 13) & 0x3f; 180 u32 p = (apll_reg >> 19) & 0xf; 181 182 mult = (m + 1); 183 div = (n + 1) * (p + 1); 184 } 185 186 } else { 187 if (apll_reg & BIT(20)) { 188 /* Pass through mode */ 189 mult = div = 1; 190 } else { 191 /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */ 192 u32 m = (apll_reg >> 5) & 0x3f; 193 u32 od = (apll_reg >> 4) & 0x1; 194 u32 n = apll_reg & 0xf; 195 196 mult = (2 - od) * (m + 2); 197 div = n + 1; 198 } 199 } 200 201 return ((clkin * mult) / div); 202 } 203 204 static u32 ast2600_a0_axi_ahb_div_table[] = { 205 2, 206 2, 207 3, 208 4, 209 }; 210 211 static u32 ast2600_a1_axi_ahb_div0_table[] = { 212 3, 213 2, 214 3, 215 4, 216 }; 217 218 static u32 ast2600_a1_axi_ahb_div1_table[] = { 219 3, 220 4, 221 6, 222 8, 223 }; 224 225 static u32 ast2600_a1_axi_ahb_default_table[] = { 226 3, 4, 3, 4, 2, 2, 2, 2, 227 }; 228 229 static u32 ast2600_get_hclk(struct ast2600_scu *scu) 230 { 231 u32 hw_rev = readl(&scu->chip_id1); 232 u32 hwstrap1 = readl(&scu->hwstrap1.hwstrap); 233 u32 axi_div = 1; 234 u32 ahb_div = 0; 235 u32 rate = 0; 236 237 if ((hw_rev & CHIP_REVISION_ID) >> 16) { 238 //After A0 239 if (hwstrap1 & BIT(16)) { 240 ast2600_a1_axi_ahb_div1_table[0] = 241 ast2600_a1_axi_ahb_default_table[(hwstrap1 >> 8) & 242 0x3]; 243 axi_div = 1; 244 ahb_div = 245 ast2600_a1_axi_ahb_div1_table[(hwstrap1 >> 11) & 246 0x3]; 247 } else { 248 ast2600_a1_axi_ahb_div0_table[0] = 249 ast2600_a1_axi_ahb_default_table[(hwstrap1 >> 8) & 250 0x3]; 251 axi_div = 2; 252 ahb_div = 253 ast2600_a1_axi_ahb_div0_table[(hwstrap1 >> 11) & 254 0x3]; 255 } 256 } else { 257 //A0 : fix axi = hpll / 2 258 axi_div = 2; 259 ahb_div = ast2600_a0_axi_ahb_div_table[(hwstrap1 >> 11) & 0x3]; 260 } 261 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 262 263 return (rate / axi_div / ahb_div); 264 } 265 266 static u32 ast2600_get_bclk_rate(struct ast2600_scu *scu) 267 { 268 u32 rate; 269 u32 bclk_sel = (readl(&scu->clk_sel1) >> 20) & 0x7; 270 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 271 272 return (rate / ((bclk_sel + 1) * 4)); 273 } 274 275 static u32 ast2600_hpll_pclk1_div_table[] = { 276 4, 8, 12, 16, 20, 24, 28, 32, 277 }; 278 279 static u32 ast2600_hpll_pclk2_div_table[] = { 280 2, 4, 6, 8, 10, 12, 14, 16, 281 }; 282 283 static u32 ast2600_get_pclk1(struct ast2600_scu *scu) 284 { 285 u32 clk_sel1 = readl(&scu->clk_sel1); 286 u32 apb_div = ast2600_hpll_pclk1_div_table[((clk_sel1 >> 23) & 0x7)]; 287 u32 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 288 289 return (rate / apb_div); 290 } 291 292 static u32 ast2600_get_pclk2(struct ast2600_scu *scu) 293 { 294 u32 clk_sel4 = readl(&scu->clk_sel4); 295 u32 apb_div = ast2600_hpll_pclk2_div_table[((clk_sel4 >> 9) & 0x7)]; 296 u32 rate = ast2600_get_hclk(scu); 297 298 return (rate / apb_div); 299 } 300 301 static u32 ast2600_get_uxclk_in_rate(struct ast2600_scu *scu) 302 { 303 u32 clk_in = 0; 304 u32 uxclk_sel = readl(&scu->clk_sel5); 305 306 uxclk_sel &= 0x3; 307 switch (uxclk_sel) { 308 case 0: 309 clk_in = ast2600_get_apll_rate(scu) / 4; 310 break; 311 case 1: 312 clk_in = ast2600_get_apll_rate(scu) / 2; 313 break; 314 case 2: 315 clk_in = ast2600_get_apll_rate(scu); 316 break; 317 case 3: 318 clk_in = ast2600_get_hclk(scu); 319 break; 320 } 321 322 return clk_in; 323 } 324 325 static u32 ast2600_get_huxclk_in_rate(struct ast2600_scu *scu) 326 { 327 u32 clk_in = 0; 328 u32 huclk_sel = readl(&scu->clk_sel5); 329 330 huclk_sel = ((huclk_sel >> 3) & 0x3); 331 switch (huclk_sel) { 332 case 0: 333 clk_in = ast2600_get_apll_rate(scu) / 4; 334 break; 335 case 1: 336 clk_in = ast2600_get_apll_rate(scu) / 2; 337 break; 338 case 2: 339 clk_in = ast2600_get_apll_rate(scu); 340 break; 341 case 3: 342 clk_in = ast2600_get_hclk(scu); 343 break; 344 } 345 346 return clk_in; 347 } 348 349 static u32 ast2600_get_uart_uxclk_rate(struct ast2600_scu *scu) 350 { 351 u32 clk_in = ast2600_get_uxclk_in_rate(scu); 352 u32 div_reg = readl(&scu->uart_24m_ref_uxclk); 353 unsigned int mult, div; 354 355 u32 n = (div_reg >> 8) & 0x3ff; 356 u32 r = div_reg & 0xff; 357 358 mult = r; 359 div = (n * 2); 360 return (clk_in * mult) / div; 361 } 362 363 static u32 ast2600_get_uart_huxclk_rate(struct ast2600_scu *scu) 364 { 365 u32 clk_in = ast2600_get_huxclk_in_rate(scu); 366 u32 div_reg = readl(&scu->uart_24m_ref_huxclk); 367 368 unsigned int mult, div; 369 370 u32 n = (div_reg >> 8) & 0x3ff; 371 u32 r = div_reg & 0xff; 372 373 mult = r; 374 div = (n * 2); 375 return (clk_in * mult) / div; 376 } 377 378 static u32 ast2600_get_sdio_clk_rate(struct ast2600_scu *scu) 379 { 380 u32 clkin = 0; 381 u32 clk_sel = readl(&scu->clk_sel4); 382 u32 div = (clk_sel >> 28) & 0x7; 383 384 if (clk_sel & BIT(8)) { 385 clkin = ast2600_get_apll_rate(scu); 386 } else { 387 clkin = ast2600_get_hclk(scu); 388 } 389 div = (div + 1) << 1; 390 391 return (clkin / div); 392 } 393 394 static u32 ast2600_get_emmc_clk_rate(struct ast2600_scu *scu) 395 { 396 u32 clkin = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 397 u32 clk_sel = readl(&scu->clk_sel1); 398 u32 div = (clk_sel >> 12) & 0x7; 399 400 div = (div + 1) << 2; 401 402 return (clkin / div); 403 } 404 405 static u32 ast2600_get_uart_clk_rate(struct ast2600_scu *scu, int uart_idx) 406 { 407 u32 uart_sel = readl(&scu->clk_sel4); 408 u32 uart_sel5 = readl(&scu->clk_sel5); 409 ulong uart_clk = 0; 410 411 switch (uart_idx) { 412 case 1: 413 case 2: 414 case 3: 415 case 4: 416 case 6: 417 if (uart_sel & BIT(uart_idx - 1)) 418 uart_clk = ast2600_get_uart_huxclk_rate(scu); 419 else 420 uart_clk = ast2600_get_uart_uxclk_rate(scu); 421 break; 422 case 5: //24mhz is come form usb phy 48Mhz 423 { 424 u8 uart5_clk_sel = 0; 425 //high bit 426 if (readl(&scu->misc_ctrl1) & BIT(12)) 427 uart5_clk_sel = 0x2; 428 else 429 uart5_clk_sel = 0x0; 430 431 if (readl(&scu->clk_sel2) & BIT(14)) 432 uart5_clk_sel |= 0x1; 433 434 switch (uart5_clk_sel) { 435 case 0: 436 uart_clk = 24000000; 437 break; 438 case 1: 439 uart_clk = 192000000; 440 break; 441 case 2: 442 uart_clk = 24000000 / 13; 443 break; 444 case 3: 445 uart_clk = 192000000 / 13; 446 break; 447 } 448 } break; 449 case 7: 450 case 8: 451 case 9: 452 case 10: 453 case 11: 454 case 12: 455 case 13: 456 if (uart_sel5 & BIT(uart_idx - 1)) 457 uart_clk = ast2600_get_uart_huxclk_rate(scu); 458 else 459 uart_clk = ast2600_get_uart_uxclk_rate(scu); 460 break; 461 } 462 463 return uart_clk; 464 } 465 466 static ulong ast2600_clk_get_rate(struct clk *clk) 467 { 468 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 469 ulong rate = 0; 470 471 switch (clk->id) { 472 case ASPEED_CLK_HPLL: 473 case ASPEED_CLK_EPLL: 474 case ASPEED_CLK_DPLL: 475 case ASPEED_CLK_MPLL: 476 rate = ast2600_get_pll_rate(priv->scu, clk->id); 477 break; 478 case ASPEED_CLK_AHB: 479 rate = ast2600_get_hclk(priv->scu); 480 break; 481 case ASPEED_CLK_APB1: 482 rate = ast2600_get_pclk1(priv->scu); 483 break; 484 case ASPEED_CLK_APB2: 485 rate = ast2600_get_pclk2(priv->scu); 486 break; 487 case ASPEED_CLK_APLL: 488 rate = ast2600_get_apll_rate(priv->scu); 489 break; 490 case ASPEED_CLK_GATE_UART1CLK: 491 rate = ast2600_get_uart_clk_rate(priv->scu, 1); 492 break; 493 case ASPEED_CLK_GATE_UART2CLK: 494 rate = ast2600_get_uart_clk_rate(priv->scu, 2); 495 break; 496 case ASPEED_CLK_GATE_UART3CLK: 497 rate = ast2600_get_uart_clk_rate(priv->scu, 3); 498 break; 499 case ASPEED_CLK_GATE_UART4CLK: 500 rate = ast2600_get_uart_clk_rate(priv->scu, 4); 501 break; 502 case ASPEED_CLK_GATE_UART5CLK: 503 rate = ast2600_get_uart_clk_rate(priv->scu, 5); 504 break; 505 case ASPEED_CLK_BCLK: 506 rate = ast2600_get_bclk_rate(priv->scu); 507 break; 508 case ASPEED_CLK_SDIO: 509 rate = ast2600_get_sdio_clk_rate(priv->scu); 510 break; 511 case ASPEED_CLK_EMMC: 512 rate = ast2600_get_emmc_clk_rate(priv->scu); 513 break; 514 case ASPEED_CLK_UARTX: 515 rate = ast2600_get_uart_uxclk_rate(priv->scu); 516 break; 517 case ASPEED_CLK_HUARTX: 518 rate = ast2600_get_uart_huxclk_rate(priv->scu); 519 break; 520 default: 521 pr_debug("can't get clk rate \n"); 522 return -ENOENT; 523 break; 524 } 525 526 return rate; 527 } 528 529 /** 530 * @brief lookup PLL divider config by input/output rate 531 * @param[in] *pll - PLL descriptor 532 * @return true - if PLL divider config is found, false - else 533 * The function caller shall fill "pll->in" and "pll->out", 534 * then this function will search the lookup table 535 * to find a valid PLL divider configuration. 536 */ 537 static bool ast2600_search_clock_config(struct ast2600_pll_desc *pll) 538 { 539 u32 i; 540 bool is_found = false; 541 542 for (i = 0; i < ARRAY_SIZE(ast2600_pll_lookup); i++) { 543 const struct ast2600_pll_desc *def_cfg = &ast2600_pll_lookup[i]; 544 if ((def_cfg->in == pll->in) && (def_cfg->out == pll->out)) { 545 is_found = true; 546 pll->cfg.reg.w = def_cfg->cfg.reg.w; 547 pll->cfg.ext_reg = def_cfg->cfg.ext_reg; 548 break; 549 } 550 } 551 return is_found; 552 } 553 static u32 ast2600_configure_pll(struct ast2600_scu *scu, 554 struct ast2600_pll_cfg *p_cfg, int pll_idx) 555 { 556 u32 addr, addr_ext; 557 u32 reg; 558 559 switch (pll_idx) { 560 case ASPEED_CLK_HPLL: 561 addr = (u32)(&scu->h_pll_param); 562 addr_ext = (u32)(&scu->h_pll_ext_param); 563 break; 564 case ASPEED_CLK_MPLL: 565 addr = (u32)(&scu->m_pll_param); 566 addr_ext = (u32)(&scu->m_pll_ext_param); 567 break; 568 case ASPEED_CLK_DPLL: 569 addr = (u32)(&scu->d_pll_param); 570 addr_ext = (u32)(&scu->d_pll_ext_param); 571 break; 572 case ASPEED_CLK_EPLL: 573 addr = (u32)(&scu->e_pll_param); 574 addr_ext = (u32)(&scu->e_pll_ext_param); 575 break; 576 default: 577 debug("unknown PLL index\n"); 578 return 1; 579 } 580 581 p_cfg->reg.b.bypass = 0; 582 p_cfg->reg.b.off = 1; 583 p_cfg->reg.b.reset = 1; 584 585 reg = readl(addr); 586 reg &= ~GENMASK(25, 0); 587 reg |= p_cfg->reg.w; 588 writel(reg, addr); 589 590 /* write extend parameter */ 591 writel(p_cfg->ext_reg, addr_ext); 592 udelay(100); 593 p_cfg->reg.b.off = 0; 594 p_cfg->reg.b.reset = 0; 595 reg &= ~GENMASK(25, 0); 596 reg |= p_cfg->reg.w; 597 writel(reg, addr); 598 599 /* polling PLL lock status */ 600 while (0 == (readl(addr_ext) & BIT(31))); 601 602 return 0; 603 } 604 static u32 ast2600_configure_ddr(struct ast2600_scu *scu, ulong rate) 605 { 606 struct ast2600_pll_desc mpll; 607 608 mpll.in = AST2600_CLK_IN; 609 mpll.out = rate; 610 if (ast2600_search_clock_config(&mpll) == false) { 611 printf("error!! unable to find valid DDR clock setting\n"); 612 return 0; 613 } 614 ast2600_configure_pll(scu, &(mpll.cfg), ASPEED_CLK_MPLL); 615 616 return ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL); 617 } 618 619 static ulong ast2600_clk_set_rate(struct clk *clk, ulong rate) 620 { 621 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 622 623 ulong new_rate; 624 switch (clk->id) { 625 case ASPEED_CLK_MPLL: 626 new_rate = ast2600_configure_ddr(priv->scu, rate); 627 break; 628 default: 629 return -ENOENT; 630 } 631 632 return new_rate; 633 } 634 635 #define SCU_CLKSTOP_MAC1 (20) 636 #define SCU_CLKSTOP_MAC2 (21) 637 #define SCU_CLKSTOP_MAC3 (20) 638 #define SCU_CLKSTOP_MAC4 (21) 639 640 static u32 ast2600_configure_mac12_clk(struct ast2600_scu *scu) 641 { 642 /* scu340[25:0]: 1G default delay */ 643 clrsetbits_le32(&scu->mac12_clk_delay, GENMASK(25, 0), 644 MAC_DEF_DELAY_1G); 645 646 /* set 100M/10M default delay */ 647 writel(MAC_DEF_DELAY_100M, &scu->mac12_clk_delay_100M); 648 writel(MAC_DEF_DELAY_10M, &scu->mac12_clk_delay_10M); 649 650 /* MAC AHB = HPLL / 6 */ 651 clrsetbits_le32(&scu->clk_sel1, GENMASK(18, 16), (0x2 << 16)); 652 653 return 0; 654 } 655 656 static u32 ast2600_configure_mac34_clk(struct ast2600_scu *scu) 657 { 658 /* 659 * scu350[31] RGMII 125M source: 0 = from IO pin 660 * scu350[25:0] MAC 1G delay 661 */ 662 clrsetbits_le32(&scu->mac34_clk_delay, (BIT(31) | GENMASK(25, 0)), 663 MAC34_DEF_DELAY_1G); 664 writel(MAC34_DEF_DELAY_100M, &scu->mac34_clk_delay_100M); 665 writel(MAC34_DEF_DELAY_10M, &scu->mac34_clk_delay_10M); 666 667 /* 668 * clock source seletion and divider 669 * scu310[26:24] : MAC AHB bus clock = HCLK / 2 670 * scu310[18:16] : RMII 50M = HCLK_200M / 4 671 */ 672 clrsetbits_le32(&scu->clk_sel4, (GENMASK(26, 24) | GENMASK(18, 16)), 673 ((0x0 << 24) | (0x3 << 16))); 674 675 /* 676 * set driving strength 677 * scu458[3:2] : MAC4 driving strength 678 * scu458[1:0] : MAC3 driving strength 679 */ 680 clrsetbits_le32(&scu->pinmux_ctrl16, GENMASK(3, 0), 681 (0x3 << 2) | (0x3 << 0)); 682 683 return 0; 684 } 685 686 /** 687 * ast2600 RGMII clock source tree 688 * 125M from external PAD -------->|\ 689 * HPLL -->|\ | |---->RGMII 125M for MAC#1 & MAC#2 690 * | |---->| divider |---->|/ + 691 * EPLL -->|/ | 692 * | 693 * +---------<-----------|RGMIICK PAD output enable|<-------------+ 694 * | 695 * +--------------------------->|\ 696 * | |----> RGMII 125M for MAC#3 & MAC#4 697 * HCLK 200M ---->|divider|---->|/ 698 * To simplify the control flow: 699 * 1. RGMII 1/2 always use EPLL as the internal clock source 700 * 2. RGMII 3/4 always use RGMIICK pad as the RGMII 125M source 701 * 125M from external PAD -------->|\ 702 * | |---->RGMII 125M for MAC#1 & MAC#2 703 * EPLL---->| divider |--->|/ + 704 * | 705 * +<--------------------|RGMIICK PAD output enable|<-------------+ 706 * | 707 * +--------------------------->RGMII 125M for MAC#3 & MAC#4 708 */ 709 #define RGMIICK_SRC_PAD 0 710 #define RGMIICK_SRC_EPLL 1 /* recommended */ 711 #define RGMIICK_SRC_HPLL 2 712 713 #define RGMIICK_DIV2 1 714 #define RGMIICK_DIV3 2 715 #define RGMIICK_DIV4 3 716 #define RGMIICK_DIV5 4 717 #define RGMIICK_DIV6 5 718 #define RGMIICK_DIV7 6 719 #define RGMIICK_DIV8 7 /* recommended */ 720 721 #define RMIICK_DIV4 0 722 #define RMIICK_DIV8 1 723 #define RMIICK_DIV12 2 724 #define RMIICK_DIV16 3 725 #define RMIICK_DIV20 4 /* recommended */ 726 #define RMIICK_DIV24 5 727 #define RMIICK_DIV28 6 728 #define RMIICK_DIV32 7 729 730 struct ast2600_mac_clk_div { 731 u32 src; /* 0=external PAD, 1=internal PLL */ 732 u32 fin; /* divider input speed */ 733 u32 n; /* 0=div2, 1=div2, 2=div3, 3=div4,...,7=div8 */ 734 u32 fout; /* fout = fin / n */ 735 }; 736 737 struct ast2600_mac_clk_div rgmii_clk_defconfig = { 738 .src = ASPEED_CLK_EPLL, 739 .fin = 1000000000, 740 .n = RGMIICK_DIV8, 741 .fout = 125000000, 742 }; 743 744 struct ast2600_mac_clk_div rmii_clk_defconfig = { 745 .src = ASPEED_CLK_EPLL, 746 .fin = 1000000000, 747 .n = RMIICK_DIV20, 748 .fout = 50000000, 749 }; 750 static void ast2600_init_mac_pll(struct ast2600_scu *p_scu, 751 struct ast2600_mac_clk_div *p_cfg) 752 { 753 struct ast2600_pll_desc pll; 754 755 pll.in = AST2600_CLK_IN; 756 pll.out = p_cfg->fin; 757 if (false == ast2600_search_clock_config(&pll)) { 758 printf("error!! unable to find valid ETHNET MAC clock " 759 "setting\n"); 760 debug("%s: pll cfg = 0x%08x 0x%08x\n", __func__, 761 pll.cfg.reg.w, pll.cfg.ext_reg); 762 debug("%s: pll cfg = %02x %02x %02x\n", __func__, 763 pll.cfg.reg.b.m, pll.cfg.reg.b.n, pll.cfg.reg.b.p); 764 return; 765 } 766 ast2600_configure_pll(p_scu, &(pll.cfg), p_cfg->src); 767 } 768 769 static void ast2600_init_rgmii_clk(struct ast2600_scu *p_scu, 770 struct ast2600_mac_clk_div *p_cfg) 771 { 772 u32 reg_304 = readl(&p_scu->clk_sel2); 773 u32 reg_340 = readl(&p_scu->mac12_clk_delay); 774 u32 reg_350 = readl(&p_scu->mac34_clk_delay); 775 776 reg_340 &= ~GENMASK(31, 29); 777 /* scu340[28]: RGMIICK PAD output enable (to MAC 3/4) */ 778 reg_340 |= BIT(28); 779 if ((p_cfg->src == ASPEED_CLK_EPLL) || 780 (p_cfg->src == ASPEED_CLK_HPLL)) { 781 /* 782 * re-init PLL if the current PLL output frequency doesn't match 783 * the divider setting 784 */ 785 if (p_cfg->fin != ast2600_get_pll_rate(p_scu, p_cfg->src)) { 786 ast2600_init_mac_pll(p_scu, p_cfg); 787 } 788 /* scu340[31]: select RGMII 125M from internal source */ 789 reg_340 |= BIT(31); 790 } 791 792 reg_304 &= ~GENMASK(23, 20); 793 794 /* set clock divider */ 795 reg_304 |= (p_cfg->n & 0x7) << 20; 796 797 /* select internal clock source */ 798 if (ASPEED_CLK_HPLL == p_cfg->src) { 799 reg_304 |= BIT(23); 800 } 801 802 /* RGMII 3/4 clock source select */ 803 reg_350 &= ~BIT(31); 804 805 writel(reg_304, &p_scu->clk_sel2); 806 writel(reg_340, &p_scu->mac12_clk_delay); 807 writel(reg_350, &p_scu->mac34_clk_delay); 808 } 809 810 /** 811 * ast2600 RMII/NCSI clock source tree 812 * HPLL -->|\ 813 * | |---->| divider |----> RMII 50M for MAC#1 & MAC#2 814 * EPLL -->|/ 815 * HCLK(SCLICLK)---->| divider |----> RMII 50M for MAC#3 & MAC#4 816 */ 817 static void ast2600_init_rmii_clk(struct ast2600_scu *p_scu, 818 struct ast2600_mac_clk_div *p_cfg) 819 { 820 u32 reg_304; 821 u32 reg_310; 822 823 if ((p_cfg->src == ASPEED_CLK_EPLL) || 824 (p_cfg->src == ASPEED_CLK_HPLL)) { 825 /* 826 * re-init PLL if the current PLL output frequency doesn't match 827 * the divider setting 828 */ 829 if (p_cfg->fin != ast2600_get_pll_rate(p_scu, p_cfg->src)) { 830 ast2600_init_mac_pll(p_scu, p_cfg); 831 } 832 } 833 834 reg_304 = readl(&p_scu->clk_sel2); 835 reg_310 = readl(&p_scu->clk_sel4); 836 837 reg_304 &= ~GENMASK(19, 16); 838 839 /* set RMII 1/2 clock divider */ 840 reg_304 |= (p_cfg->n & 0x7) << 16; 841 842 /* RMII clock source selection */ 843 if (ASPEED_CLK_HPLL == p_cfg->src) { 844 reg_304 |= BIT(19); 845 } 846 847 /* set RMII 3/4 clock divider */ 848 reg_310 &= ~GENMASK(18, 16); 849 reg_310 |= (0x3 << 16); 850 851 writel(reg_304, &p_scu->clk_sel2); 852 writel(reg_310, &p_scu->clk_sel4); 853 } 854 855 static u32 ast2600_configure_mac(struct ast2600_scu *scu, int index) 856 { 857 u32 reset_bit; 858 u32 clkstop_bit; 859 860 switch (index) { 861 case 1: 862 reset_bit = BIT(ASPEED_RESET_MAC1); 863 clkstop_bit = BIT(SCU_CLKSTOP_MAC1); 864 writel(reset_bit, &scu->sysreset_ctrl1); 865 udelay(100); 866 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 867 mdelay(10); 868 writel(reset_bit, &scu->sysreset_clr_ctrl1); 869 break; 870 case 2: 871 reset_bit = BIT(ASPEED_RESET_MAC2); 872 clkstop_bit = BIT(SCU_CLKSTOP_MAC2); 873 writel(reset_bit, &scu->sysreset_ctrl1); 874 udelay(100); 875 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 876 mdelay(10); 877 writel(reset_bit, &scu->sysreset_clr_ctrl1); 878 break; 879 case 3: 880 reset_bit = BIT(ASPEED_RESET_MAC3 - 32); 881 clkstop_bit = BIT(SCU_CLKSTOP_MAC3); 882 writel(reset_bit, &scu->sysreset_ctrl2); 883 udelay(100); 884 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 885 mdelay(10); 886 writel(reset_bit, &scu->sysreset_clr_ctrl2); 887 break; 888 case 4: 889 reset_bit = BIT(ASPEED_RESET_MAC4 - 32); 890 clkstop_bit = BIT(SCU_CLKSTOP_MAC4); 891 writel(reset_bit, &scu->sysreset_ctrl2); 892 udelay(100); 893 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 894 mdelay(10); 895 writel(reset_bit, &scu->sysreset_clr_ctrl2); 896 break; 897 default: 898 return -EINVAL; 899 } 900 901 return 0; 902 } 903 904 #define SCU_CLK_ECC_RSA_FROM_HPLL_CLK BIT(19) 905 #define SCU_CLK_ECC_RSA_CLK_MASK GENMASK(27, 26) 906 #define SCU_CLK_ECC_RSA_CLK_DIV(x) (x << 26) 907 static void ast2600_configure_rsa_ecc_clk(struct ast2600_scu *scu) 908 { 909 u32 clk_sel = readl(&scu->clk_sel1); 910 911 /* Configure RSA clock = HPLL/3 */ 912 clk_sel |= SCU_CLK_ECC_RSA_FROM_HPLL_CLK; 913 clk_sel &= ~SCU_CLK_ECC_RSA_CLK_MASK; 914 clk_sel |= SCU_CLK_ECC_RSA_CLK_DIV(2); 915 916 writel(clk_sel, &scu->clk_sel1); 917 } 918 919 #define SCU_CLKSTOP_SDIO 4 920 static ulong ast2600_enable_sdclk(struct ast2600_scu *scu) 921 { 922 u32 reset_bit; 923 u32 clkstop_bit; 924 925 reset_bit = BIT(ASPEED_RESET_SD - 32); 926 clkstop_bit = BIT(SCU_CLKSTOP_SDIO); 927 928 writel(reset_bit, &scu->sysreset_ctrl2); 929 930 udelay(100); 931 //enable clk 932 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 933 mdelay(10); 934 writel(reset_bit, &scu->sysreset_clr_ctrl2); 935 936 return 0; 937 } 938 939 #define SCU_CLKSTOP_EXTSD 31 940 #define SCU_CLK_SD_MASK (0x7 << 28) 941 #define SCU_CLK_SD_DIV(x) (x << 28) 942 #define SCU_CLK_SD_FROM_APLL_CLK BIT(8) 943 944 static ulong ast2600_enable_extsdclk(struct ast2600_scu *scu) 945 { 946 u32 clk_sel = readl(&scu->clk_sel4); 947 u32 enableclk_bit; 948 u32 rate = 0; 949 u32 div = 0; 950 int i = 0; 951 952 enableclk_bit = BIT(SCU_CLKSTOP_EXTSD); 953 954 /* ast2600 sd controller max clk is 200Mhz : 955 * use apll for clock source 800/4 = 200 : controller max is 200mhz 956 */ 957 rate = ast2600_get_apll_rate(scu); 958 for (i = 0; i < 8; i++) { 959 div = (i + 1) * 2; 960 if ((rate / div) <= 200000000) 961 break; 962 } 963 clk_sel &= ~SCU_CLK_SD_MASK; 964 clk_sel |= SCU_CLK_SD_DIV(i) | SCU_CLK_SD_FROM_APLL_CLK; 965 writel(clk_sel, &scu->clk_sel4); 966 967 //enable clk 968 setbits_le32(&scu->clk_sel4, enableclk_bit); 969 970 return 0; 971 } 972 973 #define SCU_CLKSTOP_EMMC 27 974 static ulong ast2600_enable_emmcclk(struct ast2600_scu *scu) 975 { 976 u32 reset_bit; 977 u32 clkstop_bit; 978 979 reset_bit = BIT(ASPEED_RESET_EMMC); 980 clkstop_bit = BIT(SCU_CLKSTOP_EMMC); 981 982 writel(reset_bit, &scu->sysreset_ctrl1); 983 udelay(100); 984 //enable clk 985 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 986 mdelay(10); 987 writel(reset_bit, &scu->sysreset_clr_ctrl1); 988 989 return 0; 990 } 991 992 #define SCU_CLKSTOP_EXTEMMC 15 993 #define SCU_CLK_EMMC_MASK (0x7 << 12) 994 #define SCU_CLK_EMMC_DIV(x) (x << 12) 995 #define SCU_CLK_EMMC_FROM_MPLL_CLK BIT(11) 996 997 static ulong ast2600_enable_extemmcclk(struct ast2600_scu *scu) 998 { 999 u32 revision_id = readl(&scu->chip_id1); 1000 u32 clk_sel = readl(&scu->clk_sel1); 1001 u32 enableclk_bit; 1002 u32 rate = 0; 1003 u32 div = 0; 1004 int i = 0; 1005 1006 enableclk_bit = BIT(SCU_CLKSTOP_EXTEMMC); 1007 1008 //ast2600 eMMC controller max clk is 200Mhz 1009 1010 /* HPll->1/2-> 1011 * \ 1012 * ->SCU300[11]->SCU300[14:12][1/N]->EMMC12C[15:8][1/N]-> eMMC clk 1013 * / 1014 * MPLL------> 1015 */ 1016 if (((revision_id & CHIP_REVISION_ID) >> 16)) { 1017 //AST2600A1 : use mpll to be clk source 1018 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL); 1019 for (i = 0; i < 8; i++) { 1020 div = (i + 1) * 2; 1021 if ((rate / div) <= 200000000) 1022 break; 1023 } 1024 1025 clk_sel &= ~SCU_CLK_EMMC_MASK; 1026 clk_sel |= SCU_CLK_EMMC_DIV(i) | SCU_CLK_EMMC_FROM_MPLL_CLK; 1027 writel(clk_sel, &scu->clk_sel1); 1028 1029 } else { 1030 //AST2600A0 : use hpll to be clk source 1031 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 1032 1033 for (i = 0; i < 8; i++) { 1034 div = (i + 1) * 4; 1035 if ((rate / div) <= 200000000) 1036 break; 1037 } 1038 1039 clk_sel &= ~SCU_CLK_EMMC_MASK; 1040 clk_sel |= SCU_CLK_EMMC_DIV(i); 1041 writel(clk_sel, &scu->clk_sel1); 1042 } 1043 setbits_le32(&scu->clk_sel1, enableclk_bit); 1044 1045 return 0; 1046 } 1047 1048 #define SCU_CLKSTOP_FSICLK 30 1049 1050 static ulong ast2600_enable_fsiclk(struct ast2600_scu *scu) 1051 { 1052 u32 reset_bit; 1053 u32 clkstop_bit; 1054 1055 reset_bit = BIT(ASPEED_RESET_FSI % 32); 1056 clkstop_bit = BIT(SCU_CLKSTOP_FSICLK); 1057 1058 /* The FSI clock is shared between masters. If it's already on 1059 * don't touch it, as that will reset the existing master. */ 1060 if (!(readl(&scu->clk_stop_ctrl2) & clkstop_bit)) { 1061 debug("%s: already running, not touching it\n", __func__); 1062 return 0; 1063 } 1064 1065 writel(reset_bit, &scu->sysreset_ctrl2); 1066 udelay(100); 1067 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 1068 mdelay(10); 1069 writel(reset_bit, &scu->sysreset_clr_ctrl2); 1070 1071 return 0; 1072 } 1073 1074 static ulong ast2600_enable_usbahclk(struct ast2600_scu *scu) 1075 { 1076 u32 reset_bit; 1077 u32 clkstop_bit; 1078 1079 reset_bit = BIT(ASPEED_RESET_EHCI_P1); 1080 clkstop_bit = BIT(14); 1081 1082 writel(reset_bit, &scu->sysreset_ctrl1); 1083 udelay(100); 1084 writel(clkstop_bit, &scu->clk_stop_ctrl1); 1085 mdelay(20); 1086 writel(reset_bit, &scu->sysreset_clr_ctrl1); 1087 1088 return 0; 1089 } 1090 1091 static ulong ast2600_enable_usbbhclk(struct ast2600_scu *scu) 1092 { 1093 u32 reset_bit; 1094 u32 clkstop_bit; 1095 1096 reset_bit = BIT(ASPEED_RESET_EHCI_P2); 1097 clkstop_bit = BIT(7); 1098 1099 writel(reset_bit, &scu->sysreset_ctrl1); 1100 udelay(100); 1101 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 1102 mdelay(20); 1103 1104 writel(reset_bit, &scu->sysreset_clr_ctrl1); 1105 1106 return 0; 1107 } 1108 1109 static int ast2600_clk_enable(struct clk *clk) 1110 { 1111 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 1112 1113 switch (clk->id) { 1114 case ASPEED_CLK_GATE_MAC1CLK: 1115 ast2600_configure_mac(priv->scu, 1); 1116 break; 1117 case ASPEED_CLK_GATE_MAC2CLK: 1118 ast2600_configure_mac(priv->scu, 2); 1119 break; 1120 case ASPEED_CLK_GATE_MAC3CLK: 1121 ast2600_configure_mac(priv->scu, 3); 1122 break; 1123 case ASPEED_CLK_GATE_MAC4CLK: 1124 ast2600_configure_mac(priv->scu, 4); 1125 break; 1126 case ASPEED_CLK_GATE_SDCLK: 1127 ast2600_enable_sdclk(priv->scu); 1128 break; 1129 case ASPEED_CLK_GATE_SDEXTCLK: 1130 ast2600_enable_extsdclk(priv->scu); 1131 break; 1132 case ASPEED_CLK_GATE_EMMCCLK: 1133 ast2600_enable_emmcclk(priv->scu); 1134 break; 1135 case ASPEED_CLK_GATE_EMMCEXTCLK: 1136 ast2600_enable_extemmcclk(priv->scu); 1137 break; 1138 case ASPEED_CLK_GATE_FSICLK: 1139 ast2600_enable_fsiclk(priv->scu); 1140 break; 1141 case ASPEED_CLK_GATE_USBPORT1CLK: 1142 ast2600_enable_usbahclk(priv->scu); 1143 break; 1144 case ASPEED_CLK_GATE_USBPORT2CLK: 1145 ast2600_enable_usbbhclk(priv->scu); 1146 break; 1147 default: 1148 pr_debug("can't enable clk \n"); 1149 return -ENOENT; 1150 break; 1151 } 1152 1153 return 0; 1154 } 1155 1156 struct clk_ops ast2600_clk_ops = { 1157 .get_rate = ast2600_clk_get_rate, 1158 .set_rate = ast2600_clk_set_rate, 1159 .enable = ast2600_clk_enable, 1160 }; 1161 1162 static int ast2600_clk_probe(struct udevice *dev) 1163 { 1164 struct ast2600_clk_priv *priv = dev_get_priv(dev); 1165 u32 uart_clk_source; 1166 1167 priv->scu = devfdt_get_addr_ptr(dev); 1168 if (IS_ERR(priv->scu)) 1169 return PTR_ERR(priv->scu); 1170 1171 uart_clk_source = dev_read_u32_default(dev, "uart-clk-source", 0x0); 1172 1173 if (uart_clk_source) { 1174 if (uart_clk_source & GENMASK(5, 0)) 1175 setbits_le32(&priv->scu->clk_sel4, 1176 uart_clk_source & GENMASK(5, 0)); 1177 if (uart_clk_source & GENMASK(12, 6)) 1178 setbits_le32(&priv->scu->clk_sel5, 1179 uart_clk_source & GENMASK(12, 6)); 1180 } 1181 1182 ast2600_init_rgmii_clk(priv->scu, &rgmii_clk_defconfig); 1183 ast2600_init_rmii_clk(priv->scu, &rmii_clk_defconfig); 1184 ast2600_configure_mac12_clk(priv->scu); 1185 ast2600_configure_mac34_clk(priv->scu); 1186 ast2600_configure_rsa_ecc_clk(priv->scu); 1187 1188 return 0; 1189 } 1190 1191 static int ast2600_clk_bind(struct udevice *dev) 1192 { 1193 int ret; 1194 1195 /* The reset driver does not have a device node, so bind it here */ 1196 ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev); 1197 if (ret) 1198 debug("Warning: No reset driver: ret=%d\n", ret); 1199 1200 return 0; 1201 } 1202 1203 #if CONFIG_IS_ENABLED(CMD_CLK) 1204 struct aspeed_clks { 1205 ulong id; 1206 const char *name; 1207 }; 1208 1209 static struct aspeed_clks aspeed_clk_names[] = { 1210 { ASPEED_CLK_HPLL, "hpll" }, { ASPEED_CLK_MPLL, "mpll" }, 1211 { ASPEED_CLK_APLL, "apll" }, { ASPEED_CLK_EPLL, "epll" }, 1212 { ASPEED_CLK_DPLL, "dpll" }, { ASPEED_CLK_AHB, "hclk" }, 1213 { ASPEED_CLK_APB1, "pclk1" }, { ASPEED_CLK_APB2, "pclk2" }, 1214 { ASPEED_CLK_BCLK, "bclk" }, { ASPEED_CLK_UARTX, "uxclk" }, 1215 { ASPEED_CLK_HUARTX, "huxclk" }, 1216 }; 1217 1218 int soc_clk_dump(void) 1219 { 1220 struct udevice *dev; 1221 struct clk clk; 1222 unsigned long rate; 1223 int i, ret; 1224 1225 ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu), 1226 &dev); 1227 if (ret) 1228 return ret; 1229 1230 printf("Clk\t\tHz\n"); 1231 1232 for (i = 0; i < ARRAY_SIZE(aspeed_clk_names); i++) { 1233 clk.id = aspeed_clk_names[i].id; 1234 ret = clk_request(dev, &clk); 1235 if (ret < 0) { 1236 debug("%s clk_request() failed: %d\n", __func__, ret); 1237 continue; 1238 } 1239 1240 ret = clk_get_rate(&clk); 1241 rate = ret; 1242 1243 clk_free(&clk); 1244 1245 if (ret == -ENOTSUPP) { 1246 printf("clk ID %lu not supported yet\n", 1247 aspeed_clk_names[i].id); 1248 continue; 1249 } 1250 if (ret < 0) { 1251 printf("%s %lu: get_rate err: %d\n", __func__, 1252 aspeed_clk_names[i].id, ret); 1253 continue; 1254 } 1255 1256 printf("%s(%3lu):\t%lu\n", aspeed_clk_names[i].name, 1257 aspeed_clk_names[i].id, rate); 1258 } 1259 1260 return 0; 1261 } 1262 #endif 1263 1264 static const struct udevice_id ast2600_clk_ids[] = { 1265 { 1266 .compatible = "aspeed,ast2600-scu", 1267 }, 1268 {} 1269 }; 1270 1271 U_BOOT_DRIVER(aspeed_scu) = { 1272 .name = "aspeed_scu", 1273 .id = UCLASS_CLK, 1274 .of_match = ast2600_clk_ids, 1275 .priv_auto_alloc_size = sizeof(struct ast2600_clk_priv), 1276 .ops = &ast2600_clk_ops, 1277 .bind = ast2600_clk_bind, 1278 .probe = ast2600_clk_probe, 1279 }; 1280