1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 */ 5 6 #include <common.h> 7 #include <clk-uclass.h> 8 #include <dm.h> 9 #include <asm/io.h> 10 #include <dm/lists.h> 11 #include <asm/arch/scu_ast2600.h> 12 #include <dt-bindings/clock/ast2600-clock.h> 13 #include <dt-bindings/reset/ast2600-reset.h> 14 15 /* 16 * MAC Clock Delay settings 17 */ 18 #define RGMII_TXCLK_ODLY 8 19 #define RMII_RXCLK_IDLY 2 20 21 #define MAC_DEF_DELAY_1G 0x0041b75d 22 #define MAC_DEF_DELAY_100M 0x00417410 23 #define MAC_DEF_DELAY_10M 0x00417410 24 25 #define MAC34_DEF_DELAY_1G 0x0010438a 26 #define MAC34_DEF_DELAY_100M 0x00104208 27 #define MAC34_DEF_DELAY_10M 0x00104208 28 29 /* 30 * TGMII Clock Duty constants, taken from Aspeed SDK 31 */ 32 #define RGMII2_TXCK_DUTY 0x66 33 #define RGMII1_TXCK_DUTY 0x64 34 #define D2PLL_DEFAULT_RATE (250 * 1000 * 1000) 35 #define CHIP_REVISION_ID GENMASK(23, 16) 36 37 DECLARE_GLOBAL_DATA_PTR; 38 39 /* 40 * Clock divider/multiplier configuration struct. 41 * For H-PLL and M-PLL the formula is 42 * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1) 43 * M - Numerator 44 * N - Denumerator 45 * P - Post Divider 46 * They have the same layout in their control register. 47 * 48 * D-PLL and D2-PLL have extra divider (OD + 1), which is not 49 * yet needed and ignored by clock configurations. 50 */ 51 union ast2600_pll_reg { 52 unsigned int w; 53 struct { 54 unsigned int m : 13; /* bit[12:0] */ 55 unsigned int n : 6; /* bit[18:13] */ 56 unsigned int p : 4; /* bit[22:19] */ 57 unsigned int off : 1; /* bit[23] */ 58 unsigned int bypass : 1; /* bit[24] */ 59 unsigned int reset : 1; /* bit[25] */ 60 unsigned int reserved : 6; /* bit[31:26] */ 61 } b; 62 }; 63 64 struct ast2600_pll_cfg { 65 union ast2600_pll_reg reg; 66 unsigned int ext_reg; 67 }; 68 69 struct ast2600_pll_desc { 70 u32 in; 71 u32 out; 72 struct ast2600_pll_cfg cfg; 73 }; 74 75 static const struct ast2600_pll_desc ast2600_pll_lookup[] = { 76 { 77 .in = AST2600_CLK_IN, 78 .out = 400000000, 79 .cfg.reg.b.m = 95, 80 .cfg.reg.b.n = 2, 81 .cfg.reg.b.p = 1, 82 .cfg.ext_reg = 0x31, 83 }, 84 { .in = AST2600_CLK_IN, 85 .out = 200000000, 86 .cfg.reg.b.m = 127, 87 .cfg.reg.b.n = 0, 88 .cfg.reg.b.p = 15, 89 .cfg.ext_reg = 0x3f }, 90 { .in = AST2600_CLK_IN, 91 .out = 334000000, 92 .cfg.reg.b.m = 667, 93 .cfg.reg.b.n = 4, 94 .cfg.reg.b.p = 9, 95 .cfg.ext_reg = 0x14d }, 96 { .in = AST2600_CLK_IN, 97 .out = 1000000000, 98 .cfg.reg.b.m = 119, 99 .cfg.reg.b.n = 2, 100 .cfg.reg.b.p = 0, 101 .cfg.ext_reg = 0x3d }, 102 { .in = AST2600_CLK_IN, 103 .out = 50000000, 104 .cfg.reg.b.m = 95, 105 .cfg.reg.b.n = 2, 106 .cfg.reg.b.p = 15, 107 .cfg.ext_reg = 0x31 }, 108 }; 109 110 extern u32 ast2600_get_pll_rate(struct ast2600_scu *scu, int pll_idx) 111 { 112 u32 clkin = AST2600_CLK_IN; 113 u32 pll_reg = 0; 114 unsigned int mult, div = 1; 115 116 switch (pll_idx) { 117 case ASPEED_CLK_HPLL: 118 pll_reg = readl(&scu->h_pll_param); 119 break; 120 case ASPEED_CLK_MPLL: 121 pll_reg = readl(&scu->m_pll_param); 122 break; 123 case ASPEED_CLK_DPLL: 124 pll_reg = readl(&scu->d_pll_param); 125 break; 126 case ASPEED_CLK_EPLL: 127 pll_reg = readl(&scu->e_pll_param); 128 break; 129 } 130 if (pll_reg & BIT(24)) { 131 /* Pass through mode */ 132 mult = div = 1; 133 } else { 134 /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) */ 135 union ast2600_pll_reg reg; 136 reg.w = pll_reg; 137 if (pll_idx == ASPEED_CLK_HPLL) { 138 /* 139 HPLL Numerator (M) = fix 0x5F when SCU500[10]=1 140 fix 0xBF when SCU500[10]=0 and SCU500[8]=1 141 SCU200[12:0] (default 0x8F) when SCU510[10]=0 and SCU510[8]=0 142 HPLL Denumerator (N) = SCU200[18:13] (default 0x2) 143 HPLL Divider (P) = SCU200[22:19] (default 0x0) 144 HPLL Bandwidth Adj (NB) = fix 0x2F when SCU500[10]=1 145 fix 0x5F when SCU500[10]=0 and SCU500[8]=1 146 SCU204[11:0] (default 0x31) when SCU500[10]=0 and SCU500[8]=0 147 */ 148 u32 hwstrap1 = readl(&scu->hwstrap1.hwstrap); 149 if (hwstrap1 & BIT(10)) 150 reg.b.m = 0x5F; 151 else { 152 if (hwstrap1 & BIT(8)) 153 reg.b.m = 0xBF; 154 /* Otherwise keep default 0x8F */ 155 } 156 } 157 mult = (reg.b.m + 1) / (reg.b.n + 1); 158 div = (reg.b.p + 1); 159 } 160 161 return ((clkin * mult) / div); 162 } 163 164 extern u32 ast2600_get_apll_rate(struct ast2600_scu *scu) 165 { 166 u32 hw_rev = readl(&scu->chip_id1); 167 u32 clkin = AST2600_CLK_IN; 168 u32 apll_reg = readl(&scu->a_pll_param); 169 unsigned int mult, div = 1; 170 171 if (((hw_rev & CHIP_REVISION_ID) >> 16) >= 3) { 172 //after A2 version 173 if (apll_reg & BIT(24)) { 174 /* Pass through mode */ 175 mult = div = 1; 176 } else { 177 /* F = 25Mhz * [(m + 1) / (n + 1)] / (p + 1) */ 178 u32 m = apll_reg & 0x1fff; 179 u32 n = (apll_reg >> 13) & 0x3f; 180 u32 p = (apll_reg >> 19) & 0xf; 181 182 mult = (m + 1); 183 div = (n + 1) * (p + 1); 184 } 185 186 } else { 187 if (apll_reg & BIT(20)) { 188 /* Pass through mode */ 189 mult = div = 1; 190 } else { 191 /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */ 192 u32 m = (apll_reg >> 5) & 0x3f; 193 u32 od = (apll_reg >> 4) & 0x1; 194 u32 n = apll_reg & 0xf; 195 196 mult = (2 - od) * (m + 2); 197 div = n + 1; 198 } 199 } 200 201 return ((clkin * mult) / div); 202 } 203 204 static u32 ast2600_a0_axi_ahb_div_table[] = { 205 2, 206 2, 207 3, 208 4, 209 }; 210 211 static u32 ast2600_a1_axi_ahb_div0_table[] = { 212 3, 213 2, 214 3, 215 4, 216 }; 217 218 static u32 ast2600_a1_axi_ahb_div1_table[] = { 219 3, 220 4, 221 6, 222 8, 223 }; 224 225 static u32 ast2600_a1_axi_ahb_default_table[] = { 226 3, 4, 3, 4, 2, 2, 2, 2, 227 }; 228 229 static u32 ast2600_get_hclk(struct ast2600_scu *scu) 230 { 231 u32 hw_rev = readl(&scu->chip_id1); 232 u32 hwstrap1 = readl(&scu->hwstrap1.hwstrap); 233 u32 axi_div = 1; 234 u32 ahb_div = 0; 235 u32 rate = 0; 236 237 if ((hw_rev & CHIP_REVISION_ID) >> 16) { 238 //After A0 239 if (hwstrap1 & BIT(16)) { 240 ast2600_a1_axi_ahb_div1_table[0] = 241 ast2600_a1_axi_ahb_default_table[(hwstrap1 >> 8) & 242 0x3]; 243 axi_div = 1; 244 ahb_div = 245 ast2600_a1_axi_ahb_div1_table[(hwstrap1 >> 11) & 246 0x3]; 247 } else { 248 ast2600_a1_axi_ahb_div0_table[0] = 249 ast2600_a1_axi_ahb_default_table[(hwstrap1 >> 8) & 250 0x3]; 251 axi_div = 2; 252 ahb_div = 253 ast2600_a1_axi_ahb_div0_table[(hwstrap1 >> 11) & 254 0x3]; 255 } 256 } else { 257 //A0 : fix axi = hpll / 2 258 axi_div = 2; 259 ahb_div = ast2600_a0_axi_ahb_div_table[(hwstrap1 >> 11) & 0x3]; 260 } 261 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 262 263 return (rate / axi_div / ahb_div); 264 } 265 266 static u32 ast2600_get_bclk_rate(struct ast2600_scu *scu) 267 { 268 u32 rate; 269 u32 bclk_sel = (readl(&scu->clk_sel1) >> 20) & 0x7; 270 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 271 272 return (rate / ((bclk_sel + 1) * 4)); 273 } 274 275 static u32 ast2600_hpll_pclk1_div_table[] = { 276 4, 8, 12, 16, 20, 24, 28, 32, 277 }; 278 279 static u32 ast2600_hpll_pclk2_div_table[] = { 280 2, 4, 6, 8, 10, 12, 14, 16, 281 }; 282 283 static u32 ast2600_get_pclk1(struct ast2600_scu *scu) 284 { 285 u32 clk_sel1 = readl(&scu->clk_sel1); 286 u32 apb_div = ast2600_hpll_pclk1_div_table[((clk_sel1 >> 23) & 0x7)]; 287 u32 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 288 289 return (rate / apb_div); 290 } 291 292 static u32 ast2600_get_pclk2(struct ast2600_scu *scu) 293 { 294 u32 clk_sel4 = readl(&scu->clk_sel4); 295 u32 apb_div = ast2600_hpll_pclk2_div_table[((clk_sel4 >> 9) & 0x7)]; 296 u32 rate = ast2600_get_hclk(scu); 297 298 return (rate / apb_div); 299 } 300 301 static u32 ast2600_get_uxclk_in_rate(struct ast2600_scu *scu) 302 { 303 u32 clk_in = 0; 304 u32 uxclk_sel = readl(&scu->clk_sel5); 305 306 uxclk_sel &= 0x3; 307 switch (uxclk_sel) { 308 case 0: 309 clk_in = ast2600_get_apll_rate(scu) / 4; 310 break; 311 case 1: 312 clk_in = ast2600_get_apll_rate(scu) / 2; 313 break; 314 case 2: 315 clk_in = ast2600_get_apll_rate(scu); 316 break; 317 case 3: 318 clk_in = ast2600_get_hclk(scu); 319 break; 320 } 321 322 return clk_in; 323 } 324 325 static u32 ast2600_get_huxclk_in_rate(struct ast2600_scu *scu) 326 { 327 u32 clk_in = 0; 328 u32 huclk_sel = readl(&scu->clk_sel5); 329 330 huclk_sel = ((huclk_sel >> 3) & 0x3); 331 switch (huclk_sel) { 332 case 0: 333 clk_in = ast2600_get_apll_rate(scu) / 4; 334 break; 335 case 1: 336 clk_in = ast2600_get_apll_rate(scu) / 2; 337 break; 338 case 2: 339 clk_in = ast2600_get_apll_rate(scu); 340 break; 341 case 3: 342 clk_in = ast2600_get_hclk(scu); 343 break; 344 } 345 346 return clk_in; 347 } 348 349 static u32 ast2600_get_uart_uxclk_rate(struct ast2600_scu *scu) 350 { 351 u32 clk_in = ast2600_get_uxclk_in_rate(scu); 352 u32 div_reg = readl(&scu->uart_24m_ref_uxclk); 353 unsigned int mult, div; 354 355 u32 n = (div_reg >> 8) & 0x3ff; 356 u32 r = div_reg & 0xff; 357 358 mult = r; 359 div = (n * 2); 360 return (clk_in * mult) / div; 361 } 362 363 static u32 ast2600_get_uart_huxclk_rate(struct ast2600_scu *scu) 364 { 365 u32 clk_in = ast2600_get_huxclk_in_rate(scu); 366 u32 div_reg = readl(&scu->uart_24m_ref_huxclk); 367 368 unsigned int mult, div; 369 370 u32 n = (div_reg >> 8) & 0x3ff; 371 u32 r = div_reg & 0xff; 372 373 mult = r; 374 div = (n * 2); 375 return (clk_in * mult) / div; 376 } 377 378 static u32 ast2600_get_sdio_clk_rate(struct ast2600_scu *scu) 379 { 380 u32 clkin = 0; 381 u32 clk_sel = readl(&scu->clk_sel4); 382 u32 div = (clk_sel >> 28) & 0x7; 383 384 if (clk_sel & BIT(8)) { 385 clkin = ast2600_get_apll_rate(scu); 386 } else { 387 clkin = ast2600_get_hclk(scu); 388 } 389 div = (div + 1) << 1; 390 391 return (clkin / div); 392 } 393 394 static u32 ast2600_get_emmc_clk_rate(struct ast2600_scu *scu) 395 { 396 u32 clkin = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 397 u32 clk_sel = readl(&scu->clk_sel1); 398 u32 div = (clk_sel >> 12) & 0x7; 399 400 div = (div + 1) << 2; 401 402 return (clkin / div); 403 } 404 405 static u32 ast2600_get_uart_clk_rate(struct ast2600_scu *scu, int uart_idx) 406 { 407 u32 uart_sel = readl(&scu->clk_sel4); 408 u32 uart_sel5 = readl(&scu->clk_sel5); 409 ulong uart_clk = 0; 410 411 switch (uart_idx) { 412 case 1: 413 case 2: 414 case 3: 415 case 4: 416 case 6: 417 if (uart_sel & BIT(uart_idx - 1)) 418 uart_clk = ast2600_get_uart_huxclk_rate(scu); 419 else 420 uart_clk = ast2600_get_uart_uxclk_rate(scu); 421 break; 422 case 5: //24mhz is come form usb phy 48Mhz 423 { 424 u8 uart5_clk_sel = 0; 425 //high bit 426 if (readl(&scu->misc_ctrl1) & BIT(12)) 427 uart5_clk_sel = 0x2; 428 else 429 uart5_clk_sel = 0x0; 430 431 if (readl(&scu->clk_sel2) & BIT(14)) 432 uart5_clk_sel |= 0x1; 433 434 switch (uart5_clk_sel) { 435 case 0: 436 uart_clk = 24000000; 437 break; 438 case 1: 439 uart_clk = 192000000; 440 break; 441 case 2: 442 uart_clk = 24000000 / 13; 443 break; 444 case 3: 445 uart_clk = 192000000 / 13; 446 break; 447 } 448 } break; 449 case 7: 450 case 8: 451 case 9: 452 case 10: 453 case 11: 454 case 12: 455 case 13: 456 if (uart_sel5 & BIT(uart_idx - 1)) 457 uart_clk = ast2600_get_uart_huxclk_rate(scu); 458 else 459 uart_clk = ast2600_get_uart_uxclk_rate(scu); 460 break; 461 } 462 463 return uart_clk; 464 } 465 466 static ulong ast2600_clk_get_rate(struct clk *clk) 467 { 468 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 469 ulong rate = 0; 470 471 switch (clk->id) { 472 case ASPEED_CLK_HPLL: 473 case ASPEED_CLK_EPLL: 474 case ASPEED_CLK_DPLL: 475 case ASPEED_CLK_MPLL: 476 rate = ast2600_get_pll_rate(priv->scu, clk->id); 477 break; 478 case ASPEED_CLK_AHB: 479 rate = ast2600_get_hclk(priv->scu); 480 break; 481 case ASPEED_CLK_APB1: 482 rate = ast2600_get_pclk1(priv->scu); 483 break; 484 case ASPEED_CLK_APB2: 485 rate = ast2600_get_pclk2(priv->scu); 486 break; 487 case ASPEED_CLK_APLL: 488 rate = ast2600_get_apll_rate(priv->scu); 489 break; 490 case ASPEED_CLK_GATE_UART1CLK: 491 rate = ast2600_get_uart_clk_rate(priv->scu, 1); 492 break; 493 case ASPEED_CLK_GATE_UART2CLK: 494 rate = ast2600_get_uart_clk_rate(priv->scu, 2); 495 break; 496 case ASPEED_CLK_GATE_UART3CLK: 497 rate = ast2600_get_uart_clk_rate(priv->scu, 3); 498 break; 499 case ASPEED_CLK_GATE_UART4CLK: 500 rate = ast2600_get_uart_clk_rate(priv->scu, 4); 501 break; 502 case ASPEED_CLK_GATE_UART5CLK: 503 rate = ast2600_get_uart_clk_rate(priv->scu, 5); 504 break; 505 case ASPEED_CLK_BCLK: 506 rate = ast2600_get_bclk_rate(priv->scu); 507 break; 508 case ASPEED_CLK_SDIO: 509 rate = ast2600_get_sdio_clk_rate(priv->scu); 510 break; 511 case ASPEED_CLK_EMMC: 512 rate = ast2600_get_emmc_clk_rate(priv->scu); 513 break; 514 case ASPEED_CLK_UARTX: 515 rate = ast2600_get_uart_uxclk_rate(priv->scu); 516 break; 517 case ASPEED_CLK_HUARTX: 518 rate = ast2600_get_uart_huxclk_rate(priv->scu); 519 break; 520 default: 521 pr_debug("can't get clk rate \n"); 522 return -ENOENT; 523 break; 524 } 525 526 return rate; 527 } 528 529 /** 530 * @brief lookup PLL divider config by input/output rate 531 * @param[in] *pll - PLL descriptor 532 * @return true - if PLL divider config is found, false - else 533 * 534 * The function caller shall fill "pll->in" and "pll->out", 535 * then this function will search the lookup table 536 * to find a valid PLL divider configuration. 537 */ 538 static bool ast2600_search_clock_config(struct ast2600_pll_desc *pll) 539 { 540 u32 i; 541 bool is_found = false; 542 543 for (i = 0; i < ARRAY_SIZE(ast2600_pll_lookup); i++) { 544 const struct ast2600_pll_desc *def_cfg = &ast2600_pll_lookup[i]; 545 if ((def_cfg->in == pll->in) && (def_cfg->out == pll->out)) { 546 is_found = true; 547 pll->cfg.reg.w = def_cfg->cfg.reg.w; 548 pll->cfg.ext_reg = def_cfg->cfg.ext_reg; 549 break; 550 } 551 } 552 return is_found; 553 } 554 static u32 ast2600_configure_pll(struct ast2600_scu *scu, 555 struct ast2600_pll_cfg *p_cfg, int pll_idx) 556 { 557 u32 addr, addr_ext; 558 u32 reg; 559 560 switch (pll_idx) { 561 case ASPEED_CLK_HPLL: 562 addr = (u32)(&scu->h_pll_param); 563 addr_ext = (u32)(&scu->h_pll_ext_param); 564 break; 565 case ASPEED_CLK_MPLL: 566 addr = (u32)(&scu->m_pll_param); 567 addr_ext = (u32)(&scu->m_pll_ext_param); 568 break; 569 case ASPEED_CLK_DPLL: 570 addr = (u32)(&scu->d_pll_param); 571 addr_ext = (u32)(&scu->d_pll_ext_param); 572 break; 573 case ASPEED_CLK_EPLL: 574 addr = (u32)(&scu->e_pll_param); 575 addr_ext = (u32)(&scu->e_pll_ext_param); 576 break; 577 default: 578 debug("unknown PLL index\n"); 579 return 1; 580 } 581 582 p_cfg->reg.b.bypass = 0; 583 p_cfg->reg.b.off = 1; 584 p_cfg->reg.b.reset = 1; 585 586 reg = readl(addr); 587 reg &= ~GENMASK(25, 0); 588 reg |= p_cfg->reg.w; 589 writel(reg, addr); 590 591 /* write extend parameter */ 592 writel(p_cfg->ext_reg, addr_ext); 593 udelay(100); 594 p_cfg->reg.b.off = 0; 595 p_cfg->reg.b.reset = 0; 596 reg &= ~GENMASK(25, 0); 597 reg |= p_cfg->reg.w; 598 writel(reg, addr); 599 600 /* polling PLL lock status */ 601 while (0 == (readl(addr_ext) & BIT(31))); 602 603 return 0; 604 } 605 static u32 ast2600_configure_ddr(struct ast2600_scu *scu, ulong rate) 606 { 607 struct ast2600_pll_desc mpll; 608 609 mpll.in = AST2600_CLK_IN; 610 mpll.out = rate; 611 if (false == ast2600_search_clock_config(&mpll)) { 612 printf("error!! unable to find valid DDR clock setting\n"); 613 return 0; 614 } 615 ast2600_configure_pll(scu, &(mpll.cfg), ASPEED_CLK_MPLL); 616 617 return ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL); 618 } 619 620 static ulong ast2600_clk_set_rate(struct clk *clk, ulong rate) 621 { 622 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 623 624 ulong new_rate; 625 switch (clk->id) { 626 case ASPEED_CLK_MPLL: 627 new_rate = ast2600_configure_ddr(priv->scu, rate); 628 break; 629 default: 630 return -ENOENT; 631 } 632 633 return new_rate; 634 } 635 636 #define SCU_CLKSTOP_MAC1 (20) 637 #define SCU_CLKSTOP_MAC2 (21) 638 #define SCU_CLKSTOP_MAC3 (20) 639 #define SCU_CLKSTOP_MAC4 (21) 640 641 static u32 ast2600_configure_mac12_clk(struct ast2600_scu *scu) 642 { 643 /* scu340[25:0]: 1G default delay */ 644 clrsetbits_le32(&scu->mac12_clk_delay, GENMASK(25, 0), 645 MAC_DEF_DELAY_1G); 646 647 /* set 100M/10M default delay */ 648 writel(MAC_DEF_DELAY_100M, &scu->mac12_clk_delay_100M); 649 writel(MAC_DEF_DELAY_10M, &scu->mac12_clk_delay_10M); 650 651 /* MAC AHB = HPLL / 6 */ 652 clrsetbits_le32(&scu->clk_sel1, GENMASK(18, 16), (0x2 << 16)); 653 654 return 0; 655 } 656 657 static u32 ast2600_configure_mac34_clk(struct ast2600_scu *scu) 658 { 659 /* 660 * scu350[31] RGMII 125M source: 0 = from IO pin 661 * scu350[25:0] MAC 1G delay 662 */ 663 clrsetbits_le32(&scu->mac34_clk_delay, (BIT(31) | GENMASK(25, 0)), 664 MAC34_DEF_DELAY_1G); 665 writel(MAC34_DEF_DELAY_100M, &scu->mac34_clk_delay_100M); 666 writel(MAC34_DEF_DELAY_10M, &scu->mac34_clk_delay_10M); 667 668 /* 669 * clock source seletion and divider 670 * scu310[26:24] : MAC AHB bus clock = HCLK / 2 671 * scu310[18:16] : RMII 50M = HCLK_200M / 4 672 */ 673 clrsetbits_le32(&scu->clk_sel4, (GENMASK(26, 24) | GENMASK(18, 16)), 674 ((0x0 << 24) | (0x3 << 16))); 675 676 /* 677 * set driving strength 678 * scu458[3:2] : MAC4 driving strength 679 * scu458[1:0] : MAC3 driving strength 680 */ 681 clrsetbits_le32(&scu->pinmux_ctrl16, GENMASK(3, 0), 682 (0x3 << 2) | (0x3 << 0)); 683 684 return 0; 685 } 686 687 /** 688 * ast2600 RGMII clock source tree 689 * 690 * 125M from external PAD -------->|\ 691 * HPLL -->|\ | |---->RGMII 125M for MAC#1 & MAC#2 692 * | |---->| divider |---->|/ + 693 * EPLL -->|/ | 694 * | 695 * +---------<-----------|RGMIICK PAD output enable|<-------------+ 696 * | 697 * +--------------------------->|\ 698 * | |----> RGMII 125M for MAC#3 & MAC#4 699 * HCLK 200M ---->|divider|---->|/ 700 * 701 * To simplify the control flow: 702 * 1. RGMII 1/2 always use EPLL as the internal clock source 703 * 2. RGMII 3/4 always use RGMIICK pad as the RGMII 125M source 704 * 705 * 125M from external PAD -------->|\ 706 * | |---->RGMII 125M for MAC#1 & MAC#2 707 * EPLL---->| divider |--->|/ + 708 * | 709 * +<--------------------|RGMIICK PAD output enable|<-------------+ 710 * | 711 * +--------------------------->RGMII 125M for MAC#3 & MAC#4 712 */ 713 #define RGMIICK_SRC_PAD 0 714 #define RGMIICK_SRC_EPLL 1 /* recommended */ 715 #define RGMIICK_SRC_HPLL 2 716 717 #define RGMIICK_DIV2 1 718 #define RGMIICK_DIV3 2 719 #define RGMIICK_DIV4 3 720 #define RGMIICK_DIV5 4 721 #define RGMIICK_DIV6 5 722 #define RGMIICK_DIV7 6 723 #define RGMIICK_DIV8 7 /* recommended */ 724 725 #define RMIICK_DIV4 0 726 #define RMIICK_DIV8 1 727 #define RMIICK_DIV12 2 728 #define RMIICK_DIV16 3 729 #define RMIICK_DIV20 4 /* recommended */ 730 #define RMIICK_DIV24 5 731 #define RMIICK_DIV28 6 732 #define RMIICK_DIV32 7 733 734 struct ast2600_mac_clk_div { 735 u32 src; /* 0=external PAD, 1=internal PLL */ 736 u32 fin; /* divider input speed */ 737 u32 n; /* 0=div2, 1=div2, 2=div3, 3=div4,...,7=div8 */ 738 u32 fout; /* fout = fin / n */ 739 }; 740 741 struct ast2600_mac_clk_div rgmii_clk_defconfig = { 742 .src = ASPEED_CLK_EPLL, 743 .fin = 1000000000, 744 .n = RGMIICK_DIV8, 745 .fout = 125000000, 746 }; 747 748 struct ast2600_mac_clk_div rmii_clk_defconfig = { 749 .src = ASPEED_CLK_EPLL, 750 .fin = 1000000000, 751 .n = RMIICK_DIV20, 752 .fout = 50000000, 753 }; 754 static void ast2600_init_mac_pll(struct ast2600_scu *p_scu, 755 struct ast2600_mac_clk_div *p_cfg) 756 { 757 struct ast2600_pll_desc pll; 758 759 pll.in = AST2600_CLK_IN; 760 pll.out = p_cfg->fin; 761 if (false == ast2600_search_clock_config(&pll)) { 762 printf("error!! unable to find valid ETHNET MAC clock " 763 "setting\n"); 764 debug("%s: pll cfg = 0x%08x 0x%08x\n", __func__, pll.cfg.reg.w, 765 pll.cfg.ext_reg); 766 debug("%s: pll cfg = %02x %02x %02x\n", __func__, 767 pll.cfg.reg.b.m, pll.cfg.reg.b.n, pll.cfg.reg.b.p); 768 return; 769 } 770 ast2600_configure_pll(p_scu, &(pll.cfg), p_cfg->src); 771 } 772 773 static void ast2600_init_rgmii_clk(struct ast2600_scu *p_scu, 774 struct ast2600_mac_clk_div *p_cfg) 775 { 776 u32 reg_304 = readl(&p_scu->clk_sel2); 777 u32 reg_340 = readl(&p_scu->mac12_clk_delay); 778 u32 reg_350 = readl(&p_scu->mac34_clk_delay); 779 780 reg_340 &= ~GENMASK(31, 29); 781 /* scu340[28]: RGMIICK PAD output enable (to MAC 3/4) */ 782 reg_340 |= BIT(28); 783 if ((p_cfg->src == ASPEED_CLK_EPLL) || 784 (p_cfg->src == ASPEED_CLK_HPLL)) { 785 /* 786 * re-init PLL if the current PLL output frequency doesn't match 787 * the divider setting 788 */ 789 if (p_cfg->fin != ast2600_get_pll_rate(p_scu, p_cfg->src)) { 790 ast2600_init_mac_pll(p_scu, p_cfg); 791 } 792 /* scu340[31]: select RGMII 125M from internal source */ 793 reg_340 |= BIT(31); 794 } 795 796 reg_304 &= ~GENMASK(23, 20); 797 798 /* set clock divider */ 799 reg_304 |= (p_cfg->n & 0x7) << 20; 800 801 /* select internal clock source */ 802 if (ASPEED_CLK_HPLL == p_cfg->src) { 803 reg_304 |= BIT(23); 804 } 805 806 /* RGMII 3/4 clock source select */ 807 reg_350 &= ~BIT(31); 808 809 writel(reg_304, &p_scu->clk_sel2); 810 writel(reg_340, &p_scu->mac12_clk_delay); 811 writel(reg_350, &p_scu->mac34_clk_delay); 812 } 813 814 /** 815 * ast2600 RMII/NCSI clock source tree 816 * 817 * HPLL -->|\ 818 * | |---->| divider |----> RMII 50M for MAC#1 & MAC#2 819 * EPLL -->|/ 820 * 821 * HCLK(SCLICLK)---->| divider |----> RMII 50M for MAC#3 & MAC#4 822 */ 823 static void ast2600_init_rmii_clk(struct ast2600_scu *p_scu, 824 struct ast2600_mac_clk_div *p_cfg) 825 { 826 u32 reg_304; 827 u32 reg_310; 828 829 if ((p_cfg->src == ASPEED_CLK_EPLL) || 830 (p_cfg->src == ASPEED_CLK_HPLL)) { 831 /* 832 * re-init PLL if the current PLL output frequency doesn't match 833 * the divider setting 834 */ 835 if (p_cfg->fin != ast2600_get_pll_rate(p_scu, p_cfg->src)) { 836 ast2600_init_mac_pll(p_scu, p_cfg); 837 } 838 } 839 840 reg_304 = readl(&p_scu->clk_sel2); 841 reg_310 = readl(&p_scu->clk_sel4); 842 843 reg_304 &= ~GENMASK(19, 16); 844 845 /* set RMII 1/2 clock divider */ 846 reg_304 |= (p_cfg->n & 0x7) << 16; 847 848 /* RMII clock source selection */ 849 if (ASPEED_CLK_HPLL == p_cfg->src) { 850 reg_304 |= BIT(19); 851 } 852 853 /* set RMII 3/4 clock divider */ 854 reg_310 &= ~GENMASK(18, 16); 855 reg_310 |= (0x3 << 16); 856 857 writel(reg_304, &p_scu->clk_sel2); 858 writel(reg_310, &p_scu->clk_sel4); 859 } 860 861 static u32 ast2600_configure_mac(struct ast2600_scu *scu, int index) 862 { 863 u32 reset_bit; 864 u32 clkstop_bit; 865 866 switch (index) { 867 case 1: 868 reset_bit = BIT(ASPEED_RESET_MAC1); 869 clkstop_bit = BIT(SCU_CLKSTOP_MAC1); 870 writel(reset_bit, &scu->sysreset_ctrl1); 871 udelay(100); 872 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 873 mdelay(10); 874 writel(reset_bit, &scu->sysreset_clr_ctrl1); 875 break; 876 case 2: 877 reset_bit = BIT(ASPEED_RESET_MAC2); 878 clkstop_bit = BIT(SCU_CLKSTOP_MAC2); 879 writel(reset_bit, &scu->sysreset_ctrl1); 880 udelay(100); 881 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 882 mdelay(10); 883 writel(reset_bit, &scu->sysreset_clr_ctrl1); 884 break; 885 case 3: 886 reset_bit = BIT(ASPEED_RESET_MAC3 - 32); 887 clkstop_bit = BIT(SCU_CLKSTOP_MAC3); 888 writel(reset_bit, &scu->sysreset_ctrl2); 889 udelay(100); 890 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 891 mdelay(10); 892 writel(reset_bit, &scu->sysreset_clr_ctrl2); 893 break; 894 case 4: 895 reset_bit = BIT(ASPEED_RESET_MAC4 - 32); 896 clkstop_bit = BIT(SCU_CLKSTOP_MAC4); 897 writel(reset_bit, &scu->sysreset_ctrl2); 898 udelay(100); 899 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 900 mdelay(10); 901 writel(reset_bit, &scu->sysreset_clr_ctrl2); 902 break; 903 default: 904 return -EINVAL; 905 } 906 907 return 0; 908 } 909 910 #define SCU_CLK_ECC_RSA_FROM_HPLL_CLK BIT(19) 911 #define SCU_CLK_ECC_RSA_CLK_MASK GENMASK(27, 26) 912 #define SCU_CLK_ECC_RSA_CLK_DIV(x) (x << 26) 913 static void ast2600_configure_rsa_ecc_clk(struct ast2600_scu *scu) 914 { 915 u32 clk_sel = readl(&scu->clk_sel1); 916 917 /* Configure RSA clock = HPLL/3 */ 918 clk_sel |= SCU_CLK_ECC_RSA_FROM_HPLL_CLK; 919 clk_sel &= ~SCU_CLK_ECC_RSA_CLK_MASK; 920 clk_sel |= SCU_CLK_ECC_RSA_CLK_DIV(2); 921 922 writel(clk_sel, &scu->clk_sel1); 923 } 924 925 #define SCU_CLKSTOP_SDIO 4 926 static ulong ast2600_enable_sdclk(struct ast2600_scu *scu) 927 { 928 u32 reset_bit; 929 u32 clkstop_bit; 930 931 reset_bit = BIT(ASPEED_RESET_SD - 32); 932 clkstop_bit = BIT(SCU_CLKSTOP_SDIO); 933 934 writel(reset_bit, &scu->sysreset_ctrl2); 935 936 udelay(100); 937 //enable clk 938 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 939 mdelay(10); 940 writel(reset_bit, &scu->sysreset_clr_ctrl2); 941 942 return 0; 943 } 944 945 #define SCU_CLKSTOP_EXTSD 31 946 #define SCU_CLK_SD_MASK (0x7 << 28) 947 #define SCU_CLK_SD_DIV(x) (x << 28) 948 #define SCU_CLK_SD_FROM_APLL_CLK BIT(8) 949 950 static ulong ast2600_enable_extsdclk(struct ast2600_scu *scu) 951 { 952 u32 clk_sel = readl(&scu->clk_sel4); 953 u32 enableclk_bit; 954 u32 rate = 0; 955 u32 div = 0; 956 int i = 0; 957 958 enableclk_bit = BIT(SCU_CLKSTOP_EXTSD); 959 960 /* ast2600 sd controller max clk is 200Mhz : 961 * use apll for clock source 800/4 = 200 : controller max is 200mhz 962 */ 963 rate = ast2600_get_apll_rate(scu); 964 for (i = 0; i < 8; i++) { 965 div = (i + 1) * 2; 966 if ((rate / div) <= 200000000) 967 break; 968 } 969 clk_sel &= ~SCU_CLK_SD_MASK; 970 clk_sel |= SCU_CLK_SD_DIV(i) | SCU_CLK_SD_FROM_APLL_CLK; 971 writel(clk_sel, &scu->clk_sel4); 972 973 //enable clk 974 setbits_le32(&scu->clk_sel4, enableclk_bit); 975 976 return 0; 977 } 978 979 #define SCU_CLKSTOP_EMMC 27 980 static ulong ast2600_enable_emmcclk(struct ast2600_scu *scu) 981 { 982 u32 reset_bit; 983 u32 clkstop_bit; 984 985 reset_bit = BIT(ASPEED_RESET_EMMC); 986 clkstop_bit = BIT(SCU_CLKSTOP_EMMC); 987 988 writel(reset_bit, &scu->sysreset_ctrl1); 989 udelay(100); 990 //enable clk 991 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 992 mdelay(10); 993 writel(reset_bit, &scu->sysreset_clr_ctrl1); 994 995 return 0; 996 } 997 998 #define SCU_CLKSTOP_EXTEMMC 15 999 #define SCU_CLK_EMMC_MASK (0x7 << 12) 1000 #define SCU_CLK_EMMC_DIV(x) (x << 12) 1001 #define SCU_CLK_EMMC_FROM_MPLL_CLK BIT(11) 1002 1003 static ulong ast2600_enable_extemmcclk(struct ast2600_scu *scu) 1004 { 1005 u32 revision_id = readl(&scu->chip_id1); 1006 u32 clk_sel = readl(&scu->clk_sel1); 1007 u32 enableclk_bit; 1008 u32 rate = 0; 1009 u32 div = 0; 1010 int i = 0; 1011 1012 enableclk_bit = BIT(SCU_CLKSTOP_EXTEMMC); 1013 1014 //ast2600 eMMC controller max clk is 200Mhz 1015 /* 1016 HPll->1/2-> 1017 \ 1018 ->SCU300[11]->SCU300[14:12][1/N]->EMMC12C[15:8][1/N]-> eMMC clk 1019 / 1020 MPLL------> 1021 */ 1022 if (((revision_id & CHIP_REVISION_ID) >> 16)) { 1023 //AST2600A1 : use mpll to be clk source 1024 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL); 1025 for (i = 0; i < 8; i++) { 1026 div = (i + 1) * 2; 1027 if ((rate / div) <= 200000000) 1028 break; 1029 } 1030 1031 clk_sel &= ~SCU_CLK_EMMC_MASK; 1032 clk_sel |= SCU_CLK_EMMC_DIV(i) | SCU_CLK_EMMC_FROM_MPLL_CLK; 1033 writel(clk_sel, &scu->clk_sel1); 1034 1035 } else { 1036 //AST2600A0 : use hpll to be clk source 1037 rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); 1038 1039 for (i = 0; i < 8; i++) { 1040 div = (i + 1) * 4; 1041 if ((rate / div) <= 200000000) 1042 break; 1043 } 1044 1045 clk_sel &= ~SCU_CLK_EMMC_MASK; 1046 clk_sel |= SCU_CLK_EMMC_DIV(i); 1047 writel(clk_sel, &scu->clk_sel1); 1048 } 1049 setbits_le32(&scu->clk_sel1, enableclk_bit); 1050 1051 return 0; 1052 } 1053 1054 #define SCU_CLKSTOP_FSICLK 30 1055 1056 static ulong ast2600_enable_fsiclk(struct ast2600_scu *scu) 1057 { 1058 u32 reset_bit; 1059 u32 clkstop_bit; 1060 1061 reset_bit = BIT(ASPEED_RESET_FSI % 32); 1062 clkstop_bit = BIT(SCU_CLKSTOP_FSICLK); 1063 1064 /* The FSI clock is shared between masters. If it's already on 1065 * don't touch it, as that will reset the existing master. */ 1066 if (!(readl(&scu->clk_stop_ctrl2) & clkstop_bit)) { 1067 debug("%s: already running, not touching it\n", __func__); 1068 return 0; 1069 } 1070 1071 writel(reset_bit, &scu->sysreset_ctrl2); 1072 udelay(100); 1073 writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); 1074 mdelay(10); 1075 writel(reset_bit, &scu->sysreset_clr_ctrl2); 1076 1077 return 0; 1078 } 1079 1080 static ulong ast2600_enable_usbahclk(struct ast2600_scu *scu) 1081 { 1082 u32 reset_bit; 1083 u32 clkstop_bit; 1084 1085 reset_bit = BIT(ASPEED_RESET_EHCI_P1); 1086 clkstop_bit = BIT(14); 1087 1088 writel(reset_bit, &scu->sysreset_ctrl1); 1089 udelay(100); 1090 writel(clkstop_bit, &scu->clk_stop_ctrl1); 1091 mdelay(20); 1092 writel(reset_bit, &scu->sysreset_clr_ctrl1); 1093 1094 return 0; 1095 } 1096 1097 static ulong ast2600_enable_usbbhclk(struct ast2600_scu *scu) 1098 { 1099 u32 reset_bit; 1100 u32 clkstop_bit; 1101 1102 reset_bit = BIT(ASPEED_RESET_EHCI_P2); 1103 clkstop_bit = BIT(7); 1104 1105 writel(reset_bit, &scu->sysreset_ctrl1); 1106 udelay(100); 1107 writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); 1108 mdelay(20); 1109 1110 writel(reset_bit, &scu->sysreset_clr_ctrl1); 1111 1112 return 0; 1113 } 1114 1115 static int ast2600_clk_enable(struct clk *clk) 1116 { 1117 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 1118 1119 switch (clk->id) { 1120 case ASPEED_CLK_GATE_MAC1CLK: 1121 ast2600_configure_mac(priv->scu, 1); 1122 break; 1123 case ASPEED_CLK_GATE_MAC2CLK: 1124 ast2600_configure_mac(priv->scu, 2); 1125 break; 1126 case ASPEED_CLK_GATE_MAC3CLK: 1127 ast2600_configure_mac(priv->scu, 3); 1128 break; 1129 case ASPEED_CLK_GATE_MAC4CLK: 1130 ast2600_configure_mac(priv->scu, 4); 1131 break; 1132 case ASPEED_CLK_GATE_SDCLK: 1133 ast2600_enable_sdclk(priv->scu); 1134 break; 1135 case ASPEED_CLK_GATE_SDEXTCLK: 1136 ast2600_enable_extsdclk(priv->scu); 1137 break; 1138 case ASPEED_CLK_GATE_EMMCCLK: 1139 ast2600_enable_emmcclk(priv->scu); 1140 break; 1141 case ASPEED_CLK_GATE_EMMCEXTCLK: 1142 ast2600_enable_extemmcclk(priv->scu); 1143 break; 1144 case ASPEED_CLK_GATE_FSICLK: 1145 ast2600_enable_fsiclk(priv->scu); 1146 break; 1147 case ASPEED_CLK_GATE_USBPORT1CLK: 1148 ast2600_enable_usbahclk(priv->scu); 1149 break; 1150 case ASPEED_CLK_GATE_USBPORT2CLK: 1151 ast2600_enable_usbbhclk(priv->scu); 1152 break; 1153 default: 1154 pr_debug("can't enable clk \n"); 1155 return -ENOENT; 1156 break; 1157 } 1158 1159 return 0; 1160 } 1161 1162 struct clk_ops ast2600_clk_ops = { 1163 .get_rate = ast2600_clk_get_rate, 1164 .set_rate = ast2600_clk_set_rate, 1165 .enable = ast2600_clk_enable, 1166 }; 1167 1168 static int ast2600_clk_probe(struct udevice *dev) 1169 { 1170 struct ast2600_clk_priv *priv = dev_get_priv(dev); 1171 u32 uart_clk_source; 1172 1173 priv->scu = devfdt_get_addr_ptr(dev); 1174 if (IS_ERR(priv->scu)) 1175 return PTR_ERR(priv->scu); 1176 1177 uart_clk_source = dev_read_u32_default(dev, "uart-clk-source", 0x0); 1178 1179 if (uart_clk_source) { 1180 if (uart_clk_source & GENMASK(5, 0)) 1181 setbits_le32(&priv->scu->clk_sel4, 1182 uart_clk_source & GENMASK(5, 0)); 1183 if (uart_clk_source & GENMASK(12, 6)) 1184 setbits_le32(&priv->scu->clk_sel5, 1185 uart_clk_source & GENMASK(12, 6)); 1186 } 1187 1188 ast2600_init_rgmii_clk(priv->scu, &rgmii_clk_defconfig); 1189 ast2600_init_rmii_clk(priv->scu, &rmii_clk_defconfig); 1190 ast2600_configure_mac12_clk(priv->scu); 1191 ast2600_configure_mac34_clk(priv->scu); 1192 ast2600_configure_rsa_ecc_clk(priv->scu); 1193 1194 return 0; 1195 } 1196 1197 static int ast2600_clk_bind(struct udevice *dev) 1198 { 1199 int ret; 1200 1201 /* The reset driver does not have a device node, so bind it here */ 1202 ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev); 1203 if (ret) 1204 debug("Warning: No reset driver: ret=%d\n", ret); 1205 1206 return 0; 1207 } 1208 1209 #if CONFIG_IS_ENABLED(CMD_CLK) 1210 struct aspeed_clks { 1211 ulong id; 1212 const char *name; 1213 }; 1214 1215 static struct aspeed_clks aspeed_clk_names[] = { 1216 { ASPEED_CLK_HPLL, "hpll" }, { ASPEED_CLK_MPLL, "mpll" }, 1217 { ASPEED_CLK_APLL, "apll" }, { ASPEED_CLK_EPLL, "epll" }, 1218 { ASPEED_CLK_DPLL, "dpll" }, { ASPEED_CLK_AHB, "hclk" }, 1219 { ASPEED_CLK_APB1, "pclk1" }, { ASPEED_CLK_APB2, "pclk2" }, 1220 { ASPEED_CLK_BCLK, "bclk" }, { ASPEED_CLK_UARTX, "uxclk" }, 1221 { ASPEED_CLK_HUARTX, "huxclk" }, 1222 }; 1223 1224 int soc_clk_dump(void) 1225 { 1226 struct udevice *dev; 1227 struct clk clk; 1228 unsigned long rate; 1229 int i, ret; 1230 1231 ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu), 1232 &dev); 1233 if (ret) 1234 return ret; 1235 1236 printf("Clk\t\tHz\n"); 1237 1238 for (i = 0; i < ARRAY_SIZE(aspeed_clk_names); i++) { 1239 clk.id = aspeed_clk_names[i].id; 1240 ret = clk_request(dev, &clk); 1241 if (ret < 0) { 1242 debug("%s clk_request() failed: %d\n", __func__, ret); 1243 continue; 1244 } 1245 1246 ret = clk_get_rate(&clk); 1247 rate = ret; 1248 1249 clk_free(&clk); 1250 1251 if (ret == -ENOTSUPP) { 1252 printf("clk ID %lu not supported yet\n", 1253 aspeed_clk_names[i].id); 1254 continue; 1255 } 1256 if (ret < 0) { 1257 printf("%s %lu: get_rate err: %d\n", __func__, 1258 aspeed_clk_names[i].id, ret); 1259 continue; 1260 } 1261 1262 printf("%s(%3lu):\t%lu\n", aspeed_clk_names[i].name, 1263 aspeed_clk_names[i].id, rate); 1264 } 1265 1266 return 0; 1267 } 1268 #endif 1269 1270 static const struct udevice_id ast2600_clk_ids[] = { 1271 { 1272 .compatible = "aspeed,ast2600-scu", 1273 }, 1274 {} 1275 }; 1276 1277 U_BOOT_DRIVER(aspeed_scu) = { 1278 .name = "aspeed_scu", 1279 .id = UCLASS_CLK, 1280 .of_match = ast2600_clk_ids, 1281 .priv_auto_alloc_size = sizeof(struct ast2600_clk_priv), 1282 .ops = &ast2600_clk_ops, 1283 .bind = ast2600_clk_bind, 1284 .probe = ast2600_clk_probe, 1285 }; 1286