| /openbmc/linux/drivers/gpu/drm/amd/amdkfd/ |
| H A D | kfd_device_queue_manager_v11.c | 69 qpd->sh_mem_bases = compute_sh_mem_bases_64bit(pdd); in update_qpd_v11()
71 pr_debug("sh_mem_bases 0x%X\n", qpd->sh_mem_bases); in update_qpd_v11()
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| H A D | kfd_device_queue_manager_v10.c | 69 qpd->sh_mem_bases = compute_sh_mem_bases_64bit(pdd); in update_qpd_v10()
71 pr_debug("sh_mem_bases 0x%X\n", qpd->sh_mem_bases); in update_qpd_v10()
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| H A D | kfd_device_queue_manager_v9.c | 81 qpd->sh_mem_bases = compute_sh_mem_bases_64bit(pdd); in update_qpd_v9()
83 pr_debug("sh_mem_bases 0x%X sh_mem_config 0x%X\n", qpd->sh_mem_bases, in update_qpd_v9()
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| H A D | kfd_pm4_headers.h | 75 uint32_t sh_mem_bases; member
125 uint32_t sh_mem_bases; member
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| H A D | kfd_device_queue_manager_vi.c | 132 qpd->sh_mem_bases = compute_sh_mem_bases_64bit(temp); in update_qpd_vi()
135 temp, qpd->sh_mem_bases); in update_qpd_vi()
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| H A D | kfd_device_queue_manager_cik.c | 126 qpd->sh_mem_bases = compute_sh_mem_bases_64bit(temp); in update_qpd_cik()
129 qpd->pqm->process->is_32bit_user_mode, temp, qpd->sh_mem_bases); in update_qpd_cik()
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| H A D | kfd_packet_manager_v9.c | 62 packet->sh_mem_bases = qpd->sh_mem_bases; in pm_map_process_v9()
121 packet->sh_mem_bases = qpd->sh_mem_bases; in pm_map_process_aldebaran()
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| H A D | kfd_pm4_headers_aldebaran.h | 54 uint32_t sh_mem_bases; member
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| H A D | kfd_packet_manager_vi.c | 63 packet->sh_mem_bases = qpd->sh_mem_bases; in pm_map_process_vi()
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| H A D | kfd_pm4_headers_vi.h | 172 uint32_t sh_mem_bases; member
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| H A D | kfd_pm4_headers_ai.h | 163 uint32_t sh_mem_bases; member
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| H A D | kfd_priv.h | 670 uint32_t sh_mem_bases; member
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| /openbmc/linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_amdkfd_gfx_v9.h | 26 uint32_t sh_mem_bases, uint32_t inst);
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| H A D | amdgpu_amdkfd_gfx_v7.c | 81 uint32_t sh_mem_bases, uint32_t inst) in kgd_program_sh_mem_settings() argument
88 WREG32(mmSH_MEM_BASES, sh_mem_bases); in kgd_program_sh_mem_settings()
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| H A D | amdgpu_amdkfd_gfx_v8.c | 75 uint32_t sh_mem_bases, uint32_t inst) in kgd_program_sh_mem_settings() argument
82 WREG32(mmSH_MEM_BASES, sh_mem_bases); in kgd_program_sh_mem_settings()
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| H A D | amdgpu_amdkfd_gfx_v10_3.c | 84 uint32_t sh_mem_bases, uint32_t inst) in program_sh_mem_settings_v10_3() argument
89 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); in program_sh_mem_settings_v10_3()
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| H A D | amdgpu_amdkfd_gfx_v11.c | 82 uint32_t sh_mem_bases, uint32_t inst) in program_sh_mem_settings_v11() argument
87 WREG32(SOC15_REG_OFFSET(GC, 0, regSH_MEM_BASES), sh_mem_bases); in program_sh_mem_settings_v11()
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| H A D | amdgpu_amdkfd_gfx_v10.c | 84 uint32_t sh_mem_bases, uint32_t inst) in kgd_program_sh_mem_settings() argument
89 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); in kgd_program_sh_mem_settings()
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| H A D | amdgpu_amdkfd_gfx_v9.c | 90 uint32_t sh_mem_bases, uint32_t inst) in kgd_gfx_v9_program_sh_mem_settings() argument
95 WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmSH_MEM_BASES), sh_mem_bases); in kgd_gfx_v9_program_sh_mem_settings()
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| H A D | gfx_v7_0.c | 1820 uint32_t sh_mem_bases; in gfx_v7_0_init_compute_vmid() local
1828 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); in gfx_v7_0_init_compute_vmid()
1839 WREG32(mmSH_MEM_BASES, sh_mem_bases); in gfx_v7_0_init_compute_vmid()
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| H A D | gfx_v9_4_3.c | 907 uint32_t sh_mem_bases; in gfx_v9_4_3_xcc_init_compute_vmid() local
916 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); in gfx_v9_4_3_xcc_init_compute_vmid()
927 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases); in gfx_v9_4_3_xcc_init_compute_vmid()
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| H A D | gfx_v11_0.c | 1631 uint32_t sh_mem_bases; in gfx_v11_0_init_compute_vmid() local
1640 sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) | in gfx_v11_0_init_compute_vmid()
1648 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); in gfx_v11_0_init_compute_vmid()
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| H A D | gfx_v8_0.c | 3662 uint32_t sh_mem_bases; in gfx_v8_0_init_compute_vmid() local
3670 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); in gfx_v8_0_init_compute_vmid()
3686 WREG32(mmSH_MEM_BASES, sh_mem_bases); in gfx_v8_0_init_compute_vmid()
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| H A D | gfx_v9_0.c | 2310 uint32_t sh_mem_bases; in gfx_v9_0_init_compute_vmid() local
2318 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); in gfx_v9_0_init_compute_vmid()
2329 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, sh_mem_bases); in gfx_v9_0_init_compute_vmid()
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| /openbmc/linux/drivers/gpu/drm/amd/include/ |
| H A D | kgd_kfd_interface.h | 233 uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases,
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