1*cc009e61SMukul Joshi /*
2*cc009e61SMukul Joshi * Copyright 2021 Advanced Micro Devices, Inc.
3*cc009e61SMukul Joshi *
4*cc009e61SMukul Joshi * Permission is hereby granted, free of charge, to any person obtaining a
5*cc009e61SMukul Joshi * copy of this software and associated documentation files (the "Software"),
6*cc009e61SMukul Joshi * to deal in the Software without restriction, including without limitation
7*cc009e61SMukul Joshi * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*cc009e61SMukul Joshi * and/or sell copies of the Software, and to permit persons to whom the
9*cc009e61SMukul Joshi * Software is furnished to do so, subject to the following conditions:
10*cc009e61SMukul Joshi *
11*cc009e61SMukul Joshi * The above copyright notice and this permission notice shall be included in
12*cc009e61SMukul Joshi * all copies or substantial portions of the Software.
13*cc009e61SMukul Joshi *
14*cc009e61SMukul Joshi * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*cc009e61SMukul Joshi * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*cc009e61SMukul Joshi * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17*cc009e61SMukul Joshi * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*cc009e61SMukul Joshi * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*cc009e61SMukul Joshi * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*cc009e61SMukul Joshi * OTHER DEALINGS IN THE SOFTWARE.
21*cc009e61SMukul Joshi *
22*cc009e61SMukul Joshi */
23*cc009e61SMukul Joshi
24*cc009e61SMukul Joshi #include "kfd_device_queue_manager.h"
25*cc009e61SMukul Joshi #include "gc/gc_11_0_0_offset.h"
26*cc009e61SMukul Joshi #include "gc/gc_11_0_0_sh_mask.h"
27*cc009e61SMukul Joshi #include "soc21_enum.h"
28*cc009e61SMukul Joshi
29*cc009e61SMukul Joshi static int update_qpd_v11(struct device_queue_manager *dqm,
30*cc009e61SMukul Joshi struct qcm_process_device *qpd);
31*cc009e61SMukul Joshi static void init_sdma_vm_v11(struct device_queue_manager *dqm, struct queue *q,
32*cc009e61SMukul Joshi struct qcm_process_device *qpd);
33*cc009e61SMukul Joshi
device_queue_manager_init_v11(struct device_queue_manager_asic_ops * asic_ops)34*cc009e61SMukul Joshi void device_queue_manager_init_v11(
35*cc009e61SMukul Joshi struct device_queue_manager_asic_ops *asic_ops)
36*cc009e61SMukul Joshi {
37*cc009e61SMukul Joshi asic_ops->update_qpd = update_qpd_v11;
38*cc009e61SMukul Joshi asic_ops->init_sdma_vm = init_sdma_vm_v11;
39*cc009e61SMukul Joshi asic_ops->mqd_manager_init = mqd_manager_init_v11;
40*cc009e61SMukul Joshi }
41*cc009e61SMukul Joshi
compute_sh_mem_bases_64bit(struct kfd_process_device * pdd)42*cc009e61SMukul Joshi static uint32_t compute_sh_mem_bases_64bit(struct kfd_process_device *pdd)
43*cc009e61SMukul Joshi {
44*cc009e61SMukul Joshi uint32_t shared_base = pdd->lds_base >> 48;
45*cc009e61SMukul Joshi uint32_t private_base = pdd->scratch_base >> 48;
46*cc009e61SMukul Joshi
47*cc009e61SMukul Joshi return (shared_base << SH_MEM_BASES__SHARED_BASE__SHIFT) |
48*cc009e61SMukul Joshi private_base;
49*cc009e61SMukul Joshi }
50*cc009e61SMukul Joshi
update_qpd_v11(struct device_queue_manager * dqm,struct qcm_process_device * qpd)51*cc009e61SMukul Joshi static int update_qpd_v11(struct device_queue_manager *dqm,
52*cc009e61SMukul Joshi struct qcm_process_device *qpd)
53*cc009e61SMukul Joshi {
54*cc009e61SMukul Joshi struct kfd_process_device *pdd;
55*cc009e61SMukul Joshi
56*cc009e61SMukul Joshi pdd = qpd_to_pdd(qpd);
57*cc009e61SMukul Joshi
58*cc009e61SMukul Joshi /* check if sh_mem_config register already configured */
59*cc009e61SMukul Joshi if (qpd->sh_mem_config == 0) {
60*cc009e61SMukul Joshi qpd->sh_mem_config =
61*cc009e61SMukul Joshi (SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
62*cc009e61SMukul Joshi SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) |
63*cc009e61SMukul Joshi (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT);
64*cc009e61SMukul Joshi
65*cc009e61SMukul Joshi qpd->sh_mem_ape1_limit = 0;
66*cc009e61SMukul Joshi qpd->sh_mem_ape1_base = 0;
67*cc009e61SMukul Joshi }
68*cc009e61SMukul Joshi
69*cc009e61SMukul Joshi qpd->sh_mem_bases = compute_sh_mem_bases_64bit(pdd);
70*cc009e61SMukul Joshi
71*cc009e61SMukul Joshi pr_debug("sh_mem_bases 0x%X\n", qpd->sh_mem_bases);
72*cc009e61SMukul Joshi
73*cc009e61SMukul Joshi return 0;
74*cc009e61SMukul Joshi }
75*cc009e61SMukul Joshi
init_sdma_vm_v11(struct device_queue_manager * dqm,struct queue * q,struct qcm_process_device * qpd)76*cc009e61SMukul Joshi static void init_sdma_vm_v11(struct device_queue_manager *dqm, struct queue *q,
77*cc009e61SMukul Joshi struct qcm_process_device *qpd)
78*cc009e61SMukul Joshi {
79*cc009e61SMukul Joshi /* Not needed on SDMAv4 onwards any more */
80*cc009e61SMukul Joshi q->properties.sdma_vm_addr = 0;
81*cc009e61SMukul Joshi }
82