1*d87f36a0SRajneesh Bhardwaj /* SPDX-License-Identifier: GPL-2.0 OR MIT */ 22d8f1f33SBen Goz /* 3*d87f36a0SRajneesh Bhardwaj * Copyright 2014-2022 Advanced Micro Devices, Inc. 42d8f1f33SBen Goz * 52d8f1f33SBen Goz * Permission is hereby granted, free of charge, to any person obtaining a 62d8f1f33SBen Goz * copy of this software and associated documentation files (the "Software"), 72d8f1f33SBen Goz * to deal in the Software without restriction, including without limitation 82d8f1f33SBen Goz * the rights to use, copy, modify, merge, publish, distribute, sublicense, 92d8f1f33SBen Goz * and/or sell copies of the Software, and to permit persons to whom the 102d8f1f33SBen Goz * Software is furnished to do so, subject to the following conditions: 112d8f1f33SBen Goz * 122d8f1f33SBen Goz * The above copyright notice and this permission notice shall be included in 132d8f1f33SBen Goz * all copies or substantial portions of the Software. 142d8f1f33SBen Goz * 152d8f1f33SBen Goz * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 162d8f1f33SBen Goz * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 172d8f1f33SBen Goz * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 182d8f1f33SBen Goz * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 192d8f1f33SBen Goz * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 202d8f1f33SBen Goz * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 212d8f1f33SBen Goz * OTHER DEALINGS IN THE SOFTWARE. 222d8f1f33SBen Goz * 232d8f1f33SBen Goz */ 242d8f1f33SBen Goz 252d8f1f33SBen Goz #ifndef F32_MES_PM4_PACKETS_H 262d8f1f33SBen Goz #define F32_MES_PM4_PACKETS_H 272d8f1f33SBen Goz 282d8f1f33SBen Goz #ifndef PM4_MES_HEADER_DEFINED 292d8f1f33SBen Goz #define PM4_MES_HEADER_DEFINED 302d8f1f33SBen Goz union PM4_MES_TYPE_3_HEADER { 312d8f1f33SBen Goz struct { 322d8f1f33SBen Goz uint32_t reserved1 : 8; /* < reserved */ 332d8f1f33SBen Goz uint32_t opcode : 8; /* < IT opcode */ 348eabaf54SKent Russell uint32_t count : 14;/* < Number of DWORDS - 1 in the 358eabaf54SKent Russell * information body 368eabaf54SKent Russell */ 378eabaf54SKent Russell uint32_t type : 2; /* < packet identifier 388eabaf54SKent Russell * It should be 3 for type 3 packets 398eabaf54SKent Russell */ 402d8f1f33SBen Goz }; 412d8f1f33SBen Goz uint32_t u32All; 422d8f1f33SBen Goz }; 432d8f1f33SBen Goz #endif /* PM4_MES_HEADER_DEFINED */ 442d8f1f33SBen Goz 452d8f1f33SBen Goz /*--------------------MES_SET_RESOURCES--------------------*/ 462d8f1f33SBen Goz 472d8f1f33SBen Goz #ifndef PM4_MES_SET_RESOURCES_DEFINED 482d8f1f33SBen Goz #define PM4_MES_SET_RESOURCES_DEFINED 492d8f1f33SBen Goz enum mes_set_resources_queue_type_enum { 502d8f1f33SBen Goz queue_type__mes_set_resources__kernel_interface_queue_kiq = 0, 512d8f1f33SBen Goz queue_type__mes_set_resources__hsa_interface_queue_hiq = 1, 522d8f1f33SBen Goz queue_type__mes_set_resources__hsa_debug_interface_queue = 4 532d8f1f33SBen Goz }; 542d8f1f33SBen Goz 552d8f1f33SBen Goz 562d8f1f33SBen Goz struct pm4_mes_set_resources { 572d8f1f33SBen Goz union { 582d8f1f33SBen Goz union PM4_MES_TYPE_3_HEADER header; /* header */ 592d8f1f33SBen Goz uint32_t ordinal1; 602d8f1f33SBen Goz }; 612d8f1f33SBen Goz 622d8f1f33SBen Goz union { 632d8f1f33SBen Goz struct { 642d8f1f33SBen Goz uint32_t vmid_mask:16; 652d8f1f33SBen Goz uint32_t unmap_latency:8; 662d8f1f33SBen Goz uint32_t reserved1:5; 672d8f1f33SBen Goz enum mes_set_resources_queue_type_enum queue_type:3; 682d8f1f33SBen Goz } bitfields2; 692d8f1f33SBen Goz uint32_t ordinal2; 702d8f1f33SBen Goz }; 712d8f1f33SBen Goz 722d8f1f33SBen Goz uint32_t queue_mask_lo; 732d8f1f33SBen Goz uint32_t queue_mask_hi; 742d8f1f33SBen Goz uint32_t gws_mask_lo; 752d8f1f33SBen Goz uint32_t gws_mask_hi; 762d8f1f33SBen Goz 772d8f1f33SBen Goz union { 782d8f1f33SBen Goz struct { 792d8f1f33SBen Goz uint32_t oac_mask:16; 802d8f1f33SBen Goz uint32_t reserved2:16; 812d8f1f33SBen Goz } bitfields7; 822d8f1f33SBen Goz uint32_t ordinal7; 832d8f1f33SBen Goz }; 842d8f1f33SBen Goz 852d8f1f33SBen Goz union { 862d8f1f33SBen Goz struct { 872d8f1f33SBen Goz uint32_t gds_heap_base:6; 882d8f1f33SBen Goz uint32_t reserved3:5; 892d8f1f33SBen Goz uint32_t gds_heap_size:6; 902d8f1f33SBen Goz uint32_t reserved4:15; 912d8f1f33SBen Goz } bitfields8; 922d8f1f33SBen Goz uint32_t ordinal8; 932d8f1f33SBen Goz }; 942d8f1f33SBen Goz 952d8f1f33SBen Goz }; 962d8f1f33SBen Goz #endif 972d8f1f33SBen Goz 982d8f1f33SBen Goz /*--------------------MES_RUN_LIST--------------------*/ 992d8f1f33SBen Goz 1002d8f1f33SBen Goz #ifndef PM4_MES_RUN_LIST_DEFINED 1012d8f1f33SBen Goz #define PM4_MES_RUN_LIST_DEFINED 1022d8f1f33SBen Goz 1032d8f1f33SBen Goz struct pm4_mes_runlist { 1042d8f1f33SBen Goz union { 1052d8f1f33SBen Goz union PM4_MES_TYPE_3_HEADER header; /* header */ 1062d8f1f33SBen Goz uint32_t ordinal1; 1072d8f1f33SBen Goz }; 1082d8f1f33SBen Goz 1092d8f1f33SBen Goz union { 1102d8f1f33SBen Goz struct { 1112d8f1f33SBen Goz uint32_t reserved1:2; 1122d8f1f33SBen Goz uint32_t ib_base_lo:30; 1132d8f1f33SBen Goz } bitfields2; 1142d8f1f33SBen Goz uint32_t ordinal2; 1152d8f1f33SBen Goz }; 1162d8f1f33SBen Goz 1172d8f1f33SBen Goz union { 1182d8f1f33SBen Goz struct { 1192d8f1f33SBen Goz uint32_t ib_base_hi:16; 1202d8f1f33SBen Goz uint32_t reserved2:16; 1212d8f1f33SBen Goz } bitfields3; 1222d8f1f33SBen Goz uint32_t ordinal3; 1232d8f1f33SBen Goz }; 1242d8f1f33SBen Goz 1252d8f1f33SBen Goz union { 1262d8f1f33SBen Goz struct { 1272d8f1f33SBen Goz uint32_t ib_size:20; 1282d8f1f33SBen Goz uint32_t chain:1; 1292d8f1f33SBen Goz uint32_t offload_polling:1; 130507968ddSFelix Kuehling uint32_t reserved2:1; 1312d8f1f33SBen Goz uint32_t valid:1; 132507968ddSFelix Kuehling uint32_t process_cnt:4; 133507968ddSFelix Kuehling uint32_t reserved3:4; 1342d8f1f33SBen Goz } bitfields4; 1352d8f1f33SBen Goz uint32_t ordinal4; 1362d8f1f33SBen Goz }; 1372d8f1f33SBen Goz 1382d8f1f33SBen Goz }; 1392d8f1f33SBen Goz #endif 1402d8f1f33SBen Goz 1412d8f1f33SBen Goz /*--------------------MES_MAP_PROCESS--------------------*/ 1422d8f1f33SBen Goz 1432d8f1f33SBen Goz #ifndef PM4_MES_MAP_PROCESS_DEFINED 1442d8f1f33SBen Goz #define PM4_MES_MAP_PROCESS_DEFINED 1452d8f1f33SBen Goz 1462d8f1f33SBen Goz struct pm4_mes_map_process { 1472d8f1f33SBen Goz union { 1482d8f1f33SBen Goz union PM4_MES_TYPE_3_HEADER header; /* header */ 1492d8f1f33SBen Goz uint32_t ordinal1; 1502d8f1f33SBen Goz }; 1512d8f1f33SBen Goz 1522d8f1f33SBen Goz union { 1532d8f1f33SBen Goz struct { 1542d8f1f33SBen Goz uint32_t pasid:16; 1552d8f1f33SBen Goz uint32_t reserved1:8; 1562d8f1f33SBen Goz uint32_t diq_enable:1; 1572d8f1f33SBen Goz uint32_t process_quantum:7; 1582d8f1f33SBen Goz } bitfields2; 1592d8f1f33SBen Goz uint32_t ordinal2; 1602d8f1f33SBen Goz }; 1612d8f1f33SBen Goz 1622d8f1f33SBen Goz union { 1632d8f1f33SBen Goz struct { 1642d8f1f33SBen Goz uint32_t page_table_base:28; 165507968ddSFelix Kuehling uint32_t reserved3:4; 1662d8f1f33SBen Goz } bitfields3; 1672d8f1f33SBen Goz uint32_t ordinal3; 1682d8f1f33SBen Goz }; 1692d8f1f33SBen Goz 170507968ddSFelix Kuehling uint32_t reserved; 171507968ddSFelix Kuehling 1722d8f1f33SBen Goz uint32_t sh_mem_bases; 173507968ddSFelix Kuehling uint32_t sh_mem_config; 1742d8f1f33SBen Goz uint32_t sh_mem_ape1_base; 1752d8f1f33SBen Goz uint32_t sh_mem_ape1_limit; 176507968ddSFelix Kuehling 177507968ddSFelix Kuehling uint32_t sh_hidden_private_base_vmid; 178507968ddSFelix Kuehling 179507968ddSFelix Kuehling uint32_t reserved2; 180507968ddSFelix Kuehling uint32_t reserved3; 181507968ddSFelix Kuehling 1822d8f1f33SBen Goz uint32_t gds_addr_lo; 1832d8f1f33SBen Goz uint32_t gds_addr_hi; 1842d8f1f33SBen Goz 1852d8f1f33SBen Goz union { 1862d8f1f33SBen Goz struct { 1872d8f1f33SBen Goz uint32_t num_gws:6; 188507968ddSFelix Kuehling uint32_t reserved4:2; 1892d8f1f33SBen Goz uint32_t num_oac:4; 190507968ddSFelix Kuehling uint32_t reserved5:4; 1912d8f1f33SBen Goz uint32_t gds_size:6; 1922d8f1f33SBen Goz uint32_t num_queues:10; 1932d8f1f33SBen Goz } bitfields10; 1942d8f1f33SBen Goz uint32_t ordinal10; 1952d8f1f33SBen Goz }; 1962d8f1f33SBen Goz 197507968ddSFelix Kuehling uint32_t completion_signal_lo; 198507968ddSFelix Kuehling uint32_t completion_signal_hi; 199507968ddSFelix Kuehling 2002d8f1f33SBen Goz }; 201507968ddSFelix Kuehling 2022d8f1f33SBen Goz #endif 2032d8f1f33SBen Goz 2042d8f1f33SBen Goz /*--------------------MES_MAP_QUEUES--------------------*/ 2052d8f1f33SBen Goz 2062d8f1f33SBen Goz #ifndef PM4_MES_MAP_QUEUES_VI_DEFINED 2072d8f1f33SBen Goz #define PM4_MES_MAP_QUEUES_VI_DEFINED 2082d8f1f33SBen Goz enum mes_map_queues_queue_sel_vi_enum { 2092d8f1f33SBen Goz queue_sel__mes_map_queues__map_to_specified_queue_slots_vi = 0, 2102d8f1f33SBen Goz queue_sel__mes_map_queues__map_to_hws_determined_queue_slots_vi = 1 2112d8f1f33SBen Goz }; 2122d8f1f33SBen Goz 2132d8f1f33SBen Goz enum mes_map_queues_queue_type_vi_enum { 2142d8f1f33SBen Goz queue_type__mes_map_queues__normal_compute_vi = 0, 2152d8f1f33SBen Goz queue_type__mes_map_queues__debug_interface_queue_vi = 1, 2162d8f1f33SBen Goz queue_type__mes_map_queues__normal_latency_static_queue_vi = 2, 2172d8f1f33SBen Goz queue_type__mes_map_queues__low_latency_static_queue_vi = 3 2182d8f1f33SBen Goz }; 2192d8f1f33SBen Goz 2202d8f1f33SBen Goz enum mes_map_queues_engine_sel_vi_enum { 2212d8f1f33SBen Goz engine_sel__mes_map_queues__compute_vi = 0, 2222d8f1f33SBen Goz engine_sel__mes_map_queues__sdma0_vi = 2, 2232d8f1f33SBen Goz engine_sel__mes_map_queues__sdma1_vi = 3 2242d8f1f33SBen Goz }; 2252d8f1f33SBen Goz 2262d8f1f33SBen Goz 2272d8f1f33SBen Goz struct pm4_mes_map_queues { 2282d8f1f33SBen Goz union { 2292d8f1f33SBen Goz union PM4_MES_TYPE_3_HEADER header; /* header */ 2302d8f1f33SBen Goz uint32_t ordinal1; 2312d8f1f33SBen Goz }; 2322d8f1f33SBen Goz 2332d8f1f33SBen Goz union { 2342d8f1f33SBen Goz struct { 2352d8f1f33SBen Goz uint32_t reserved1:4; 2362d8f1f33SBen Goz enum mes_map_queues_queue_sel_vi_enum queue_sel:2; 2372d8f1f33SBen Goz uint32_t reserved2:15; 2382d8f1f33SBen Goz enum mes_map_queues_queue_type_vi_enum queue_type:3; 23916631affSOak Zeng uint32_t reserved3:2; 2402d8f1f33SBen Goz enum mes_map_queues_engine_sel_vi_enum engine_sel:3; 2412d8f1f33SBen Goz uint32_t num_queues:3; 2422d8f1f33SBen Goz } bitfields2; 2432d8f1f33SBen Goz uint32_t ordinal2; 2442d8f1f33SBen Goz }; 2452d8f1f33SBen Goz 2462d8f1f33SBen Goz union { 2472d8f1f33SBen Goz struct { 2482d8f1f33SBen Goz uint32_t reserved3:1; 2492d8f1f33SBen Goz uint32_t check_disable:1; 2502d8f1f33SBen Goz uint32_t doorbell_offset:21; 2512d8f1f33SBen Goz uint32_t reserved4:3; 2522d8f1f33SBen Goz uint32_t queue:6; 2532d8f1f33SBen Goz } bitfields3; 2542d8f1f33SBen Goz uint32_t ordinal3; 2552d8f1f33SBen Goz }; 2562d8f1f33SBen Goz 2572d8f1f33SBen Goz uint32_t mqd_addr_lo; 2582d8f1f33SBen Goz uint32_t mqd_addr_hi; 2592d8f1f33SBen Goz uint32_t wptr_addr_lo; 2602d8f1f33SBen Goz uint32_t wptr_addr_hi; 2612d8f1f33SBen Goz }; 2622d8f1f33SBen Goz #endif 2632d8f1f33SBen Goz 2642d8f1f33SBen Goz /*--------------------MES_QUERY_STATUS--------------------*/ 2652d8f1f33SBen Goz 2662d8f1f33SBen Goz #ifndef PM4_MES_QUERY_STATUS_DEFINED 2672d8f1f33SBen Goz #define PM4_MES_QUERY_STATUS_DEFINED 2682d8f1f33SBen Goz enum mes_query_status_interrupt_sel_enum { 2692d8f1f33SBen Goz interrupt_sel__mes_query_status__completion_status = 0, 2702d8f1f33SBen Goz interrupt_sel__mes_query_status__process_status = 1, 2712d8f1f33SBen Goz interrupt_sel__mes_query_status__queue_status = 2 2722d8f1f33SBen Goz }; 2732d8f1f33SBen Goz 2742d8f1f33SBen Goz enum mes_query_status_command_enum { 2752d8f1f33SBen Goz command__mes_query_status__interrupt_only = 0, 2762d8f1f33SBen Goz command__mes_query_status__fence_only_immediate = 1, 2772d8f1f33SBen Goz command__mes_query_status__fence_only_after_write_ack = 2, 2782d8f1f33SBen Goz command__mes_query_status__fence_wait_for_write_ack_send_interrupt = 3 2792d8f1f33SBen Goz }; 2802d8f1f33SBen Goz 2812d8f1f33SBen Goz enum mes_query_status_engine_sel_enum { 2822d8f1f33SBen Goz engine_sel__mes_query_status__compute = 0, 2832d8f1f33SBen Goz engine_sel__mes_query_status__sdma0_queue = 2, 2842d8f1f33SBen Goz engine_sel__mes_query_status__sdma1_queue = 3 2852d8f1f33SBen Goz }; 2862d8f1f33SBen Goz 2872d8f1f33SBen Goz struct pm4_mes_query_status { 2882d8f1f33SBen Goz union { 2892d8f1f33SBen Goz union PM4_MES_TYPE_3_HEADER header; /* header */ 2902d8f1f33SBen Goz uint32_t ordinal1; 2912d8f1f33SBen Goz }; 2922d8f1f33SBen Goz 2932d8f1f33SBen Goz union { 2942d8f1f33SBen Goz struct { 2952d8f1f33SBen Goz uint32_t context_id:28; 2962d8f1f33SBen Goz enum mes_query_status_interrupt_sel_enum 2972d8f1f33SBen Goz interrupt_sel:2; 2982d8f1f33SBen Goz enum mes_query_status_command_enum command:2; 2992d8f1f33SBen Goz } bitfields2; 3002d8f1f33SBen Goz uint32_t ordinal2; 3012d8f1f33SBen Goz }; 3022d8f1f33SBen Goz 3032d8f1f33SBen Goz union { 3042d8f1f33SBen Goz struct { 3052d8f1f33SBen Goz uint32_t pasid:16; 3062d8f1f33SBen Goz uint32_t reserved1:16; 3072d8f1f33SBen Goz } bitfields3a; 3082d8f1f33SBen Goz struct { 3092d8f1f33SBen Goz uint32_t reserved2:2; 3102d8f1f33SBen Goz uint32_t doorbell_offset:21; 3112d8f1f33SBen Goz uint32_t reserved3:2; 3122d8f1f33SBen Goz enum mes_query_status_engine_sel_enum engine_sel:3; 3132d8f1f33SBen Goz uint32_t reserved4:4; 3142d8f1f33SBen Goz } bitfields3b; 3152d8f1f33SBen Goz uint32_t ordinal3; 3162d8f1f33SBen Goz }; 3172d8f1f33SBen Goz 3182d8f1f33SBen Goz uint32_t addr_lo; 3192d8f1f33SBen Goz uint32_t addr_hi; 3202d8f1f33SBen Goz uint32_t data_lo; 3212d8f1f33SBen Goz uint32_t data_hi; 3222d8f1f33SBen Goz }; 3232d8f1f33SBen Goz #endif 3242d8f1f33SBen Goz 3252d8f1f33SBen Goz /*--------------------MES_UNMAP_QUEUES--------------------*/ 3262d8f1f33SBen Goz 3272d8f1f33SBen Goz #ifndef PM4_MES_UNMAP_QUEUES_DEFINED 3282d8f1f33SBen Goz #define PM4_MES_UNMAP_QUEUES_DEFINED 3292d8f1f33SBen Goz enum mes_unmap_queues_action_enum { 3302d8f1f33SBen Goz action__mes_unmap_queues__preempt_queues = 0, 3312d8f1f33SBen Goz action__mes_unmap_queues__reset_queues = 1, 3322d8f1f33SBen Goz action__mes_unmap_queues__disable_process_queues = 2, 3332d8f1f33SBen Goz action__mes_unmap_queues__reserved = 3 3342d8f1f33SBen Goz }; 3352d8f1f33SBen Goz 3362d8f1f33SBen Goz enum mes_unmap_queues_queue_sel_enum { 3372d8f1f33SBen Goz queue_sel__mes_unmap_queues__perform_request_on_specified_queues = 0, 3382d8f1f33SBen Goz queue_sel__mes_unmap_queues__perform_request_on_pasid_queues = 1, 3392d8f1f33SBen Goz queue_sel__mes_unmap_queues__unmap_all_queues = 2, 3402d8f1f33SBen Goz queue_sel__mes_unmap_queues__unmap_all_non_static_queues = 3 3412d8f1f33SBen Goz }; 3422d8f1f33SBen Goz 3432d8f1f33SBen Goz enum mes_unmap_queues_engine_sel_enum { 3442d8f1f33SBen Goz engine_sel__mes_unmap_queues__compute = 0, 3452d8f1f33SBen Goz engine_sel__mes_unmap_queues__sdma0 = 2, 3462d8f1f33SBen Goz engine_sel__mes_unmap_queues__sdmal = 3 3472d8f1f33SBen Goz }; 3482d8f1f33SBen Goz 349507968ddSFelix Kuehling struct pm4_mes_unmap_queues { 3502d8f1f33SBen Goz union { 3512d8f1f33SBen Goz union PM4_MES_TYPE_3_HEADER header; /* header */ 3522d8f1f33SBen Goz uint32_t ordinal1; 3532d8f1f33SBen Goz }; 3542d8f1f33SBen Goz 3552d8f1f33SBen Goz union { 3562d8f1f33SBen Goz struct { 3572d8f1f33SBen Goz enum mes_unmap_queues_action_enum action:2; 3582d8f1f33SBen Goz uint32_t reserved1:2; 3592d8f1f33SBen Goz enum mes_unmap_queues_queue_sel_enum queue_sel:2; 3602d8f1f33SBen Goz uint32_t reserved2:20; 3612d8f1f33SBen Goz enum mes_unmap_queues_engine_sel_enum engine_sel:3; 3622d8f1f33SBen Goz uint32_t num_queues:3; 3632d8f1f33SBen Goz } bitfields2; 3642d8f1f33SBen Goz uint32_t ordinal2; 3652d8f1f33SBen Goz }; 3662d8f1f33SBen Goz 3672d8f1f33SBen Goz union { 3682d8f1f33SBen Goz struct { 3692d8f1f33SBen Goz uint32_t pasid:16; 3702d8f1f33SBen Goz uint32_t reserved3:16; 3712d8f1f33SBen Goz } bitfields3a; 3722d8f1f33SBen Goz struct { 3732d8f1f33SBen Goz uint32_t reserved4:2; 3742d8f1f33SBen Goz uint32_t doorbell_offset0:21; 3752d8f1f33SBen Goz uint32_t reserved5:9; 3762d8f1f33SBen Goz } bitfields3b; 3772d8f1f33SBen Goz uint32_t ordinal3; 3782d8f1f33SBen Goz }; 3792d8f1f33SBen Goz 3802d8f1f33SBen Goz union { 3812d8f1f33SBen Goz struct { 3822d8f1f33SBen Goz uint32_t reserved6:2; 3832d8f1f33SBen Goz uint32_t doorbell_offset1:21; 3842d8f1f33SBen Goz uint32_t reserved7:9; 3852d8f1f33SBen Goz } bitfields4; 3862d8f1f33SBen Goz uint32_t ordinal4; 3872d8f1f33SBen Goz }; 3882d8f1f33SBen Goz 3892d8f1f33SBen Goz union { 3902d8f1f33SBen Goz struct { 3912d8f1f33SBen Goz uint32_t reserved8:2; 3922d8f1f33SBen Goz uint32_t doorbell_offset2:21; 3932d8f1f33SBen Goz uint32_t reserved9:9; 3942d8f1f33SBen Goz } bitfields5; 3952d8f1f33SBen Goz uint32_t ordinal5; 3962d8f1f33SBen Goz }; 3972d8f1f33SBen Goz 3982d8f1f33SBen Goz union { 3992d8f1f33SBen Goz struct { 4002d8f1f33SBen Goz uint32_t reserved10:2; 4012d8f1f33SBen Goz uint32_t doorbell_offset3:21; 4022d8f1f33SBen Goz uint32_t reserved11:9; 4032d8f1f33SBen Goz } bitfields6; 4042d8f1f33SBen Goz uint32_t ordinal6; 4052d8f1f33SBen Goz }; 4062d8f1f33SBen Goz }; 4072d8f1f33SBen Goz #endif 4082d8f1f33SBen Goz 409507968ddSFelix Kuehling #ifndef PM4_MEC_RELEASE_MEM_DEFINED 410507968ddSFelix Kuehling #define PM4_MEC_RELEASE_MEM_DEFINED 411507968ddSFelix Kuehling enum RELEASE_MEM_event_index_enum { 412507968ddSFelix Kuehling event_index___release_mem__end_of_pipe = 5, 413507968ddSFelix Kuehling event_index___release_mem__shader_done = 6 414507968ddSFelix Kuehling }; 415507968ddSFelix Kuehling 416507968ddSFelix Kuehling enum RELEASE_MEM_cache_policy_enum { 417507968ddSFelix Kuehling cache_policy___release_mem__lru = 0, 418507968ddSFelix Kuehling cache_policy___release_mem__stream = 1, 419507968ddSFelix Kuehling cache_policy___release_mem__bypass = 2 420507968ddSFelix Kuehling }; 421507968ddSFelix Kuehling 422507968ddSFelix Kuehling enum RELEASE_MEM_dst_sel_enum { 423507968ddSFelix Kuehling dst_sel___release_mem__memory_controller = 0, 424507968ddSFelix Kuehling dst_sel___release_mem__tc_l2 = 1, 425507968ddSFelix Kuehling dst_sel___release_mem__queue_write_pointer_register = 2, 426507968ddSFelix Kuehling dst_sel___release_mem__queue_write_pointer_poll_mask_bit = 3 427507968ddSFelix Kuehling }; 428507968ddSFelix Kuehling 429507968ddSFelix Kuehling enum RELEASE_MEM_int_sel_enum { 430507968ddSFelix Kuehling int_sel___release_mem__none = 0, 431507968ddSFelix Kuehling int_sel___release_mem__send_interrupt_only = 1, 432507968ddSFelix Kuehling int_sel___release_mem__send_interrupt_after_write_confirm = 2, 433507968ddSFelix Kuehling int_sel___release_mem__send_data_after_write_confirm = 3 434507968ddSFelix Kuehling }; 435507968ddSFelix Kuehling 436507968ddSFelix Kuehling enum RELEASE_MEM_data_sel_enum { 437507968ddSFelix Kuehling data_sel___release_mem__none = 0, 438507968ddSFelix Kuehling data_sel___release_mem__send_32_bit_low = 1, 439507968ddSFelix Kuehling data_sel___release_mem__send_64_bit_data = 2, 440507968ddSFelix Kuehling data_sel___release_mem__send_gpu_clock_counter = 3, 441507968ddSFelix Kuehling data_sel___release_mem__send_cp_perfcounter_hi_lo = 4, 442507968ddSFelix Kuehling data_sel___release_mem__store_gds_data_to_memory = 5 443507968ddSFelix Kuehling }; 444507968ddSFelix Kuehling 445507968ddSFelix Kuehling struct pm4_mec_release_mem { 446507968ddSFelix Kuehling union { 447507968ddSFelix Kuehling union PM4_MES_TYPE_3_HEADER header; /*header */ 448507968ddSFelix Kuehling unsigned int ordinal1; 449507968ddSFelix Kuehling }; 450507968ddSFelix Kuehling 451507968ddSFelix Kuehling union { 452507968ddSFelix Kuehling struct { 453507968ddSFelix Kuehling unsigned int event_type:6; 454507968ddSFelix Kuehling unsigned int reserved1:2; 455507968ddSFelix Kuehling enum RELEASE_MEM_event_index_enum event_index:4; 456507968ddSFelix Kuehling unsigned int tcl1_vol_action_ena:1; 457507968ddSFelix Kuehling unsigned int tc_vol_action_ena:1; 458507968ddSFelix Kuehling unsigned int reserved2:1; 459507968ddSFelix Kuehling unsigned int tc_wb_action_ena:1; 460507968ddSFelix Kuehling unsigned int tcl1_action_ena:1; 461507968ddSFelix Kuehling unsigned int tc_action_ena:1; 462507968ddSFelix Kuehling unsigned int reserved3:6; 463507968ddSFelix Kuehling unsigned int atc:1; 464507968ddSFelix Kuehling enum RELEASE_MEM_cache_policy_enum cache_policy:2; 465507968ddSFelix Kuehling unsigned int reserved4:5; 466507968ddSFelix Kuehling } bitfields2; 467507968ddSFelix Kuehling unsigned int ordinal2; 468507968ddSFelix Kuehling }; 469507968ddSFelix Kuehling 470507968ddSFelix Kuehling union { 471507968ddSFelix Kuehling struct { 472507968ddSFelix Kuehling unsigned int reserved5:16; 473507968ddSFelix Kuehling enum RELEASE_MEM_dst_sel_enum dst_sel:2; 474507968ddSFelix Kuehling unsigned int reserved6:6; 475507968ddSFelix Kuehling enum RELEASE_MEM_int_sel_enum int_sel:3; 476507968ddSFelix Kuehling unsigned int reserved7:2; 477507968ddSFelix Kuehling enum RELEASE_MEM_data_sel_enum data_sel:3; 478507968ddSFelix Kuehling } bitfields3; 479507968ddSFelix Kuehling unsigned int ordinal3; 480507968ddSFelix Kuehling }; 481507968ddSFelix Kuehling 482507968ddSFelix Kuehling union { 483507968ddSFelix Kuehling struct { 484507968ddSFelix Kuehling unsigned int reserved8:2; 485507968ddSFelix Kuehling unsigned int address_lo_32b:30; 486507968ddSFelix Kuehling } bitfields4; 487507968ddSFelix Kuehling struct { 488507968ddSFelix Kuehling unsigned int reserved9:3; 489507968ddSFelix Kuehling unsigned int address_lo_64b:29; 490507968ddSFelix Kuehling } bitfields5; 491507968ddSFelix Kuehling unsigned int ordinal4; 492507968ddSFelix Kuehling }; 493507968ddSFelix Kuehling 494507968ddSFelix Kuehling unsigned int address_hi; 495507968ddSFelix Kuehling 496507968ddSFelix Kuehling unsigned int data_lo; 497507968ddSFelix Kuehling 498507968ddSFelix Kuehling unsigned int data_hi; 499507968ddSFelix Kuehling }; 500507968ddSFelix Kuehling #endif 501507968ddSFelix Kuehling 502507968ddSFelix Kuehling enum { 503507968ddSFelix Kuehling CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000014 504507968ddSFelix Kuehling }; 505507968ddSFelix Kuehling 5062d8f1f33SBen Goz #endif 507