Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79, v6.0.8, v5.15.78, v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4, v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71, v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64, v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58, v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48, v5.15.47, v5.15.46, v5.15.45, v5.15.44, v5.15.43, v5.15.42, v5.18, v5.15.41, v5.15.40, v5.15.39, v5.15.38 |
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#
e0f85f46 |
| 06-May-2022 |
Jonathan Kim <jonathan.kim@amd.com> |
drm/amdkfd: add debug set and clear address watch points operation
Shader read, write and atomic memory operations can be alerted to the debugger as an address watch exception.
Allow the debugger t
drm/amdkfd: add debug set and clear address watch points operation
Shader read, write and atomic memory operations can be alerted to the debugger as an address watch exception.
Allow the debugger to pass in a watch point to a particular memory address per device.
Note that there exists only 4 watch points per devices to date, so have the KFD keep track of what watch points are allocated or not.
Signed-off-by: Jonathan Kim <jonathan.kim@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
aea1b473 |
| 02-May-2022 |
Jonathan Kim <jonathan.kim@amd.com> |
drm/amdkfd: add debug wave launch mode operation
Allow the debugger to set wave behaviour on to either normally operate, halt at launch, trap on every instruction, terminate immediately or stall on
drm/amdkfd: add debug wave launch mode operation
Allow the debugger to set wave behaviour on to either normally operate, halt at launch, trap on every instruction, terminate immediately or stall on allocation.
Signed-off-by: Jonathan Kim <jonathan.kim@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.15.37 |
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#
101827e1 |
| 27-Apr-2022 |
Jonathan Kim <jonathan.kim@amd.com> |
drm/amdkfd: add debug wave launch override operation
This operation allows the debugger to override the enabled HW exceptions on the device.
On debug devices that only support the debugging of a si
drm/amdkfd: add debug wave launch override operation
This operation allows the debugger to override the enabled HW exceptions on the device.
On debug devices that only support the debugging of a single process, the HW exceptions are global and set through the SPI_GDBG_TRAP_MASK register. Because they are global, only address watch exceptions are allowed to be enabled. In other words, the debugger must preserve all non-address watch exception states in normal mode operation by barring a full replacement override or a non-address watch override request.
For multi-process debugging, all HW exception overrides are per-VMID so all exceptions can be overridden or fully replaced.
In order for the debugger to know what is permissible, returned the supported override mask back to the debugger along with the previously enable overrides.
Signed-off-by: Jonathan Kim <jonathan.kim@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
7cee6a68 |
| 23-Mar-2023 |
Jonathan Kim <jonathan.kim@amd.com> |
drm/amdgpu: add configurable grace period for unmap queues
The HWS schedule allows a grace period for wave completion prior to preemption for better performance by avoiding CWSR on waves that can po
drm/amdgpu: add configurable grace period for unmap queues
The HWS schedule allows a grace period for wave completion prior to preemption for better performance by avoiding CWSR on waves that can potentially complete quickly. The debugger, on the other hand, will want to inspect wave status immediately after it actively triggers preemption (a suspend function to be provided).
To minimize latency between preemption and debugger wave inspection, allow immediate preemption by setting the grace period to 0.
Note that setting the preepmtion grace period to 0 will result in an infinite grace period being set due to a CP FW bug so set it to 1 for now.
Signed-off-by: Jonathan Kim <jonathan.kim@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.15.36, v5.15.35, v5.15.34, v5.15.33 |
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#
d13f050f |
| 31-Mar-2022 |
Jonathan Kim <jonathan.kim@amd.com> |
drm/amdgpu: add gfx10 hw debug mode enable and disable calls
Similar to GFX9 debug devices, set the hardware debug mode by draining the SPI appropriately prior the mode setting request.
Because GFX
drm/amdgpu: add gfx10 hw debug mode enable and disable calls
Similar to GFX9 debug devices, set the hardware debug mode by draining the SPI appropriately prior the mode setting request.
Because GFX10 has waves allocated by the work group boundary and each SE's SPI instances do not communicate, the SPI drain time is much longer. This long drain time will be fixed for GFX11 onwards.
Also remove a bunch of deprecated misplaced references for GFX10.3.
Signed-off-by: Jonathan Kim <jonathan.kim@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e2069a7b |
| 09-May-2022 |
Mukul Joshi <mukul.joshi@amd.com> |
drm/amdkfd: Add XCC instance to kgd2kfd interface (v3)
Gfx 9 starts to have multiple XCC instances in one device. Add instance parameter to kgd2kfd functions where XCC instance was hard coded as 0.
drm/amdkfd: Add XCC instance to kgd2kfd interface (v3)
Gfx 9 starts to have multiple XCC instances in one device. Add instance parameter to kgd2kfd functions where XCC instance was hard coded as 0. Also, update code to pass the correct instance number when running on a multi-XCC setup.
v2: introduce the XCC instance to gfx v11 (Morris) v3: rebase (Alex)
Signed-off-by: Amber Lin <Amber.Lin@amd.com> Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Tested-by: Amber Lin <Amber.Lin@amd.com> Signed-off-by: Morris Zhang <Shiwu.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
277bd337 |
| 23-May-2022 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: convert gfx.kiq to array type (v3)
v1: more kiq instances are a available in SOC (Le) v2: squash commits to avoid breaking the build (Le) v3: make the conversion for gfx/mec v11_0 (Hawki
drm/amdgpu: convert gfx.kiq to array type (v3)
v1: more kiq instances are a available in SOC (Le) v2: squash commits to avoid breaking the build (Le) v3: make the conversion for gfx/mec v11_0 (Hawking)
Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.15.32, v5.15.31, v5.17, v5.15.30, v5.15.29, v5.15.28, v5.15.27 |
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#
b664a56e |
| 03-Mar-2022 |
Yifan Zhang <yifan1.zhang@amd.com> |
drm/amdkfd: implement get_atc_vmid_pasid_mapping_info for gfx10.3
This patch implements get_atc_vmid_pasid_mapping_info for gfx10.3
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Al
drm/amdkfd: implement get_atc_vmid_pasid_mapping_info for gfx10.3
This patch implements get_atc_vmid_pasid_mapping_info for gfx10.3
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.15.26, v5.15.25, v5.15.24, v5.15.23, v5.15.22, v5.15.21, v5.15.20 |
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#
5bdd3eb2 |
| 04-Feb-2022 |
Mukul Joshi <mukul.joshi@amd.com> |
drm/amdkfd: Remove unused old debugger implementation
Cleanup the kfd code by removing the unused old debugger implementation. The address watch was only ever implemented in the upstream driver for
drm/amdkfd: Remove unused old debugger implementation
Cleanup the kfd code by removing the unused old debugger implementation. The address watch was only ever implemented in the upstream driver for GFXv7 (Kaveri). The user mode tools runtime using this API was never open-sourced. Work on the old debugger prototype that used this API has been discontinued years ago. Only a small piece of resetting wavefronts is kept and is moved to kfd_device_queue_manager.c.
Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.15.19, v5.15.18, v5.15.17, v5.4.173, v5.15.16, v5.15.15, v5.16, v5.15.10, v5.15.9, v5.15.8, v5.15.7, v5.15.6, v5.15.5, v5.15.4, v5.15.3, v5.15.2, v5.15.1, v5.15, v5.14.14 |
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#
56c5977e |
| 19-Oct-2021 |
Graham Sider <Graham.Sider@amd.com> |
drm/amdkfd: replace/remove remaining kgd_dev references
Remove get_amdgpu_device and other remaining kgd_dev references aside from declaration/kfd struct entry and initialization.
Signed-off-by: Gr
drm/amdkfd: replace/remove remaining kgd_dev references
Remove get_amdgpu_device and other remaining kgd_dev references aside from declaration/kfd struct entry and initialization.
Signed-off-by: Graham Sider <Graham.Sider@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.14.13 |
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#
3356c38d |
| 14-Oct-2021 |
Graham Sider <Graham.Sider@amd.com> |
drm/amdkfd: replace kgd_dev in various kfd2kgd funcs
Modified definitions:
- program_sh_mem_settings - set_pasid_vmid_mapping - init_interrupts - address_watch_disable - address_watch_execute - wav
drm/amdkfd: replace kgd_dev in various kfd2kgd funcs
Modified definitions:
- program_sh_mem_settings - set_pasid_vmid_mapping - init_interrupts - address_watch_disable - address_watch_execute - wave_control_execute - address_watch_get_offset - get_atc_vmid_pasid_mapping_info - set_scratch_backing_va - set_vm_context_page_table_base - read_vmid_from_vmfault_reg - get_cu_occupancy - program_trap_handler_settings
Signed-off-by: Graham Sider <Graham.Sider@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
420185fd |
| 15-Oct-2021 |
Graham Sider <Graham.Sider@amd.com> |
drm/amdkfd: replace kgd_dev in hqd/mqd kfd2kgd funcs
Modified definitions:
- hqd_load - hiq_mqd_load - hqd_sdma_load - hqd_dump - hqd_sdma_dump - hqd_is_occupied - hqd_destroy - hqd_sdma_is_occupie
drm/amdkfd: replace kgd_dev in hqd/mqd kfd2kgd funcs
Modified definitions:
- hqd_load - hiq_mqd_load - hqd_sdma_load - hqd_dump - hqd_sdma_dump - hqd_is_occupied - hqd_destroy - hqd_sdma_is_occupied - hqd_sdma_destroy
Signed-off-by: Graham Sider <Graham.Sider@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c531a58b |
| 14-Oct-2021 |
Graham Sider <Graham.Sider@amd.com> |
drm/amdkfd: replace kgd_dev in static gfx v10_3 funcs
Static funcs in amdgpu_amdkfd_gfx_v10_3.c now using amdgpu_device.
Signed-off-by: Graham Sider <Graham.Sider@amd.com> Reviewed-by: Felix Kuehli
drm/amdkfd: replace kgd_dev in static gfx v10_3 funcs
Static funcs in amdgpu_amdkfd_gfx_v10_3.c now using amdgpu_device.
Signed-off-by: Graham Sider <Graham.Sider@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.14.12, v5.14.11, v5.14.10, v5.14.9, v5.14.8, v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5, v5.14.4, v5.10.65, v5.14.3, v5.10.64, v5.14.2, v5.10.63, v5.14.1, v5.10.62, v5.14, v5.10.61, v5.10.60 |
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#
b53ef0df |
| 09-Aug-2021 |
Mukul Joshi <mukul.joshi@amd.com> |
drm/amdkfd: CWSR with software scheduler
This patch adds support to program trap handler settings when loading driver with software scheduler (sched_policy=2).
Signed-off-by: Mukul Joshi <mukul.jos
drm/amdkfd: CWSR with software scheduler
This patch adds support to program trap handler settings when loading driver with software scheduler (sched_policy=2).
Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Suggested-by: Jay Cornwall <Jay.Cornwall@amd.com> Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.10.53, v5.10.52, v5.10.51, v5.10.50, v5.10.49, v5.13, v5.10.46, v5.10.43 |
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#
46ed43e6 |
| 04-Jun-2021 |
Rohit Khaire <rohit.khaire@amd.com> |
drm/amdgpu: Modify GC register access to use _SOC15 macros
In SRIOV environment, KMD should access GC registers with RLCG if GC indirect access flag enabled.
Using _SOC15 read/write macros ensures
drm/amdgpu: Modify GC register access to use _SOC15 macros
In SRIOV environment, KMD should access GC registers with RLCG if GC indirect access flag enabled.
Using _SOC15 read/write macros ensures that they go through RLC when flag is enabled.
Signed-off-by: Rohit Khaire <rohit.khaire@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.10.42, v5.10.41, v5.10.40, v5.10.39 |
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#
8200b1cd |
| 18-May-2021 |
Kevin Wang <kevin1.wang@amd.com> |
drm/amdkfd: correct sienna_cichlid SDMA RLC register offset error
1.correct KFD SDMA RLC queue register offset error. (all sdma rlc register offset is base on SDMA0.RLC0_RLC0_RB_CNTL) 2.HQD_N_REGS (
drm/amdkfd: correct sienna_cichlid SDMA RLC register offset error
1.correct KFD SDMA RLC queue register offset error. (all sdma rlc register offset is base on SDMA0.RLC0_RLC0_RB_CNTL) 2.HQD_N_REGS (19+6+7+12) 12: the 2 more resgisters than navi1x (SDMAx_RLCy_MIDCMD_DATA{9,10})
the patch also can be fixed NULL pointer issue when read /sys/kernel/debug/kfd/hqds on sienna_cichlid chip.
Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ba515a58 |
| 18-May-2021 |
Kevin Wang <kevin1.wang@amd.com> |
drm/amdkfd: correct sienna_cichlid SDMA RLC register offset error
1.correct KFD SDMA RLC queue register offset error. (all sdma rlc register offset is base on SDMA0.RLC0_RLC0_RB_CNTL) 2.HQD_N_REGS (
drm/amdkfd: correct sienna_cichlid SDMA RLC register offset error
1.correct KFD SDMA RLC queue register offset error. (all sdma rlc register offset is base on SDMA0.RLC0_RLC0_RB_CNTL) 2.HQD_N_REGS (19+6+7+12) 12: the 2 more resgisters than navi1x (SDMAx_RLCy_MIDCMD_DATA{9,10})
the patch also can be fixed NULL pointer issue when read /sys/kernel/debug/kfd/hqds on sienna_cichlid chip.
Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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Revision tags: v5.4.119, v5.10.36, v5.10.35, v5.10.34, v5.4.116, v5.10.33, v5.12, v5.10.32, v5.10.31, v5.10.30, v5.10.27, v5.10.26, v5.10.25, v5.10.24, v5.10.23, v5.10.22, v5.10.21, v5.10.20, v5.10.19, v5.4.101, v5.10.18, v5.10.17, v5.11, v5.10.16, v5.10.15, v5.10.14 |
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#
beea33e1 |
| 04-Jan-2021 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: remove redundant include of navi10_enum
Remove unnecessary include of navi10_enum header file.
Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd
drm/amdgpu: remove redundant include of navi10_enum
Remove unnecessary include of navi10_enum header file.
Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
01abf691 |
| 18-May-2021 |
Kevin Wang <kevin1.wang@amd.com> |
drm/amdkfd: correct sienna_cichlid SDMA RLC register offset error
commit ba515a5821dc0d101ded0379b14b1d1471ebfaba upstream.
1.correct KFD SDMA RLC queue register offset error. (all sdma rlc registe
drm/amdkfd: correct sienna_cichlid SDMA RLC register offset error
commit ba515a5821dc0d101ded0379b14b1d1471ebfaba upstream.
1.correct KFD SDMA RLC queue register offset error. (all sdma rlc register offset is base on SDMA0.RLC0_RLC0_RB_CNTL) 2.HQD_N_REGS (19+6+7+12) 12: the 2 more resgisters than navi1x (SDMAx_RLCy_MIDCMD_DATA{9,10})
the patch also can be fixed NULL pointer issue when read /sys/kernel/debug/kfd/hqds on sienna_cichlid chip.
Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Revision tags: v5.10, v5.8.17, v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11 |
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#
8ffff9b4 |
| 17-Sep-2020 |
Oak Zeng <Oak.Zeng@amd.com> |
drm/amdgpu: use function pointer for gfxhub functions
gfxhub functions are now called from function pointers, instead of from asic-specific functions.
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Rev
drm/amdgpu: use function pointer for gfxhub functions
gfxhub functions are now called from function pointers, instead of from asic-specific functions.
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.8.10, v5.8.9, v5.8.8, v5.8.7, v5.8.6, v5.4.62, v5.8.5, v5.8.4, v5.4.61 |
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#
332f6e1e |
| 24-Aug-2020 |
Felix Kuehling <Felix.Kuehling@amd.com> |
drm/amdkfd: call amdgpu_amdkfd_get_hive_id directly
No need to use a function pointer because the implementation is not ASIC-specific.
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewe
drm/amdkfd: call amdgpu_amdkfd_get_hive_id directly
No need to use a function pointer because the implementation is not ASIC-specific.
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
df561f66 |
| 23-Aug-2020 |
Gustavo A. R. Silva <gustavoars@kernel.org> |
treewide: Use fallthrough pseudo-keyword
Replace the existing /* fall through */ comments and its variants with the new pseudo-keyword macro fallthrough[1]. Also, remove unnecessary fall-through mar
treewide: Use fallthrough pseudo-keyword
Replace the existing /* fall through */ comments and its variants with the new pseudo-keyword macro fallthrough[1]. Also, remove unnecessary fall-through markings when it is the case.
[1] https://www.kernel.org/doc/html/v5.7/process/deprecated.html?highlight=fallthrough#implicit-switch-case-fall-through
Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org>
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Revision tags: v5.8.3, v5.4.60, v5.8.2, v5.4.59, v5.8.1, v5.4.58, v5.4.57, v5.4.56, v5.8, v5.7.12, v5.4.55, v5.7.11, v5.4.54, v5.7.10, v5.4.53, v5.4.52, v5.7.9, v5.7.8, v5.4.51, v5.4.50, v5.7.7, v5.4.49, v5.7.6, v5.7.5, v5.4.48, v5.7.4, v5.7.3, v5.4.47, v5.4.46, v5.7.2, v5.4.45, v5.7.1, v5.4.44, v5.7, v5.4.43, v5.4.42, v5.4.41, v5.4.40, v5.4.39, v5.4.38, v5.4.37, v5.4.36, v5.4.35, v5.4.34, v5.4.33, v5.4.32, v5.4.31, v5.4.30, v5.4.29, v5.6, v5.4.28, v5.4.27, v5.4.26, v5.4.25, v5.4.24, v5.4.23, v5.4.22, v5.4.21, v5.4.20, v5.4.19, v5.4.18, v5.4.17, v5.4.16, v5.5, v5.4.15, v5.4.14, v5.4.13, v5.4.12, v5.4.11, v5.4.10, v5.4.9, v5.4.8, v5.4.7, v5.4.6, v5.4.5, v5.4.4, v5.4.3, v5.3.15, v5.4.2, v5.4.1, v5.3.14, v5.4, v5.3.13, v5.3.12, v5.3.11, v5.3.10, v5.3.9, v5.3.8, v5.3.7, v5.3.6, v5.3.5, v5.3.4, v5.3.3 |
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3a2f0c81 |
| 01-Oct-2019 |
Yong Zhao <Yong.Zhao@amd.com> |
drm/amdkfd: Support Sienna_Cichlid KFD v4
v4: drop get_tile_config, comment out other callbacks
Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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01abf691 |
| 18-May-2021 |
Kevin Wang <kevin1.wang@amd.com> |
drm/amdkfd: correct sienna_cichlid SDMA RLC register offset error commit ba515a5821dc0d101ded0379b14b1d1471ebfaba upstream. 1.correct KFD SDMA RLC queue register offset error. (
drm/amdkfd: correct sienna_cichlid SDMA RLC register offset error commit ba515a5821dc0d101ded0379b14b1d1471ebfaba upstream. 1.correct KFD SDMA RLC queue register offset error. (all sdma rlc register offset is base on SDMA0.RLC0_RLC0_RB_CNTL) 2.HQD_N_REGS (19+6+7+12) 12: the 2 more resgisters than navi1x (SDMAx_RLCy_MIDCMD_DATA{9,10}) the patch also can be fixed NULL pointer issue when read /sys/kernel/debug/kfd/hqds on sienna_cichlid chip. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Revision tags: v5.10, v5.8.17, v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11 |
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8ffff9b4 |
| 17-Sep-2020 |
Oak Zeng <Oak.Zeng@amd.com> |
drm/amdgpu: use function pointer for gfxhub functions gfxhub functions are now called from function pointers, instead of from asic-specific functions. Signed-off-by: Oak Zeng <O
drm/amdgpu: use function pointer for gfxhub functions gfxhub functions are now called from function pointers, instead of from asic-specific functions. Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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