1d87f36a0SRajneesh Bhardwaj // SPDX-License-Identifier: GPL-2.0 OR MIT
2594d0c90SYong Zhao /*
3d87f36a0SRajneesh Bhardwaj * Copyright 2016-2022 Advanced Micro Devices, Inc.
4594d0c90SYong Zhao *
5594d0c90SYong Zhao * Permission is hereby granted, free of charge, to any person obtaining a
6594d0c90SYong Zhao * copy of this software and associated documentation files (the "Software"),
7594d0c90SYong Zhao * to deal in the Software without restriction, including without limitation
8594d0c90SYong Zhao * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9594d0c90SYong Zhao * and/or sell copies of the Software, and to permit persons to whom the
10594d0c90SYong Zhao * Software is furnished to do so, subject to the following conditions:
11594d0c90SYong Zhao *
12594d0c90SYong Zhao * The above copyright notice and this permission notice shall be included in
13594d0c90SYong Zhao * all copies or substantial portions of the Software.
14594d0c90SYong Zhao *
15594d0c90SYong Zhao * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16594d0c90SYong Zhao * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17594d0c90SYong Zhao * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18594d0c90SYong Zhao * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19594d0c90SYong Zhao * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20594d0c90SYong Zhao * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21594d0c90SYong Zhao * OTHER DEALINGS IN THE SOFTWARE.
22594d0c90SYong Zhao *
23594d0c90SYong Zhao */
24594d0c90SYong Zhao
25594d0c90SYong Zhao #include "kfd_kernel_queue.h"
26594d0c90SYong Zhao #include "kfd_device_queue_manager.h"
27594d0c90SYong Zhao #include "kfd_pm4_headers_ai.h"
28fd6a440eSJonathan Kim #include "kfd_pm4_headers_aldebaran.h"
29594d0c90SYong Zhao #include "kfd_pm4_opcodes.h"
30594d0c90SYong Zhao #include "gc/gc_10_1_0_sh_mask.h"
31594d0c90SYong Zhao
pm_map_process_v9(struct packet_manager * pm,uint32_t * buffer,struct qcm_process_device * qpd)32594d0c90SYong Zhao static int pm_map_process_v9(struct packet_manager *pm,
33594d0c90SYong Zhao uint32_t *buffer, struct qcm_process_device *qpd)
34594d0c90SYong Zhao {
35594d0c90SYong Zhao struct pm4_mes_map_process *packet;
36594d0c90SYong Zhao uint64_t vm_page_table_base_addr = qpd->page_table_base;
3797ae3c8cSJonathan Kim struct kfd_node *kfd = pm->dqm->dev;
3897ae3c8cSJonathan Kim struct kfd_process_device *pdd =
3997ae3c8cSJonathan Kim container_of(qpd, struct kfd_process_device, qpd);
40594d0c90SYong Zhao
41594d0c90SYong Zhao packet = (struct pm4_mes_map_process *)buffer;
42594d0c90SYong Zhao memset(buffer, 0, sizeof(struct pm4_mes_map_process));
43594d0c90SYong Zhao packet->header.u32All = pm_build_pm4_header(IT_MAP_PROCESS,
44594d0c90SYong Zhao sizeof(struct pm4_mes_map_process));
45594d0c90SYong Zhao packet->bitfields2.diq_enable = (qpd->is_debug) ? 1 : 0;
465d7c6f18SJoseph Greathouse packet->bitfields2.process_quantum = 10;
47594d0c90SYong Zhao packet->bitfields2.pasid = qpd->pqm->process->pasid;
48594d0c90SYong Zhao packet->bitfields14.gds_size = qpd->gds_size & 0x3F;
49594d0c90SYong Zhao packet->bitfields14.gds_size_hi = (qpd->gds_size >> 6) & 0xF;
50b8020b03SJoseph Greathouse packet->bitfields14.num_gws = (qpd->mapped_gws_queue) ? qpd->num_gws : 0;
51594d0c90SYong Zhao packet->bitfields14.num_oac = qpd->num_oac;
52594d0c90SYong Zhao packet->bitfields14.sdma_enable = 1;
53594d0c90SYong Zhao packet->bitfields14.num_queues = (qpd->is_debug) ? 0 : qpd->queue_count;
54594d0c90SYong Zhao
5597ae3c8cSJonathan Kim if (kfd->dqm->trap_debug_vmid && pdd->process->debug_trap_enabled &&
5697ae3c8cSJonathan Kim pdd->process->runtime_info.runtime_state == DEBUG_RUNTIME_STATE_ENABLED) {
5797ae3c8cSJonathan Kim packet->bitfields2.debug_vmid = kfd->dqm->trap_debug_vmid;
5897ae3c8cSJonathan Kim packet->bitfields2.new_debug = 1;
5997ae3c8cSJonathan Kim }
6097ae3c8cSJonathan Kim
61594d0c90SYong Zhao packet->sh_mem_config = qpd->sh_mem_config;
62594d0c90SYong Zhao packet->sh_mem_bases = qpd->sh_mem_bases;
63594d0c90SYong Zhao if (qpd->tba_addr) {
64594d0c90SYong Zhao packet->sq_shader_tba_lo = lower_32_bits(qpd->tba_addr >> 8);
65594d0c90SYong Zhao /* On GFX9, unlike GFX10, bit TRAP_EN of SQ_SHADER_TBA_HI is
66594d0c90SYong Zhao * not defined, so setting it won't do any harm.
67594d0c90SYong Zhao */
68594d0c90SYong Zhao packet->sq_shader_tba_hi = upper_32_bits(qpd->tba_addr >> 8)
69594d0c90SYong Zhao | 1 << SQ_SHADER_TBA_HI__TRAP_EN__SHIFT;
70594d0c90SYong Zhao
71594d0c90SYong Zhao packet->sq_shader_tma_lo = lower_32_bits(qpd->tma_addr >> 8);
72594d0c90SYong Zhao packet->sq_shader_tma_hi = upper_32_bits(qpd->tma_addr >> 8);
73594d0c90SYong Zhao }
74594d0c90SYong Zhao
75594d0c90SYong Zhao packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area);
76594d0c90SYong Zhao packet->gds_addr_hi = upper_32_bits(qpd->gds_context_area);
77594d0c90SYong Zhao
78594d0c90SYong Zhao packet->vm_context_page_table_base_addr_lo32 =
79594d0c90SYong Zhao lower_32_bits(vm_page_table_base_addr);
80594d0c90SYong Zhao packet->vm_context_page_table_base_addr_hi32 =
81594d0c90SYong Zhao upper_32_bits(vm_page_table_base_addr);
82594d0c90SYong Zhao
83594d0c90SYong Zhao return 0;
84594d0c90SYong Zhao }
85594d0c90SYong Zhao
pm_map_process_aldebaran(struct packet_manager * pm,uint32_t * buffer,struct qcm_process_device * qpd)86fd6a440eSJonathan Kim static int pm_map_process_aldebaran(struct packet_manager *pm,
87fd6a440eSJonathan Kim uint32_t *buffer, struct qcm_process_device *qpd)
88fd6a440eSJonathan Kim {
89fd6a440eSJonathan Kim struct pm4_mes_map_process_aldebaran *packet;
90fd6a440eSJonathan Kim uint64_t vm_page_table_base_addr = qpd->page_table_base;
910de4ec9aSJonathan Kim struct kfd_dev *kfd = pm->dqm->dev->kfd;
920de4ec9aSJonathan Kim struct kfd_process_device *pdd =
930de4ec9aSJonathan Kim container_of(qpd, struct kfd_process_device, qpd);
940de4ec9aSJonathan Kim int i;
95fd6a440eSJonathan Kim
96fd6a440eSJonathan Kim packet = (struct pm4_mes_map_process_aldebaran *)buffer;
97fd6a440eSJonathan Kim memset(buffer, 0, sizeof(struct pm4_mes_map_process_aldebaran));
98fd6a440eSJonathan Kim packet->header.u32All = pm_build_pm4_header(IT_MAP_PROCESS,
99fd6a440eSJonathan Kim sizeof(struct pm4_mes_map_process_aldebaran));
100fd6a440eSJonathan Kim packet->bitfields2.diq_enable = (qpd->is_debug) ? 1 : 0;
101fd6a440eSJonathan Kim packet->bitfields2.process_quantum = 10;
102fd6a440eSJonathan Kim packet->bitfields2.pasid = qpd->pqm->process->pasid;
103fd6a440eSJonathan Kim packet->bitfields14.gds_size = qpd->gds_size & 0x3F;
104fd6a440eSJonathan Kim packet->bitfields14.gds_size_hi = (qpd->gds_size >> 6) & 0xF;
105fd6a440eSJonathan Kim packet->bitfields14.num_gws = (qpd->mapped_gws_queue) ? qpd->num_gws : 0;
106fd6a440eSJonathan Kim packet->bitfields14.num_oac = qpd->num_oac;
107fd6a440eSJonathan Kim packet->bitfields14.sdma_enable = 1;
108fd6a440eSJonathan Kim packet->bitfields14.num_queues = (qpd->is_debug) ? 0 : qpd->queue_count;
1090de4ec9aSJonathan Kim packet->spi_gdbg_per_vmid_cntl = pdd->spi_dbg_override |
1100de4ec9aSJonathan Kim pdd->spi_dbg_launch_mode;
1110de4ec9aSJonathan Kim
1120de4ec9aSJonathan Kim if (pdd->process->debug_trap_enabled) {
1130de4ec9aSJonathan Kim for (i = 0; i < kfd->device_info.num_of_watch_points; i++)
1140de4ec9aSJonathan Kim packet->tcp_watch_cntl[i] = pdd->watch_points[i];
1150de4ec9aSJonathan Kim
1160de4ec9aSJonathan Kim packet->bitfields2.single_memops =
1170de4ec9aSJonathan Kim !!(pdd->process->dbg_flags & KFD_DBG_TRAP_FLAG_SINGLE_MEM_OP);
1180de4ec9aSJonathan Kim }
119fd6a440eSJonathan Kim
120fd6a440eSJonathan Kim packet->sh_mem_config = qpd->sh_mem_config;
121fd6a440eSJonathan Kim packet->sh_mem_bases = qpd->sh_mem_bases;
122fd6a440eSJonathan Kim if (qpd->tba_addr) {
123fd6a440eSJonathan Kim packet->sq_shader_tba_lo = lower_32_bits(qpd->tba_addr >> 8);
124a34cab44SJay Cornwall packet->sq_shader_tba_hi = upper_32_bits(qpd->tba_addr >> 8);
125fd6a440eSJonathan Kim packet->sq_shader_tma_lo = lower_32_bits(qpd->tma_addr >> 8);
126fd6a440eSJonathan Kim packet->sq_shader_tma_hi = upper_32_bits(qpd->tma_addr >> 8);
127fd6a440eSJonathan Kim }
128fd6a440eSJonathan Kim
129fd6a440eSJonathan Kim packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area);
130fd6a440eSJonathan Kim packet->gds_addr_hi = upper_32_bits(qpd->gds_context_area);
131fd6a440eSJonathan Kim
132fd6a440eSJonathan Kim packet->vm_context_page_table_base_addr_lo32 =
133fd6a440eSJonathan Kim lower_32_bits(vm_page_table_base_addr);
134fd6a440eSJonathan Kim packet->vm_context_page_table_base_addr_hi32 =
135fd6a440eSJonathan Kim upper_32_bits(vm_page_table_base_addr);
136fd6a440eSJonathan Kim
137fd6a440eSJonathan Kim return 0;
138fd6a440eSJonathan Kim }
139fd6a440eSJonathan Kim
pm_runlist_v9(struct packet_manager * pm,uint32_t * buffer,uint64_t ib,size_t ib_size_in_dwords,bool chain)140594d0c90SYong Zhao static int pm_runlist_v9(struct packet_manager *pm, uint32_t *buffer,
141594d0c90SYong Zhao uint64_t ib, size_t ib_size_in_dwords, bool chain)
142594d0c90SYong Zhao {
143594d0c90SYong Zhao struct pm4_mes_runlist *packet;
144594d0c90SYong Zhao
145594d0c90SYong Zhao int concurrent_proc_cnt = 0;
1468dc1db31SMukul Joshi struct kfd_node *kfd = pm->dqm->dev;
147594d0c90SYong Zhao
148594d0c90SYong Zhao /* Determine the number of processes to map together to HW:
149594d0c90SYong Zhao * it can not exceed the number of VMIDs available to the
150594d0c90SYong Zhao * scheduler, and it is determined by the smaller of the number
151594d0c90SYong Zhao * of processes in the runlist and kfd module parameter
152594d0c90SYong Zhao * hws_max_conc_proc.
153594d0c90SYong Zhao * Note: the arbitration between the number of VMIDs and
154594d0c90SYong Zhao * hws_max_conc_proc has been done in
155594d0c90SYong Zhao * kgd2kfd_device_init().
156594d0c90SYong Zhao */
157594d0c90SYong Zhao concurrent_proc_cnt = min(pm->dqm->processes_count,
158594d0c90SYong Zhao kfd->max_proc_per_quantum);
159594d0c90SYong Zhao
160594d0c90SYong Zhao packet = (struct pm4_mes_runlist *)buffer;
161594d0c90SYong Zhao
162594d0c90SYong Zhao memset(buffer, 0, sizeof(struct pm4_mes_runlist));
163594d0c90SYong Zhao packet->header.u32All = pm_build_pm4_header(IT_RUN_LIST,
164594d0c90SYong Zhao sizeof(struct pm4_mes_runlist));
165594d0c90SYong Zhao
166594d0c90SYong Zhao packet->bitfields4.ib_size = ib_size_in_dwords;
167594d0c90SYong Zhao packet->bitfields4.chain = chain ? 1 : 0;
168594d0c90SYong Zhao packet->bitfields4.offload_polling = 0;
169594d0c90SYong Zhao packet->bitfields4.chained_runlist_idle_disable = chain ? 1 : 0;
170594d0c90SYong Zhao packet->bitfields4.valid = 1;
171594d0c90SYong Zhao packet->bitfields4.process_cnt = concurrent_proc_cnt;
172594d0c90SYong Zhao packet->ordinal2 = lower_32_bits(ib);
173594d0c90SYong Zhao packet->ib_base_hi = upper_32_bits(ib);
174594d0c90SYong Zhao
175594d0c90SYong Zhao return 0;
176594d0c90SYong Zhao }
177594d0c90SYong Zhao
pm_set_resources_v9(struct packet_manager * pm,uint32_t * buffer,struct scheduling_resources * res)178594d0c90SYong Zhao static int pm_set_resources_v9(struct packet_manager *pm, uint32_t *buffer,
179594d0c90SYong Zhao struct scheduling_resources *res)
180594d0c90SYong Zhao {
181594d0c90SYong Zhao struct pm4_mes_set_resources *packet;
182594d0c90SYong Zhao
183594d0c90SYong Zhao packet = (struct pm4_mes_set_resources *)buffer;
184594d0c90SYong Zhao memset(buffer, 0, sizeof(struct pm4_mes_set_resources));
185594d0c90SYong Zhao
186594d0c90SYong Zhao packet->header.u32All = pm_build_pm4_header(IT_SET_RESOURCES,
187594d0c90SYong Zhao sizeof(struct pm4_mes_set_resources));
188594d0c90SYong Zhao
189594d0c90SYong Zhao packet->bitfields2.queue_type =
190594d0c90SYong Zhao queue_type__mes_set_resources__hsa_interface_queue_hiq;
191594d0c90SYong Zhao packet->bitfields2.vmid_mask = res->vmid_mask;
192594d0c90SYong Zhao packet->bitfields2.unmap_latency = KFD_UNMAP_LATENCY_MS / 100;
193594d0c90SYong Zhao packet->bitfields7.oac_mask = res->oac_mask;
194594d0c90SYong Zhao packet->bitfields8.gds_heap_base = res->gds_heap_base;
195594d0c90SYong Zhao packet->bitfields8.gds_heap_size = res->gds_heap_size;
196594d0c90SYong Zhao
197594d0c90SYong Zhao packet->gws_mask_lo = lower_32_bits(res->gws_mask);
198594d0c90SYong Zhao packet->gws_mask_hi = upper_32_bits(res->gws_mask);
199594d0c90SYong Zhao
200594d0c90SYong Zhao packet->queue_mask_lo = lower_32_bits(res->queue_mask);
201594d0c90SYong Zhao packet->queue_mask_hi = upper_32_bits(res->queue_mask);
202594d0c90SYong Zhao
203594d0c90SYong Zhao return 0;
204594d0c90SYong Zhao }
205594d0c90SYong Zhao
pm_use_ext_eng(struct kfd_dev * dev)206009e9a15SJonathan Kim static inline bool pm_use_ext_eng(struct kfd_dev *dev)
207009e9a15SJonathan Kim {
208009e9a15SJonathan Kim return dev->adev->ip_versions[SDMA0_HWIP][0] >= IP_VERSION(5, 2, 0);
209009e9a15SJonathan Kim }
210009e9a15SJonathan Kim
pm_map_queues_v9(struct packet_manager * pm,uint32_t * buffer,struct queue * q,bool is_static)211594d0c90SYong Zhao static int pm_map_queues_v9(struct packet_manager *pm, uint32_t *buffer,
212594d0c90SYong Zhao struct queue *q, bool is_static)
213594d0c90SYong Zhao {
214594d0c90SYong Zhao struct pm4_mes_map_queues *packet;
215594d0c90SYong Zhao bool use_static = is_static;
216594d0c90SYong Zhao
217594d0c90SYong Zhao packet = (struct pm4_mes_map_queues *)buffer;
218594d0c90SYong Zhao memset(buffer, 0, sizeof(struct pm4_mes_map_queues));
219594d0c90SYong Zhao
220594d0c90SYong Zhao packet->header.u32All = pm_build_pm4_header(IT_MAP_QUEUES,
221594d0c90SYong Zhao sizeof(struct pm4_mes_map_queues));
222594d0c90SYong Zhao packet->bitfields2.num_queues = 1;
223594d0c90SYong Zhao packet->bitfields2.queue_sel =
224594d0c90SYong Zhao queue_sel__mes_map_queues__map_to_hws_determined_queue_slots_vi;
225594d0c90SYong Zhao
226594d0c90SYong Zhao packet->bitfields2.engine_sel =
227594d0c90SYong Zhao engine_sel__mes_map_queues__compute_vi;
228594d0c90SYong Zhao packet->bitfields2.gws_control_queue = q->gws ? 1 : 0;
229594d0c90SYong Zhao packet->bitfields2.extended_engine_sel =
230594d0c90SYong Zhao extended_engine_sel__mes_map_queues__legacy_engine_sel;
231594d0c90SYong Zhao packet->bitfields2.queue_type =
232594d0c90SYong Zhao queue_type__mes_map_queues__normal_compute_vi;
233594d0c90SYong Zhao
234594d0c90SYong Zhao switch (q->properties.type) {
235594d0c90SYong Zhao case KFD_QUEUE_TYPE_COMPUTE:
236594d0c90SYong Zhao if (use_static)
237594d0c90SYong Zhao packet->bitfields2.queue_type =
238594d0c90SYong Zhao queue_type__mes_map_queues__normal_latency_static_queue_vi;
239594d0c90SYong Zhao break;
240594d0c90SYong Zhao case KFD_QUEUE_TYPE_DIQ:
241594d0c90SYong Zhao packet->bitfields2.queue_type =
242594d0c90SYong Zhao queue_type__mes_map_queues__debug_interface_queue_vi;
243594d0c90SYong Zhao break;
244594d0c90SYong Zhao case KFD_QUEUE_TYPE_SDMA:
245594d0c90SYong Zhao case KFD_QUEUE_TYPE_SDMA_XGMI:
246594d0c90SYong Zhao use_static = false; /* no static queues under SDMA */
2478dc1db31SMukul Joshi if (q->properties.sdma_engine_id < 2 &&
2488dc1db31SMukul Joshi !pm_use_ext_eng(q->device->kfd))
249594d0c90SYong Zhao packet->bitfields2.engine_sel = q->properties.sdma_engine_id +
250594d0c90SYong Zhao engine_sel__mes_map_queues__sdma0_vi;
251594d0c90SYong Zhao else {
2521794e9d7SMukul Joshi /*
2531794e9d7SMukul Joshi * For GFX9.4.3, SDMA engine id can be greater than 8.
2541794e9d7SMukul Joshi * For such cases, set extended_engine_sel to 2 and
2551794e9d7SMukul Joshi * ensure engine_sel lies between 0-7.
2561794e9d7SMukul Joshi */
2571794e9d7SMukul Joshi if (q->properties.sdma_engine_id >= 8)
2581794e9d7SMukul Joshi packet->bitfields2.extended_engine_sel =
2591794e9d7SMukul Joshi extended_engine_sel__mes_map_queues__sdma8_to_15_sel;
2601794e9d7SMukul Joshi else
261594d0c90SYong Zhao packet->bitfields2.extended_engine_sel =
262594d0c90SYong Zhao extended_engine_sel__mes_map_queues__sdma0_to_7_sel;
2631794e9d7SMukul Joshi
2641794e9d7SMukul Joshi packet->bitfields2.engine_sel = q->properties.sdma_engine_id % 8;
265594d0c90SYong Zhao }
266594d0c90SYong Zhao break;
267594d0c90SYong Zhao default:
268594d0c90SYong Zhao WARN(1, "queue type %d", q->properties.type);
269594d0c90SYong Zhao return -EINVAL;
270594d0c90SYong Zhao }
271594d0c90SYong Zhao packet->bitfields3.doorbell_offset =
272594d0c90SYong Zhao q->properties.doorbell_off;
273594d0c90SYong Zhao
274594d0c90SYong Zhao packet->mqd_addr_lo =
275594d0c90SYong Zhao lower_32_bits(q->gart_mqd_addr);
276594d0c90SYong Zhao
277594d0c90SYong Zhao packet->mqd_addr_hi =
278594d0c90SYong Zhao upper_32_bits(q->gart_mqd_addr);
279594d0c90SYong Zhao
280594d0c90SYong Zhao packet->wptr_addr_lo =
281594d0c90SYong Zhao lower_32_bits((uint64_t)q->properties.write_ptr);
282594d0c90SYong Zhao
283594d0c90SYong Zhao packet->wptr_addr_hi =
284594d0c90SYong Zhao upper_32_bits((uint64_t)q->properties.write_ptr);
285594d0c90SYong Zhao
286594d0c90SYong Zhao return 0;
287594d0c90SYong Zhao }
288594d0c90SYong Zhao
pm_set_grace_period_v9(struct packet_manager * pm,uint32_t * buffer,uint32_t grace_period)2897cee6a68SJonathan Kim static int pm_set_grace_period_v9(struct packet_manager *pm,
2907cee6a68SJonathan Kim uint32_t *buffer,
2917cee6a68SJonathan Kim uint32_t grace_period)
2927cee6a68SJonathan Kim {
2937cee6a68SJonathan Kim struct pm4_mec_write_data_mmio *packet;
2947cee6a68SJonathan Kim uint32_t reg_offset = 0;
2957cee6a68SJonathan Kim uint32_t reg_data = 0;
2967cee6a68SJonathan Kim
2977cee6a68SJonathan Kim pm->dqm->dev->kfd2kgd->build_grace_period_packet_info(
2987cee6a68SJonathan Kim pm->dqm->dev->adev,
2997cee6a68SJonathan Kim pm->dqm->wait_times,
3007cee6a68SJonathan Kim grace_period,
3017cee6a68SJonathan Kim ®_offset,
302*81faf9e0SMukul Joshi ®_data);
3037cee6a68SJonathan Kim
3047cee6a68SJonathan Kim if (grace_period == USE_DEFAULT_GRACE_PERIOD)
3057cee6a68SJonathan Kim reg_data = pm->dqm->wait_times;
3067cee6a68SJonathan Kim
3077cee6a68SJonathan Kim packet = (struct pm4_mec_write_data_mmio *)buffer;
3087cee6a68SJonathan Kim memset(buffer, 0, sizeof(struct pm4_mec_write_data_mmio));
3097cee6a68SJonathan Kim
3107cee6a68SJonathan Kim packet->header.u32All = pm_build_pm4_header(IT_WRITE_DATA,
3117cee6a68SJonathan Kim sizeof(struct pm4_mec_write_data_mmio));
3127cee6a68SJonathan Kim
3137cee6a68SJonathan Kim packet->bitfields2.dst_sel = dst_sel___write_data__mem_mapped_register;
3147cee6a68SJonathan Kim packet->bitfields2.addr_incr =
3157cee6a68SJonathan Kim addr_incr___write_data__do_not_increment_address;
3167cee6a68SJonathan Kim
3177cee6a68SJonathan Kim packet->bitfields3.dst_mmreg_addr = reg_offset;
3187cee6a68SJonathan Kim
3197cee6a68SJonathan Kim packet->data = reg_data;
3207cee6a68SJonathan Kim
3217cee6a68SJonathan Kim return 0;
3227cee6a68SJonathan Kim }
3237cee6a68SJonathan Kim
pm_unmap_queues_v9(struct packet_manager * pm,uint32_t * buffer,enum kfd_unmap_queues_filter filter,uint32_t filter_param,bool reset)324594d0c90SYong Zhao static int pm_unmap_queues_v9(struct packet_manager *pm, uint32_t *buffer,
325594d0c90SYong Zhao enum kfd_unmap_queues_filter filter,
326d2cb0b21SJonathan Kim uint32_t filter_param, bool reset)
327594d0c90SYong Zhao {
328594d0c90SYong Zhao struct pm4_mes_unmap_queues *packet;
329594d0c90SYong Zhao
330594d0c90SYong Zhao packet = (struct pm4_mes_unmap_queues *)buffer;
331594d0c90SYong Zhao memset(buffer, 0, sizeof(struct pm4_mes_unmap_queues));
332594d0c90SYong Zhao
333594d0c90SYong Zhao packet->header.u32All = pm_build_pm4_header(IT_UNMAP_QUEUES,
334594d0c90SYong Zhao sizeof(struct pm4_mes_unmap_queues));
335d2cb0b21SJonathan Kim
3368dc1db31SMukul Joshi packet->bitfields2.extended_engine_sel =
3378dc1db31SMukul Joshi pm_use_ext_eng(pm->dqm->dev->kfd) ?
338b63c54d9SNathan Chancellor extended_engine_sel__mes_unmap_queues__sdma0_to_7_sel :
339594d0c90SYong Zhao extended_engine_sel__mes_unmap_queues__legacy_engine_sel;
340009e9a15SJonathan Kim
341594d0c90SYong Zhao packet->bitfields2.engine_sel =
342594d0c90SYong Zhao engine_sel__mes_unmap_queues__compute;
343594d0c90SYong Zhao
344594d0c90SYong Zhao if (reset)
345594d0c90SYong Zhao packet->bitfields2.action =
346594d0c90SYong Zhao action__mes_unmap_queues__reset_queues;
347594d0c90SYong Zhao else
348594d0c90SYong Zhao packet->bitfields2.action =
349594d0c90SYong Zhao action__mes_unmap_queues__preempt_queues;
350594d0c90SYong Zhao
351594d0c90SYong Zhao switch (filter) {
352594d0c90SYong Zhao case KFD_UNMAP_QUEUES_FILTER_BY_PASID:
353594d0c90SYong Zhao packet->bitfields2.queue_sel =
354594d0c90SYong Zhao queue_sel__mes_unmap_queues__perform_request_on_pasid_queues;
355594d0c90SYong Zhao packet->bitfields3a.pasid = filter_param;
356594d0c90SYong Zhao break;
357594d0c90SYong Zhao case KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES:
358594d0c90SYong Zhao packet->bitfields2.queue_sel =
359594d0c90SYong Zhao queue_sel__mes_unmap_queues__unmap_all_queues;
360594d0c90SYong Zhao break;
361594d0c90SYong Zhao case KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES:
362594d0c90SYong Zhao /* in this case, we do not preempt static queues */
363594d0c90SYong Zhao packet->bitfields2.queue_sel =
364594d0c90SYong Zhao queue_sel__mes_unmap_queues__unmap_all_non_static_queues;
365594d0c90SYong Zhao break;
366594d0c90SYong Zhao default:
367594d0c90SYong Zhao WARN(1, "filter %d", filter);
368594d0c90SYong Zhao return -EINVAL;
369594d0c90SYong Zhao }
370594d0c90SYong Zhao
371594d0c90SYong Zhao return 0;
372594d0c90SYong Zhao
373594d0c90SYong Zhao }
374594d0c90SYong Zhao
pm_query_status_v9(struct packet_manager * pm,uint32_t * buffer,uint64_t fence_address,uint64_t fence_value)375594d0c90SYong Zhao static int pm_query_status_v9(struct packet_manager *pm, uint32_t *buffer,
376b010affeSQu Huang uint64_t fence_address, uint64_t fence_value)
377594d0c90SYong Zhao {
378594d0c90SYong Zhao struct pm4_mes_query_status *packet;
379594d0c90SYong Zhao
380594d0c90SYong Zhao packet = (struct pm4_mes_query_status *)buffer;
381594d0c90SYong Zhao memset(buffer, 0, sizeof(struct pm4_mes_query_status));
382594d0c90SYong Zhao
383594d0c90SYong Zhao
384594d0c90SYong Zhao packet->header.u32All = pm_build_pm4_header(IT_QUERY_STATUS,
385594d0c90SYong Zhao sizeof(struct pm4_mes_query_status));
386594d0c90SYong Zhao
387594d0c90SYong Zhao packet->bitfields2.context_id = 0;
388594d0c90SYong Zhao packet->bitfields2.interrupt_sel =
389594d0c90SYong Zhao interrupt_sel__mes_query_status__completion_status;
390594d0c90SYong Zhao packet->bitfields2.command =
391594d0c90SYong Zhao command__mes_query_status__fence_only_after_write_ack;
392594d0c90SYong Zhao
393594d0c90SYong Zhao packet->addr_hi = upper_32_bits((uint64_t)fence_address);
394594d0c90SYong Zhao packet->addr_lo = lower_32_bits((uint64_t)fence_address);
395594d0c90SYong Zhao packet->data_hi = upper_32_bits((uint64_t)fence_value);
396594d0c90SYong Zhao packet->data_lo = lower_32_bits((uint64_t)fence_value);
397594d0c90SYong Zhao
398594d0c90SYong Zhao return 0;
399594d0c90SYong Zhao }
400594d0c90SYong Zhao
401594d0c90SYong Zhao const struct packet_manager_funcs kfd_v9_pm_funcs = {
402594d0c90SYong Zhao .map_process = pm_map_process_v9,
403594d0c90SYong Zhao .runlist = pm_runlist_v9,
404594d0c90SYong Zhao .set_resources = pm_set_resources_v9,
405594d0c90SYong Zhao .map_queues = pm_map_queues_v9,
406594d0c90SYong Zhao .unmap_queues = pm_unmap_queues_v9,
4077cee6a68SJonathan Kim .set_grace_period = pm_set_grace_period_v9,
408594d0c90SYong Zhao .query_status = pm_query_status_v9,
409594d0c90SYong Zhao .release_mem = NULL,
410594d0c90SYong Zhao .map_process_size = sizeof(struct pm4_mes_map_process),
411594d0c90SYong Zhao .runlist_size = sizeof(struct pm4_mes_runlist),
412594d0c90SYong Zhao .set_resources_size = sizeof(struct pm4_mes_set_resources),
413594d0c90SYong Zhao .map_queues_size = sizeof(struct pm4_mes_map_queues),
414594d0c90SYong Zhao .unmap_queues_size = sizeof(struct pm4_mes_unmap_queues),
4157cee6a68SJonathan Kim .set_grace_period_size = sizeof(struct pm4_mec_write_data_mmio),
416594d0c90SYong Zhao .query_status_size = sizeof(struct pm4_mes_query_status),
417594d0c90SYong Zhao .release_mem_size = 0,
418594d0c90SYong Zhao };
419fd6a440eSJonathan Kim
420fd6a440eSJonathan Kim const struct packet_manager_funcs kfd_aldebaran_pm_funcs = {
421fd6a440eSJonathan Kim .map_process = pm_map_process_aldebaran,
422fd6a440eSJonathan Kim .runlist = pm_runlist_v9,
423fd6a440eSJonathan Kim .set_resources = pm_set_resources_v9,
424fd6a440eSJonathan Kim .map_queues = pm_map_queues_v9,
425fd6a440eSJonathan Kim .unmap_queues = pm_unmap_queues_v9,
4267cee6a68SJonathan Kim .set_grace_period = pm_set_grace_period_v9,
427fd6a440eSJonathan Kim .query_status = pm_query_status_v9,
428fd6a440eSJonathan Kim .release_mem = NULL,
429fd6a440eSJonathan Kim .map_process_size = sizeof(struct pm4_mes_map_process_aldebaran),
430fd6a440eSJonathan Kim .runlist_size = sizeof(struct pm4_mes_runlist),
431fd6a440eSJonathan Kim .set_resources_size = sizeof(struct pm4_mes_set_resources),
432fd6a440eSJonathan Kim .map_queues_size = sizeof(struct pm4_mes_map_queues),
433fd6a440eSJonathan Kim .unmap_queues_size = sizeof(struct pm4_mes_unmap_queues),
4347cee6a68SJonathan Kim .set_grace_period_size = sizeof(struct pm4_mec_write_data_mmio),
435fd6a440eSJonathan Kim .query_status_size = sizeof(struct pm4_mes_query_status),
436fd6a440eSJonathan Kim .release_mem_size = 0,
437fd6a440eSJonathan Kim };
438