13e205a08SOak Zeng /* 23e205a08SOak Zeng * Copyright 2019 Advanced Micro Devices, Inc. 33e205a08SOak Zeng * 43e205a08SOak Zeng * Permission is hereby granted, free of charge, to any person obtaining a 53e205a08SOak Zeng * copy of this software and associated documentation files (the "Software"), 63e205a08SOak Zeng * to deal in the Software without restriction, including without limitation 73e205a08SOak Zeng * the rights to use, copy, modify, merge, publish, distribute, sublicense, 83e205a08SOak Zeng * and/or sell copies of the Software, and to permit persons to whom the 93e205a08SOak Zeng * Software is furnished to do so, subject to the following conditions: 103e205a08SOak Zeng * 113e205a08SOak Zeng * The above copyright notice and this permission notice shall be included in 123e205a08SOak Zeng * all copies or substantial portions of the Software. 133e205a08SOak Zeng * 143e205a08SOak Zeng * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 153e205a08SOak Zeng * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 163e205a08SOak Zeng * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 173e205a08SOak Zeng * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 183e205a08SOak Zeng * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 193e205a08SOak Zeng * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 203e205a08SOak Zeng * OTHER DEALINGS IN THE SOFTWARE. 213e205a08SOak Zeng */ 223e205a08SOak Zeng 233356c38dSGraham Sider void kgd_gfx_v9_program_sh_mem_settings(struct amdgpu_device *adev, uint32_t vmid, 243e205a08SOak Zeng uint32_t sh_mem_config, 253e205a08SOak Zeng uint32_t sh_mem_ape1_base, uint32_t sh_mem_ape1_limit, 26e2069a7bSMukul Joshi uint32_t sh_mem_bases, uint32_t inst); 273356c38dSGraham Sider int kgd_gfx_v9_set_pasid_vmid_mapping(struct amdgpu_device *adev, u32 pasid, 28e2069a7bSMukul Joshi unsigned int vmid, uint32_t inst); 29e2069a7bSMukul Joshi int kgd_gfx_v9_init_interrupts(struct amdgpu_device *adev, uint32_t pipe_id, 30e2069a7bSMukul Joshi uint32_t inst); 31420185fdSGraham Sider int kgd_gfx_v9_hqd_load(struct amdgpu_device *adev, void *mqd, uint32_t pipe_id, 323e205a08SOak Zeng uint32_t queue_id, uint32_t __user *wptr, 333e205a08SOak Zeng uint32_t wptr_shift, uint32_t wptr_mask, 34e2069a7bSMukul Joshi struct mm_struct *mm, uint32_t inst); 35420185fdSGraham Sider int kgd_gfx_v9_hiq_mqd_load(struct amdgpu_device *adev, void *mqd, 3635cd89d5SAaron Liu uint32_t pipe_id, uint32_t queue_id, 37e2069a7bSMukul Joshi uint32_t doorbell_off, uint32_t inst); 38420185fdSGraham Sider int kgd_gfx_v9_hqd_dump(struct amdgpu_device *adev, 393e205a08SOak Zeng uint32_t pipe_id, uint32_t queue_id, 40e2069a7bSMukul Joshi uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst); 41420185fdSGraham Sider bool kgd_gfx_v9_hqd_is_occupied(struct amdgpu_device *adev, 42420185fdSGraham Sider uint64_t queue_address, uint32_t pipe_id, 43e2069a7bSMukul Joshi uint32_t queue_id, uint32_t inst); 44420185fdSGraham Sider int kgd_gfx_v9_hqd_destroy(struct amdgpu_device *adev, void *mqd, 453e205a08SOak Zeng enum kfd_preempt_type reset_type, 463e205a08SOak Zeng unsigned int utimeout, uint32_t pipe_id, 47e2069a7bSMukul Joshi uint32_t queue_id, uint32_t inst); 483356c38dSGraham Sider int kgd_gfx_v9_wave_control_execute(struct amdgpu_device *adev, 493e205a08SOak Zeng uint32_t gfx_index_val, 50e2069a7bSMukul Joshi uint32_t sq_cmd, uint32_t inst); 513356c38dSGraham Sider bool kgd_gfx_v9_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev, 5256fc40abSYong Zhao uint8_t vmid, uint16_t *p_pasid); 533356c38dSGraham Sider void kgd_gfx_v9_set_vm_context_page_table_base(struct amdgpu_device *adev, 549fb1506eSOak Zeng uint32_t vmid, uint64_t page_table_base); 553356c38dSGraham Sider void kgd_gfx_v9_get_cu_occupancy(struct amdgpu_device *adev, int pasid, 56e2069a7bSMukul Joshi int *pasid_wave_cnt, int *max_waves_per_cu, uint32_t inst); 573356c38dSGraham Sider void kgd_gfx_v9_program_trap_handler_settings(struct amdgpu_device *adev, 58e2069a7bSMukul Joshi uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr, 59e2069a7bSMukul Joshi uint32_t inst); 60f544afacSAmber Lin void kgd_gfx_v9_acquire_queue(struct amdgpu_device *adev, uint32_t pipe_id, 61e2069a7bSMukul Joshi uint32_t queue_id, uint32_t inst); 62f544afacSAmber Lin uint64_t kgd_gfx_v9_get_queue_mask(struct amdgpu_device *adev, 63f544afacSAmber Lin uint32_t pipe_id, uint32_t queue_id); 64e2069a7bSMukul Joshi void kgd_gfx_v9_release_queue(struct amdgpu_device *adev, uint32_t inst); 65cde2e087SJonathan Kim void kgd_gfx_v9_set_wave_launch_stall(struct amdgpu_device *adev, 66cde2e087SJonathan Kim uint32_t vmid, 67cde2e087SJonathan Kim bool stall); 68cde2e087SJonathan Kim uint32_t kgd_gfx_v9_enable_debug_trap(struct amdgpu_device *adev, 69cde2e087SJonathan Kim bool restore_dbg_registers, 70cde2e087SJonathan Kim uint32_t vmid); 71cde2e087SJonathan Kim uint32_t kgd_gfx_v9_disable_debug_trap(struct amdgpu_device *adev, 72cde2e087SJonathan Kim bool keep_trap_enabled, 73cde2e087SJonathan Kim uint32_t vmid); 74101827e1SJonathan Kim int kgd_gfx_v9_validate_trap_override_request(struct amdgpu_device *adev, 75101827e1SJonathan Kim uint32_t trap_override, 76101827e1SJonathan Kim uint32_t *trap_mask_supported); 77aea1b473SJonathan Kim uint32_t kgd_gfx_v9_set_wave_launch_mode(struct amdgpu_device *adev, 78aea1b473SJonathan Kim uint8_t wave_launch_mode, 79aea1b473SJonathan Kim uint32_t vmid); 80101827e1SJonathan Kim uint32_t kgd_gfx_v9_set_wave_launch_trap_override(struct amdgpu_device *adev, 81101827e1SJonathan Kim uint32_t vmid, 82101827e1SJonathan Kim uint32_t trap_override, 83101827e1SJonathan Kim uint32_t trap_mask_bits, 84101827e1SJonathan Kim uint32_t trap_mask_request, 85101827e1SJonathan Kim uint32_t *trap_mask_prev, 86101827e1SJonathan Kim uint32_t kfd_dbg_trap_cntl_prev); 87e0f85f46SJonathan Kim uint32_t kgd_gfx_v9_set_address_watch(struct amdgpu_device *adev, 88e0f85f46SJonathan Kim uint64_t watch_address, 89e0f85f46SJonathan Kim uint32_t watch_address_mask, 90e0f85f46SJonathan Kim uint32_t watch_id, 91e0f85f46SJonathan Kim uint32_t watch_mode, 92036e348fSEric Huang uint32_t debug_vmid, 93036e348fSEric Huang uint32_t inst); 94e0f85f46SJonathan Kim uint32_t kgd_gfx_v9_clear_address_watch(struct amdgpu_device *adev, 95e0f85f46SJonathan Kim uint32_t watch_id); 96036e348fSEric Huang void kgd_gfx_v9_get_iq_wait_times(struct amdgpu_device *adev, 97036e348fSEric Huang uint32_t *wait_times, 98036e348fSEric Huang uint32_t inst); 997cee6a68SJonathan Kim void kgd_gfx_v9_build_grace_period_packet_info(struct amdgpu_device *adev, 1007cee6a68SJonathan Kim uint32_t wait_times, 1017cee6a68SJonathan Kim uint32_t grace_period, 1027cee6a68SJonathan Kim uint32_t *reg_offset, 103*81faf9e0SMukul Joshi uint32_t *reg_data); 104