1d87f36a0SRajneesh Bhardwaj // SPDX-License-Identifier: GPL-2.0 OR MIT
214328aa5SPhilip Cox /*
3d87f36a0SRajneesh Bhardwaj * Copyright 2018-2022 Advanced Micro Devices, Inc.
414328aa5SPhilip Cox *
514328aa5SPhilip Cox * Permission is hereby granted, free of charge, to any person obtaining a
614328aa5SPhilip Cox * copy of this software and associated documentation files (the "Software"),
714328aa5SPhilip Cox * to deal in the Software without restriction, including without limitation
814328aa5SPhilip Cox * the rights to use, copy, modify, merge, publish, distribute, sublicense,
914328aa5SPhilip Cox * and/or sell copies of the Software, and to permit persons to whom the
1014328aa5SPhilip Cox * Software is furnished to do so, subject to the following conditions:
1114328aa5SPhilip Cox *
1214328aa5SPhilip Cox * The above copyright notice and this permission notice shall be included in
1314328aa5SPhilip Cox * all copies or substantial portions of the Software.
1414328aa5SPhilip Cox *
1514328aa5SPhilip Cox * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1614328aa5SPhilip Cox * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1714328aa5SPhilip Cox * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
1814328aa5SPhilip Cox * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
1914328aa5SPhilip Cox * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
2014328aa5SPhilip Cox * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
2114328aa5SPhilip Cox * OTHER DEALINGS IN THE SOFTWARE.
2214328aa5SPhilip Cox *
2314328aa5SPhilip Cox */
2414328aa5SPhilip Cox
2514328aa5SPhilip Cox #include "kfd_device_queue_manager.h"
2614328aa5SPhilip Cox #include "navi10_enum.h"
2714328aa5SPhilip Cox #include "gc/gc_10_1_0_offset.h"
2814328aa5SPhilip Cox #include "gc/gc_10_1_0_sh_mask.h"
2914328aa5SPhilip Cox
3014328aa5SPhilip Cox static int update_qpd_v10(struct device_queue_manager *dqm,
3114328aa5SPhilip Cox struct qcm_process_device *qpd);
3214328aa5SPhilip Cox static void init_sdma_vm_v10(struct device_queue_manager *dqm, struct queue *q,
3314328aa5SPhilip Cox struct qcm_process_device *qpd);
3414328aa5SPhilip Cox
device_queue_manager_init_v10(struct device_queue_manager_asic_ops * asic_ops)35*80e28aafSAlex Deucher void device_queue_manager_init_v10(
3614328aa5SPhilip Cox struct device_queue_manager_asic_ops *asic_ops)
3714328aa5SPhilip Cox {
3814328aa5SPhilip Cox asic_ops->update_qpd = update_qpd_v10;
3914328aa5SPhilip Cox asic_ops->init_sdma_vm = init_sdma_vm_v10;
4014328aa5SPhilip Cox asic_ops->mqd_manager_init = mqd_manager_init_v10;
4114328aa5SPhilip Cox }
4214328aa5SPhilip Cox
compute_sh_mem_bases_64bit(struct kfd_process_device * pdd)4314328aa5SPhilip Cox static uint32_t compute_sh_mem_bases_64bit(struct kfd_process_device *pdd)
4414328aa5SPhilip Cox {
4514328aa5SPhilip Cox uint32_t shared_base = pdd->lds_base >> 48;
4614328aa5SPhilip Cox uint32_t private_base = pdd->scratch_base >> 48;
4714328aa5SPhilip Cox
4814328aa5SPhilip Cox return (shared_base << SH_MEM_BASES__SHARED_BASE__SHIFT) |
4914328aa5SPhilip Cox private_base;
5014328aa5SPhilip Cox }
5114328aa5SPhilip Cox
update_qpd_v10(struct device_queue_manager * dqm,struct qcm_process_device * qpd)5214328aa5SPhilip Cox static int update_qpd_v10(struct device_queue_manager *dqm,
5314328aa5SPhilip Cox struct qcm_process_device *qpd)
5414328aa5SPhilip Cox {
5514328aa5SPhilip Cox struct kfd_process_device *pdd;
5614328aa5SPhilip Cox
5714328aa5SPhilip Cox pdd = qpd_to_pdd(qpd);
5814328aa5SPhilip Cox
5914328aa5SPhilip Cox /* check if sh_mem_config register already configured */
6014328aa5SPhilip Cox if (qpd->sh_mem_config == 0) {
6114328aa5SPhilip Cox qpd->sh_mem_config =
62d56b1980SJay Cornwall (SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
63d56b1980SJay Cornwall SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) |
64d56b1980SJay Cornwall (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT);
6514328aa5SPhilip Cox qpd->sh_mem_ape1_limit = 0;
6614328aa5SPhilip Cox qpd->sh_mem_ape1_base = 0;
6714328aa5SPhilip Cox }
6814328aa5SPhilip Cox
6914328aa5SPhilip Cox qpd->sh_mem_bases = compute_sh_mem_bases_64bit(pdd);
7014328aa5SPhilip Cox
7114328aa5SPhilip Cox pr_debug("sh_mem_bases 0x%X\n", qpd->sh_mem_bases);
7214328aa5SPhilip Cox
7314328aa5SPhilip Cox return 0;
7414328aa5SPhilip Cox }
7514328aa5SPhilip Cox
init_sdma_vm_v10(struct device_queue_manager * dqm,struct queue * q,struct qcm_process_device * qpd)7614328aa5SPhilip Cox static void init_sdma_vm_v10(struct device_queue_manager *dqm, struct queue *q,
7714328aa5SPhilip Cox struct qcm_process_device *qpd)
7814328aa5SPhilip Cox {
7914328aa5SPhilip Cox /* Not needed on SDMAv4 onwards any more */
8014328aa5SPhilip Cox q->properties.sdma_vm_addr = 0;
8114328aa5SPhilip Cox }
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