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Searched refs:sdhci_writel (Results 1 – 25 of 30) sorted by relevance

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/openbmc/linux/drivers/mmc/host/
H A Dsdhci-pci-dwc-mshc.c41 sdhci_writel(host, reg, (SDHC_AT_CTRL_R + vendor_ptr)); in sdhci_snps_set_clock()
49 sdhci_writel(host, reg, (SDHC_GPIO_OUT + vendor_ptr)); in sdhci_snps_set_clock()
53 sdhci_writel(host, DIV_REG_100_MHZ, SDHC_MMCM_DIV_REG); in sdhci_snps_set_clock()
54 sdhci_writel(host, CLKFBOUT_100_MHZ, in sdhci_snps_set_clock()
57 sdhci_writel(host, DIV_REG_200_MHZ, SDHC_MMCM_DIV_REG); in sdhci_snps_set_clock()
58 sdhci_writel(host, CLKFBOUT_200_MHZ, in sdhci_snps_set_clock()
65 sdhci_writel(host, reg, (SDHC_GPIO_OUT + vendor_ptr)); in sdhci_snps_set_clock()
H A Dsdhci-milbeaut.c67 sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2); in sdhci_milbeaut_soft_voltage_switch()
69 sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2); in sdhci_milbeaut_soft_voltage_switch()
72 sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2); in sdhci_milbeaut_soft_voltage_switch()
77 sdhci_writel(host, ctrl, F_SDH30_TUNING_SETTING); in sdhci_milbeaut_soft_voltage_switch()
120 sdhci_writel(host, ctl, F_SDH30_ESD_CONTROL); in sdhci_milbeaut_reset()
138 sdhci_writel(host, 0, MLB_SOFT_RESET); in sdhci_milbeaut_bridge_reset()
169 sdhci_writel(host, val, MLB_CR_SET); in sdhci_milbeaut_bridge_init()
183 sdhci_writel(host, ctl, F_SDH30_IO_CONTROL2); in sdhci_milbeaut_vendor_init()
185 sdhci_writel(host, ctl, F_SDH30_IO_CONTROL2); in sdhci_milbeaut_vendor_init()
187 sdhci_writel(host, ctl, F_SDH30_IO_CONTROL2); in sdhci_milbeaut_vendor_init()
[all …]
H A Dsdhci-of-esdhc.c800 sdhci_writel(host, ctrl, ESDHC_PROCTL); in esdhc_pltfm_set_bus_width()
839 sdhci_writel(host, val, ESDHC_PROCTL); in esdhc_reset()
853 sdhci_writel(host, val, ESDHC_TBCTL); in esdhc_reset()
968 sdhci_writel(host, val, ESDHC_TBCTL); in esdhc_tuning_block_enable()
982 sdhci_writel(host, val, ESDHC_TBCTL); in esdhc_tuning_window_ptr()
988 sdhci_writel(host, val, ESDHC_TBCTL); in esdhc_tuning_window_ptr()
1048 sdhci_writel(host, val, ESDHC_TBPTR); in esdhc_execute_sw_tuning()
1054 sdhci_writel(host, val, ESDHC_TBCTL); in esdhc_execute_sw_tuning()
1104 sdhci_writel(host, val, ESDHC_TBCTL); in esdhc_execute_tuning()
1197 sdhci_writel(host, val, ESDHC_TBCTL); in esdhc_set_uhs_signaling()
[all …]
H A Dsdhci_f_sdh30.c47 sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2); in sdhci_f_sdh30_soft_voltage_switch()
49 sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2); in sdhci_f_sdh30_soft_voltage_switch()
52 sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2); in sdhci_f_sdh30_soft_voltage_switch()
59 sdhci_writel(host, ctrl, F_SDH30_ESD_CONTROL); in sdhci_f_sdh30_soft_voltage_switch()
64 sdhci_writel(host, ctrl, F_SDH30_TUNING_SETTING); in sdhci_f_sdh30_soft_voltage_switch()
85 sdhci_writel(host, ctl, F_SDH30_ESD_CONTROL); in sdhci_f_sdh30_reset()
92 sdhci_writel(host, ctl, F_SDH30_TEST); in sdhci_f_sdh30_reset()
180 sdhci_writel(host, reg & ~F_SDH30_EMMC_RST, F_SDH30_ESD_CONTROL); in sdhci_f_sdh30_probe()
182 sdhci_writel(host, reg | F_SDH30_EMMC_RST, F_SDH30_ESD_CONTROL); in sdhci_f_sdh30_probe()
H A Dsdhci-of-dwcmshc.c210 sdhci_writel(host, vendor, reg); in dwcmshc_hs400_enhanced_strobe()
244 sdhci_writel(host, extra, reg); in dwcmshc_rk3568_set_clock()
253 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK); in dwcmshc_rk3568_set_clock()
254 sdhci_writel(host, 0, DECMSHC_EMMC_DLL_CMDOUT); in dwcmshc_rk3568_set_clock()
268 sdhci_writel(host, BIT(1), DWCMSHC_EMMC_DLL_CTRL); in dwcmshc_rk3568_set_clock()
270 sdhci_writel(host, 0x0, DWCMSHC_EMMC_DLL_CTRL); in dwcmshc_rk3568_set_clock()
279 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK); in dwcmshc_rk3568_set_clock()
285 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL); in dwcmshc_rk3568_set_clock()
318 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK); in dwcmshc_rk3568_set_clock()
417 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK); in dwcmshc_rk35xx_init()
[all …]
H A Dsdhci-xenon-phy.c258 sdhci_writel(host, reg, phy_regs->timing_adj); in xenon_emmc_phy_init()
383 sdhci_writel(host, reg, phy_regs->dll_ctrl); in xenon_emmc_phy_enable_dll()
438 sdhci_writel(host, reg, XENON_SLOT_OP_STATUS_CTRL); in xenon_emmc_phy_config_tuning()
452 sdhci_writel(host, reg, XENON_SLOT_EMMC_CTRL); in xenon_emmc_phy_disable_strobe()
495 sdhci_writel(host, reg, XENON_SLOT_EMMC_CTRL); in xenon_emmc_phy_strobe_delay_adj()
566 sdhci_writel(host, reg, phy_regs->timing_adj); in xenon_emmc_phy_slow_mode()
591 sdhci_writel(host, reg, phy_regs->pad_ctrl); in xenon_emmc_phy_set()
620 sdhci_writel(host, reg, phy_regs->timing_adj); in xenon_emmc_phy_set()
633 sdhci_writel(host, reg, phy_regs->pad_ctrl2); in xenon_emmc_phy_set()
660 sdhci_writel(host, reg, phy_regs->func_ctrl); in xenon_emmc_phy_set()
[all …]
H A Dsdhci-bcm-kona.c58 sdhci_writel(host, val, KONA_SDHOST_CORECTRL); in sdhci_bcm_kona_sd_reset()
78 sdhci_writel(host, val, KONA_SDHOST_CORECTRL); in sdhci_bcm_kona_sd_reset()
90 sdhci_writel(host, val, KONA_SDHOST_COREIMR); in sdhci_bcm_kona_sd_init()
103 sdhci_writel(host, val, KONA_SDHOST_CORECTRL); in sdhci_bcm_kona_sd_init()
138 sdhci_writel(host, val, KONA_SDHOST_CORESTAT); in sdhci_bcm_kona_sd_card_emulate()
141 sdhci_writel(host, val, KONA_SDHOST_CORESTAT); in sdhci_bcm_kona_sd_card_emulate()
H A Dsdhci-xenon.c32 sdhci_writel(host, reg, SDHCI_CLOCK_CONTROL); in xenon_enable_internal_clk()
66 sdhci_writel(host, reg, XENON_SYS_OP_CTRL); in xenon_set_sdclk_off_idle()
79 sdhci_writel(host, reg, XENON_SYS_OP_CTRL); in xenon_set_acg()
90 sdhci_writel(host, reg, XENON_SYS_OP_CTRL); in xenon_enable_sdhc()
108 sdhci_writel(host, reg, XENON_SYS_OP_CTRL); in xenon_disable_sdhc()
119 sdhci_writel(host, reg, XENON_SYS_EXT_OP_CTRL); in xenon_enable_sdhc_parallel_tran()
129 sdhci_writel(host, reg, XENON_SYS_EXT_OP_CTRL); in xenon_mask_cmd_conflict_err()
146 sdhci_writel(host, reg, SDHCI_SIGNAL_ENABLE); in xenon_retune_setup()
149 sdhci_writel(host, reg, SDHCI_INT_ENABLE); in xenon_retune_setup()
391 sdhci_writel(host, reg, XENON_SYS_CFG_INFO); in xenon_enable_sdio_irq()
[all …]
H A Dsdhci-sprd.c126 sdhci_writel(host, val, SDHCI_SPRD_REG_DEBOUNCE); in sdhci_sprd_init_config()
248 sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI); in _sdhci_sprd_set_clock()
253 sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI); in _sdhci_sprd_set_clock()
264 sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); in sdhci_sprd_enable_phy_dll()
271 sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); in sdhci_sprd_enable_phy_dll()
277 sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); in sdhci_sprd_enable_phy_dll()
378 sdhci_writel(host, p[timing], SDHCI_SPRD_REG_32_DLL_DLY); in sdhci_sprd_set_uhs_signaling()
568 sdhci_writel(host, p[MMC_TIMING_MMC_HS400 + 1], in sdhci_sprd_hs400_enhanced_strobe()
648 sdhci_writel(host, dll_cfg, SDHCI_SPRD_REG_32_DLL_CFG); in sdhci_sprd_tuning()
661 sdhci_writel(host, dll_dly, SDHCI_SPRD_REG_32_DLL_DLY); in sdhci_sprd_tuning()
[all …]
H A Dsdhci-pci-gli.c244 sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT); in gl9750_wt_on()
261 sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT); in gl9750_wt_off()
327 sdhci_writel(host, pll_value, SDHCI_GLI_9750_PLL); in gli_set_9750()
328 sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC); in gli_set_9750()
373 sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC); in gli_set_9750_rx_inv()
438 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL); in gl9750_disable_ssc_pll()
454 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL); in gl9750_set_pll()
488 sdhci_writel(host, ssc, SDHCI_GLI_9750_PLLSSC); in gl9750_set_ssc()
489 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL); in gl9750_set_ssc()
561 sdhci_writel(host, value, SDHCI_GLI_9750_CFG2); in gl9750_hw_setting()
[all …]
H A Dsdhci-of-arasan.c460 sdhci_writel(host, vendor, SDHCI_ARASAN_VENDOR_REGISTER); in sdhci_arasan_hs400_enhanced_strobe()
904 sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER); in sdhci_versal_sdcardclk_set_phase()
907 sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER); in sdhci_versal_sdcardclk_set_phase()
971 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER); in sdhci_versal_sampleclk_set_phase()
1020 sdhci_writel(host, regval, PHY_CTRL_REG1); in sdhci_versal_net_emmc_sdcardclk_set_phase()
1023 sdhci_writel(host, regval, PHY_CTRL_REG1); in sdhci_versal_net_emmc_sdcardclk_set_phase()
1054 sdhci_writel(host, regval, PHY_CTRL_REG1); in sdhci_versal_net_emmc_sampleclk_set_phase()
1066 sdhci_writel(host, regval, PHY_CTRL_REG1); in sdhci_versal_net_emmc_sampleclk_set_phase()
1068 sdhci_writel(host, regval, PHY_CTRL_REG1); in sdhci_versal_net_emmc_sampleclk_set_phase()
1071 sdhci_writel(host, regval, PHY_CTRL_REG1); in sdhci_versal_net_emmc_sampleclk_set_phase()
[all …]
H A Dsdhci.c172 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); in sdhci_set_card_detection()
601 sdhci_writel(host, scratch, SDHCI_BUFFER); in sdhci_write_block_pio()
900 sdhci_writel(host, addr, SDHCI_DMA_ADDRESS); in sdhci_set_sdma_addr()
1672 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT); in sdhci_send_command()
2342 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); in sdhci_set_ios()
3773 sdhci_writel(host, 0, SDHCI_INT_ENABLE); in sdhci_suspend_host()
4002 sdhci_writel(host, mask, SDHCI_INT_STATUS); in sdhci_cqe_irq()
4856 sdhci_writel(host, 0, SDHCI_INT_ENABLE); in __sdhci_add_host()
4857 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); in __sdhci_add_host()
4915 sdhci_writel(host, 0, SDHCI_INT_ENABLE); in sdhci_remove_host()
[all …]
H A Dsdhci-tegra.c355 sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); in tegra_sdhci_set_tap()
437 sdhci_writel(host, val, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); in tegra_sdhci_configure_cal_pad()
451 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); in tegra_sdhci_set_pad_autocal_offset()
497 sdhci_writel(host, reg, in tegra_sdhci_set_padctrl()
559 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); in tegra_sdhci_pad_autocalib()
577 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); in tegra_sdhci_pad_autocalib()
842 sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_DLLCAL_CFG); in tegra_sdhci_hs400_dll_cal()
880 sdhci_writel(host, val, SDHCI_VNDR_TUN_CTRL0_0); in tegra_sdhci_tap_correction()
1048 sdhci_writel(host, val, SDHCI_VNDR_TUN_CTRL0_0); in tegra_sdhci_set_uhs_signaling()
1049 sdhci_writel(host, 0, SDHCI_TEGRA_VNDR_TUN_CTRL1_0); in tegra_sdhci_set_uhs_signaling()
[all …]
H A Dsdhci-pci-o2micro.c118 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_enable_internal_clock()
121 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_enable_internal_clock()
125 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_enable_internal_clock()
152 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_enable_internal_clock()
265 sdhci_writel(host, scratch_32, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_dll_recovery()
791 sdhci_writel(host, reg, O2_SD_VENDOR_SETTING2); in sdhci_pci_o2_probe_slot()
H A Dsdhci-omap.c494 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); in sdhci_omap_execute_tuning()
495 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); in sdhci_omap_execute_tuning()
521 sdhci_writel(host, ier, SDHCI_INT_ENABLE); in sdhci_omap_card_busy()
522 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE); in sdhci_omap_card_busy()
537 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); in sdhci_omap_card_busy()
538 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); in sdhci_omap_card_busy()
912 sdhci_writel(host, intmask & CMD_MASK, SDHCI_INT_STATUS); in sdhci_omap_irq()
H A Dsdhci-pxav2.c108 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK, SDHCI_INT_STATUS); in pxav1_irq()
145 sdhci_writel(host, 0, SDHCI_ARGUMENT); in pxav1_request_done()
H A Dsdhci-acpi.c404 sdhci_writel(host, 0x3, VENDOR_SPECIFIC_PWRCTL_CLEAR_REG); in sdhci_acpi_qcom_handler()
405 sdhci_writel(host, 0x1, VENDOR_SPECIFIC_PWRCTL_CTL_REG); in sdhci_acpi_qcom_handler()
519 sdhci_writel(host, 0x40003210, SDHCI_AMD_RESET_DLL_REGISTER); in sdhci_acpi_amd_hs400_dll()
522 sdhci_writel(host, 0x40033210, SDHCI_AMD_RESET_DLL_REGISTER); in sdhci_acpi_amd_hs400_dll()
H A Dsdhci-esdhc-mcf.c201 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); in esdhc_mcf_reset()
202 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); in esdhc_mcf_reset()
H A Dsdhci.h676 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) in sdhci_writel() function
726 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) in sdhci_writel() function
/openbmc/u-boot/drivers/mmc/
H A Dkona_sdhci.c34 sdhci_writel(host, mask, SDHCI_CORECTRL_OFFSET); in init_kona_mmc_core()
51 sdhci_writel(host, mask, SDHCI_CORECTRL_OFFSET); in init_kona_mmc_core()
55 sdhci_writel(host, mask | SDHCI_CORECTRL_EN, SDHCI_CORECTRL_OFFSET); in init_kona_mmc_core()
58 sdhci_writel(host, SDHCI_COREIMR_IP, SDHCI_COREIMR_OFFSET); in init_kona_mmc_core()
62 sdhci_writel(host, mask | SDHCI_CORESTAT_CD_SW, SDHCI_CORESTAT_OFFSET); in init_kona_mmc_core()
H A Dxenon_sdhci.c147 sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST); in xenon_mmc_phy_init()
168 sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST); in xenon_mmc_phy_init()
218 sdhci_writel(host, var, EMMC_PHY_PAD_CONTROL); in xenon_mmc_phy_set()
224 sdhci_writel(host, var, EMMC_PHY_PAD_CONTROL1); in xenon_mmc_phy_set()
239 sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST); in xenon_mmc_phy_set()
257 sdhci_writel(host, var, EMMC_PHY_FUNC_CONTROL); in xenon_mmc_phy_set()
278 sdhci_writel(host, var, SDHC_SYS_OP_CTRL); in xenon_mmc_set_acg()
290 sdhci_writel(host, var, SDHC_SYS_OP_CTRL); in xenon_mmc_enable_slot()
300 sdhci_writel(host, var, SDHC_SYS_EXT_OP_CTRL); in xenon_mmc_enable_parallel_tran()
315 sdhci_writel(host, var, SDHCI_SIGNAL_ENABLE); in xenon_mmc_disable_tuning()
[all …]
H A Dsdhci.c66 sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER); in sdhci_transfer_pio()
95 sdhci_writel(host, rdy, SDHCI_INT_STATUS); in sdhci_transfer_data()
109 sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS); in sdhci_transfer_data()
112 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS); in sdhci_transfer_data()
184 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
245 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
257 sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
284 sdhci_writel(host, mask, SDHCI_INT_STATUS);
295 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
557 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
[all …]
H A Ds5p_sdhci.c39 sdhci_writel(host, SDHCI_CTRL4_DRIVE_MASK(0x3), SDHCI_CONTROL4); in s5p_sdhci_set_control_reg()
49 sdhci_writel(host, val, SDHCI_CONTROL2); in s5p_sdhci_set_control_reg()
61 sdhci_writel(host, val, SDHCI_CONTROL3); in s5p_sdhci_set_control_reg()
72 sdhci_writel(host, ctrl, SDHCI_CONTROL2); in s5p_sdhci_set_control_reg()
H A Dzynq_sdhci.c110 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE); in arasan_sdhci_execute_tuning()
111 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE); in arasan_sdhci_execute_tuning()
145 sdhci_writel(host, ctrl, SDHCI_HOST_CTRL2); in arasan_sdhci_execute_tuning()
157 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK, in arasan_sdhci_execute_tuning()
160 sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE); in arasan_sdhci_execute_tuning()
/openbmc/u-boot/include/
H A Dsdhci.h284 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) in sdhci_writel() function
334 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) in sdhci_writel() function

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