1152f8204SPrabu Thangamuthu // SPDX-License-Identifier: GPL-2.0
2152f8204SPrabu Thangamuthu /*
3152f8204SPrabu Thangamuthu * SDHCI driver for Synopsys DWC_MSHC controller
4152f8204SPrabu Thangamuthu *
5152f8204SPrabu Thangamuthu * Copyright (C) 2018 Synopsys, Inc. (www.synopsys.com)
6152f8204SPrabu Thangamuthu *
7152f8204SPrabu Thangamuthu * Authors:
8152f8204SPrabu Thangamuthu * Prabu Thangamuthu <prabu.t@synopsys.com>
9152f8204SPrabu Thangamuthu * Manjunath M B <manjumb@synopsys.com>
10152f8204SPrabu Thangamuthu */
11152f8204SPrabu Thangamuthu
12152f8204SPrabu Thangamuthu #include "sdhci.h"
13152f8204SPrabu Thangamuthu #include "sdhci-pci.h"
14152f8204SPrabu Thangamuthu
15152f8204SPrabu Thangamuthu #define SDHCI_VENDOR_PTR_R 0xE8
16152f8204SPrabu Thangamuthu
17152f8204SPrabu Thangamuthu /* Synopsys vendor specific registers */
18152f8204SPrabu Thangamuthu #define SDHC_GPIO_OUT 0x34
19152f8204SPrabu Thangamuthu #define SDHC_AT_CTRL_R 0x40
20152f8204SPrabu Thangamuthu #define SDHC_SW_TUNE_EN 0x00000010
21152f8204SPrabu Thangamuthu
22152f8204SPrabu Thangamuthu /* MMCM DRP */
23152f8204SPrabu Thangamuthu #define SDHC_MMCM_DIV_REG 0x1020
24152f8204SPrabu Thangamuthu #define DIV_REG_100_MHZ 0x1145
25152f8204SPrabu Thangamuthu #define DIV_REG_200_MHZ 0x1083
26152f8204SPrabu Thangamuthu #define SDHC_MMCM_CLKFBOUT 0x1024
27152f8204SPrabu Thangamuthu #define CLKFBOUT_100_MHZ 0x0000
28152f8204SPrabu Thangamuthu #define CLKFBOUT_200_MHZ 0x0080
29152f8204SPrabu Thangamuthu #define SDHC_CCLK_MMCM_RST 0x00000001
30152f8204SPrabu Thangamuthu
sdhci_snps_set_clock(struct sdhci_host * host,unsigned int clock)31152f8204SPrabu Thangamuthu static void sdhci_snps_set_clock(struct sdhci_host *host, unsigned int clock)
32152f8204SPrabu Thangamuthu {
33152f8204SPrabu Thangamuthu u16 clk;
34152f8204SPrabu Thangamuthu u32 reg, vendor_ptr;
35152f8204SPrabu Thangamuthu
36152f8204SPrabu Thangamuthu vendor_ptr = sdhci_readw(host, SDHCI_VENDOR_PTR_R);
37152f8204SPrabu Thangamuthu
38152f8204SPrabu Thangamuthu /* Disable software managed rx tuning */
39152f8204SPrabu Thangamuthu reg = sdhci_readl(host, (SDHC_AT_CTRL_R + vendor_ptr));
40152f8204SPrabu Thangamuthu reg &= ~SDHC_SW_TUNE_EN;
41152f8204SPrabu Thangamuthu sdhci_writel(host, reg, (SDHC_AT_CTRL_R + vendor_ptr));
42152f8204SPrabu Thangamuthu
43152f8204SPrabu Thangamuthu if (clock <= 52000000) {
44152f8204SPrabu Thangamuthu sdhci_set_clock(host, clock);
45152f8204SPrabu Thangamuthu } else {
46152f8204SPrabu Thangamuthu /* Assert reset to MMCM */
47152f8204SPrabu Thangamuthu reg = sdhci_readl(host, (SDHC_GPIO_OUT + vendor_ptr));
48152f8204SPrabu Thangamuthu reg |= SDHC_CCLK_MMCM_RST;
49152f8204SPrabu Thangamuthu sdhci_writel(host, reg, (SDHC_GPIO_OUT + vendor_ptr));
50152f8204SPrabu Thangamuthu
51152f8204SPrabu Thangamuthu /* Configure MMCM */
52152f8204SPrabu Thangamuthu if (clock == 100000000) {
53152f8204SPrabu Thangamuthu sdhci_writel(host, DIV_REG_100_MHZ, SDHC_MMCM_DIV_REG);
54152f8204SPrabu Thangamuthu sdhci_writel(host, CLKFBOUT_100_MHZ,
55152f8204SPrabu Thangamuthu SDHC_MMCM_CLKFBOUT);
56152f8204SPrabu Thangamuthu } else {
57152f8204SPrabu Thangamuthu sdhci_writel(host, DIV_REG_200_MHZ, SDHC_MMCM_DIV_REG);
58152f8204SPrabu Thangamuthu sdhci_writel(host, CLKFBOUT_200_MHZ,
59152f8204SPrabu Thangamuthu SDHC_MMCM_CLKFBOUT);
60152f8204SPrabu Thangamuthu }
61152f8204SPrabu Thangamuthu
62152f8204SPrabu Thangamuthu /* De-assert reset to MMCM */
63152f8204SPrabu Thangamuthu reg = sdhci_readl(host, (SDHC_GPIO_OUT + vendor_ptr));
64152f8204SPrabu Thangamuthu reg &= ~SDHC_CCLK_MMCM_RST;
65152f8204SPrabu Thangamuthu sdhci_writel(host, reg, (SDHC_GPIO_OUT + vendor_ptr));
66152f8204SPrabu Thangamuthu
67152f8204SPrabu Thangamuthu /* Enable clock */
68152f8204SPrabu Thangamuthu clk = SDHCI_PROG_CLOCK_MODE | SDHCI_CLOCK_INT_EN |
69152f8204SPrabu Thangamuthu SDHCI_CLOCK_CARD_EN;
70152f8204SPrabu Thangamuthu sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
71152f8204SPrabu Thangamuthu }
72152f8204SPrabu Thangamuthu }
73152f8204SPrabu Thangamuthu
74152f8204SPrabu Thangamuthu static const struct sdhci_ops sdhci_snps_ops = {
75152f8204SPrabu Thangamuthu .set_clock = sdhci_snps_set_clock,
76152f8204SPrabu Thangamuthu .enable_dma = sdhci_pci_enable_dma,
77152f8204SPrabu Thangamuthu .set_bus_width = sdhci_set_bus_width,
78152f8204SPrabu Thangamuthu .reset = sdhci_reset,
79152f8204SPrabu Thangamuthu .set_uhs_signaling = sdhci_set_uhs_signaling,
80152f8204SPrabu Thangamuthu };
81152f8204SPrabu Thangamuthu
82152f8204SPrabu Thangamuthu const struct sdhci_pci_fixes sdhci_snps = {
83152f8204SPrabu Thangamuthu .ops = &sdhci_snps_ops,
84152f8204SPrabu Thangamuthu };
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