1e51df6ceSBen Chuang // SPDX-License-Identifier: GPL-2.0+
2e51df6ceSBen Chuang /*
3e51df6ceSBen Chuang * Copyright (C) 2019 Genesys Logic, Inc.
4e51df6ceSBen Chuang *
5e51df6ceSBen Chuang * Authors: Ben Chuang <ben.chuang@genesyslogic.com.tw>
6e51df6ceSBen Chuang *
7e51df6ceSBen Chuang * Version: v0.9.0 (2019-08-08)
8e51df6ceSBen Chuang */
9e51df6ceSBen Chuang
10e51df6ceSBen Chuang #include <linux/bitfield.h>
11e51df6ceSBen Chuang #include <linux/bits.h>
12e51df6ceSBen Chuang #include <linux/pci.h>
13e51df6ceSBen Chuang #include <linux/mmc/mmc.h>
14e51df6ceSBen Chuang #include <linux/delay.h>
15189f1d9bSHector Martin #include <linux/of.h>
16d607667bSBen Chuang #include <linux/iopoll.h>
17e51df6ceSBen Chuang #include "sdhci.h"
1808b863bbSBrian Norris #include "sdhci-cqhci.h"
19e51df6ceSBen Chuang #include "sdhci-pci.h"
20347f6be1SBen Chuang #include "cqhci.h"
21e51df6ceSBen Chuang
22e51df6ceSBen Chuang /* Genesys Logic extra registers */
23e51df6ceSBen Chuang #define SDHCI_GLI_9750_WT 0x800
24e51df6ceSBen Chuang #define SDHCI_GLI_9750_WT_EN BIT(0)
25e51df6ceSBen Chuang #define GLI_9750_WT_EN_ON 0x1
26e51df6ceSBen Chuang #define GLI_9750_WT_EN_OFF 0x0
27e51df6ceSBen Chuang
28cd93b795SVictor Shih #define PCI_GLI_9750_PM_CTRL 0xFC
29cd93b795SVictor Shih #define PCI_GLI_9750_PM_STATE GENMASK(1, 0)
30cd93b795SVictor Shih
31ea672572SVictor Shih #define PCI_GLI_9750_CORRERR_MASK 0x214
32ea672572SVictor Shih #define PCI_GLI_9750_CORRERR_MASK_REPLAY_TIMER_TIMEOUT BIT(12)
33ea672572SVictor Shih
349751baccSBen Chuang #define SDHCI_GLI_9750_CFG2 0x848
359751baccSBen Chuang #define SDHCI_GLI_9750_CFG2_L1DLY GENMASK(28, 24)
369751baccSBen Chuang #define GLI_9750_CFG2_L1DLY_VALUE 0x1F
379751baccSBen Chuang
38e51df6ceSBen Chuang #define SDHCI_GLI_9750_DRIVING 0x860
39e51df6ceSBen Chuang #define SDHCI_GLI_9750_DRIVING_1 GENMASK(11, 0)
40e51df6ceSBen Chuang #define SDHCI_GLI_9750_DRIVING_2 GENMASK(27, 26)
41e51df6ceSBen Chuang #define GLI_9750_DRIVING_1_VALUE 0xFFF
42e51df6ceSBen Chuang #define GLI_9750_DRIVING_2_VALUE 0x3
43b56ff195SBen Chuang #define SDHCI_GLI_9750_SEL_1 BIT(29)
44b56ff195SBen Chuang #define SDHCI_GLI_9750_SEL_2 BIT(31)
45b56ff195SBen Chuang #define SDHCI_GLI_9750_ALL_RST (BIT(24)|BIT(25)|BIT(28)|BIT(30))
46e51df6ceSBen Chuang
47e51df6ceSBen Chuang #define SDHCI_GLI_9750_PLL 0x864
48786d33c8SBen Chuang #define SDHCI_GLI_9750_PLL_LDIV GENMASK(9, 0)
49786d33c8SBen Chuang #define SDHCI_GLI_9750_PLL_PDIV GENMASK(14, 12)
50786d33c8SBen Chuang #define SDHCI_GLI_9750_PLL_DIR BIT(15)
51e51df6ceSBen Chuang #define SDHCI_GLI_9750_PLL_TX2_INV BIT(23)
52e51df6ceSBen Chuang #define SDHCI_GLI_9750_PLL_TX2_DLY GENMASK(22, 20)
53e51df6ceSBen Chuang #define GLI_9750_PLL_TX2_INV_VALUE 0x1
54e51df6ceSBen Chuang #define GLI_9750_PLL_TX2_DLY_VALUE 0x0
55786d33c8SBen Chuang #define SDHCI_GLI_9750_PLLSSC_STEP GENMASK(28, 24)
56786d33c8SBen Chuang #define SDHCI_GLI_9750_PLLSSC_EN BIT(31)
57786d33c8SBen Chuang
58786d33c8SBen Chuang #define SDHCI_GLI_9750_PLLSSC 0x86C
59786d33c8SBen Chuang #define SDHCI_GLI_9750_PLLSSC_PPM GENMASK(31, 16)
60e51df6ceSBen Chuang
61e51df6ceSBen Chuang #define SDHCI_GLI_9750_SW_CTRL 0x874
62e51df6ceSBen Chuang #define SDHCI_GLI_9750_SW_CTRL_4 GENMASK(7, 6)
63e51df6ceSBen Chuang #define GLI_9750_SW_CTRL_4_VALUE 0x3
64e51df6ceSBen Chuang
65e51df6ceSBen Chuang #define SDHCI_GLI_9750_MISC 0x878
66e51df6ceSBen Chuang #define SDHCI_GLI_9750_MISC_TX1_INV BIT(2)
67e51df6ceSBen Chuang #define SDHCI_GLI_9750_MISC_RX_INV BIT(3)
68e51df6ceSBen Chuang #define SDHCI_GLI_9750_MISC_TX1_DLY GENMASK(6, 4)
69e51df6ceSBen Chuang #define GLI_9750_MISC_TX1_INV_VALUE 0x0
70e51df6ceSBen Chuang #define GLI_9750_MISC_RX_INV_ON 0x1
71e51df6ceSBen Chuang #define GLI_9750_MISC_RX_INV_OFF 0x0
72e51df6ceSBen Chuang #define GLI_9750_MISC_RX_INV_VALUE GLI_9750_MISC_RX_INV_OFF
73e51df6ceSBen Chuang #define GLI_9750_MISC_TX1_DLY_VALUE 0x5
7408df1a50SBen Chuang #define SDHCI_GLI_9750_MISC_SSC_OFF BIT(26)
75e51df6ceSBen Chuang
76e51df6ceSBen Chuang #define SDHCI_GLI_9750_TUNING_CONTROL 0x540
77e51df6ceSBen Chuang #define SDHCI_GLI_9750_TUNING_CONTROL_EN BIT(4)
78e51df6ceSBen Chuang #define GLI_9750_TUNING_CONTROL_EN_ON 0x1
79e51df6ceSBen Chuang #define GLI_9750_TUNING_CONTROL_EN_OFF 0x0
80e51df6ceSBen Chuang #define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1 BIT(16)
81e51df6ceSBen Chuang #define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2 GENMASK(20, 19)
82e51df6ceSBen Chuang #define GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE 0x1
83e51df6ceSBen Chuang #define GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE 0x2
84e51df6ceSBen Chuang
85e51df6ceSBen Chuang #define SDHCI_GLI_9750_TUNING_PARAMETERS 0x544
86e51df6ceSBen Chuang #define SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY GENMASK(2, 0)
87e51df6ceSBen Chuang #define GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE 0x1
88e51df6ceSBen Chuang
891ae1d2d6SBen Chuang #define SDHCI_GLI_9763E_CTRL_HS400 0x7
901ae1d2d6SBen Chuang
911ae1d2d6SBen Chuang #define SDHCI_GLI_9763E_HS400_ES_REG 0x52C
921ae1d2d6SBen Chuang #define SDHCI_GLI_9763E_HS400_ES_BIT BIT(8)
931ae1d2d6SBen Chuang
941ae1d2d6SBen Chuang #define PCIE_GLI_9763E_VHS 0x884
951ae1d2d6SBen Chuang #define GLI_9763E_VHS_REV GENMASK(19, 16)
961ae1d2d6SBen Chuang #define GLI_9763E_VHS_REV_R 0x0
971ae1d2d6SBen Chuang #define GLI_9763E_VHS_REV_M 0x1
981ae1d2d6SBen Chuang #define GLI_9763E_VHS_REV_W 0x2
99347f6be1SBen Chuang #define PCIE_GLI_9763E_MB 0x888
100347f6be1SBen Chuang #define GLI_9763E_MB_CMDQ_OFF BIT(19)
10115f908faSRenius Chen #define GLI_9763E_MB_ERP_ON BIT(7)
1021ae1d2d6SBen Chuang #define PCIE_GLI_9763E_SCR 0x8E0
1031ae1d2d6SBen Chuang #define GLI_9763E_SCR_AXI_REQ BIT(9)
1041ae1d2d6SBen Chuang
105f9e5b339SJason Lai #define PCIE_GLI_9763E_CFG 0x8A0
106f9e5b339SJason Lai #define GLI_9763E_CFG_LPSN_DIS BIT(12)
107f9e5b339SJason Lai
108edee82f7SRenius Chen #define PCIE_GLI_9763E_CFG2 0x8A4
109edee82f7SRenius Chen #define GLI_9763E_CFG2_L1DLY GENMASK(28, 19)
11034dd3cccSBen Chuang #define GLI_9763E_CFG2_L1DLY_MID 0x54
111edee82f7SRenius Chen
11298991b18SBen Chuang #define PCIE_GLI_9763E_MMC_CTRL 0x960
11398991b18SBen Chuang #define GLI_9763E_HS400_SLOW BIT(3)
11498991b18SBen Chuang
115c58c5950SRenius Chen #define PCIE_GLI_9763E_CLKRXDLY 0x934
116c58c5950SRenius Chen #define GLI_9763E_HS400_RXDLY GENMASK(31, 28)
117c58c5950SRenius Chen #define GLI_9763E_HS400_RXDLY_5 0x5
118c58c5950SRenius Chen
119347f6be1SBen Chuang #define SDHCI_GLI_9763E_CQE_BASE_ADDR 0x200
120347f6be1SBen Chuang #define GLI_9763E_CQE_TRNS_MODE (SDHCI_TRNS_MULTI | \
121347f6be1SBen Chuang SDHCI_TRNS_BLK_CNT_EN | \
122347f6be1SBen Chuang SDHCI_TRNS_DMA)
123347f6be1SBen Chuang
124786d33c8SBen Chuang #define PCI_GLI_9755_WT 0x800
125786d33c8SBen Chuang #define PCI_GLI_9755_WT_EN BIT(0)
126786d33c8SBen Chuang #define GLI_9755_WT_EN_ON 0x1
127786d33c8SBen Chuang #define GLI_9755_WT_EN_OFF 0x0
128786d33c8SBen Chuang
1290f1d9961SBen Chuang #define PCI_GLI_9755_PECONF 0x44
1300f1d9961SBen Chuang #define PCI_GLI_9755_LFCLK GENMASK(14, 12)
1310f1d9961SBen Chuang #define PCI_GLI_9755_DMACLK BIT(29)
132189f1d9bSHector Martin #define PCI_GLI_9755_INVERT_CD BIT(30)
133189f1d9bSHector Martin #define PCI_GLI_9755_INVERT_WP BIT(31)
1340f1d9961SBen Chuang
1359751baccSBen Chuang #define PCI_GLI_9755_CFG2 0x48
1369751baccSBen Chuang #define PCI_GLI_9755_CFG2_L1DLY GENMASK(28, 24)
1379751baccSBen Chuang #define GLI_9755_CFG2_L1DLY_VALUE 0x1F
1389751baccSBen Chuang
139786d33c8SBen Chuang #define PCI_GLI_9755_PLL 0x64
140786d33c8SBen Chuang #define PCI_GLI_9755_PLL_LDIV GENMASK(9, 0)
141786d33c8SBen Chuang #define PCI_GLI_9755_PLL_PDIV GENMASK(14, 12)
142786d33c8SBen Chuang #define PCI_GLI_9755_PLL_DIR BIT(15)
143786d33c8SBen Chuang #define PCI_GLI_9755_PLLSSC_STEP GENMASK(28, 24)
144786d33c8SBen Chuang #define PCI_GLI_9755_PLLSSC_EN BIT(31)
145786d33c8SBen Chuang
146786d33c8SBen Chuang #define PCI_GLI_9755_PLLSSC 0x68
147786d33c8SBen Chuang #define PCI_GLI_9755_PLLSSC_PPM GENMASK(15, 0)
148786d33c8SBen Chuang
149f46b54ccSRenius Chen #define PCI_GLI_9755_SerDes 0x70
150f46b54ccSRenius Chen #define PCI_GLI_9755_SCP_DIS BIT(19)
151f46b54ccSRenius Chen
15208df1a50SBen Chuang #define PCI_GLI_9755_MISC 0x78
15308df1a50SBen Chuang #define PCI_GLI_9755_MISC_SSC_OFF BIT(26)
15408df1a50SBen Chuang
15536ed2fd3SBen Chuang #define PCI_GLI_9755_PM_CTRL 0xFC
15636ed2fd3SBen Chuang #define PCI_GLI_9755_PM_STATE GENMASK(1, 0)
15736ed2fd3SBen Chuang
158fcf890ecSVictor Shih #define PCI_GLI_9755_CORRERR_MASK 0x214
159fcf890ecSVictor Shih #define PCI_GLI_9755_CORRERR_MASK_REPLAY_TIMER_TIMEOUT BIT(12)
160fcf890ecSVictor Shih
161f3a5b56cSVictor Shih #define SDHCI_GLI_9767_GM_BURST_SIZE 0x510
162f3a5b56cSVictor Shih #define SDHCI_GLI_9767_GM_BURST_SIZE_AXI_ALWAYS_SET BIT(8)
163f3a5b56cSVictor Shih
164f3a5b56cSVictor Shih #define PCIE_GLI_9767_VHS 0x884
165f3a5b56cSVictor Shih #define GLI_9767_VHS_REV GENMASK(19, 16)
166f3a5b56cSVictor Shih #define GLI_9767_VHS_REV_R 0x0
167f3a5b56cSVictor Shih #define GLI_9767_VHS_REV_M 0x1
168f3a5b56cSVictor Shih #define GLI_9767_VHS_REV_W 0x2
169f3a5b56cSVictor Shih
170d2754355SVictor Shih #define PCIE_GLI_9767_COM_MAILBOX 0x888
171d2754355SVictor Shih #define PCIE_GLI_9767_COM_MAILBOX_SSC_EN BIT(1)
172d2754355SVictor Shih
173d2754355SVictor Shih #define PCIE_GLI_9767_CFG 0x8A0
174d2754355SVictor Shih #define PCIE_GLI_9767_CFG_LOW_PWR_OFF BIT(12)
175d2754355SVictor Shih
1760e92aec2SVictor Shih #define PCIE_GLI_9767_COMBO_MUX_CTL 0x8C8
1770e92aec2SVictor Shih #define PCIE_GLI_9767_COMBO_MUX_CTL_RST_EN BIT(6)
1780e92aec2SVictor Shih #define PCIE_GLI_9767_COMBO_MUX_CTL_WAIT_PERST_EN BIT(10)
1790e92aec2SVictor Shih
180f3a5b56cSVictor Shih #define PCIE_GLI_9767_PWR_MACRO_CTL 0x8D0
181f3a5b56cSVictor Shih #define PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE GENMASK(3, 0)
182f3a5b56cSVictor Shih #define PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE GENMASK(15, 12)
183f3a5b56cSVictor Shih #define PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE_VALUE 0x7
184f3a5b56cSVictor Shih #define PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL GENMASK(29, 28)
185f3a5b56cSVictor Shih #define PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL_VALUE 0x3
186f3a5b56cSVictor Shih
187f3a5b56cSVictor Shih #define PCIE_GLI_9767_SCR 0x8E0
188f3a5b56cSVictor Shih #define PCIE_GLI_9767_SCR_AUTO_AXI_W_BURST BIT(6)
189f3a5b56cSVictor Shih #define PCIE_GLI_9767_SCR_AUTO_AXI_R_BURST BIT(7)
190f3a5b56cSVictor Shih #define PCIE_GLI_9767_SCR_AXI_REQ BIT(9)
191f3a5b56cSVictor Shih #define PCIE_GLI_9767_SCR_CARD_DET_PWR_SAVING_EN BIT(10)
192f3a5b56cSVictor Shih #define PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE0 BIT(16)
193f3a5b56cSVictor Shih #define PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE1 BIT(17)
194f3a5b56cSVictor Shih #define PCIE_GLI_9767_SCR_CORE_PWR_D3_OFF BIT(21)
195f3a5b56cSVictor Shih #define PCIE_GLI_9767_SCR_CFG_RST_DATA_LINK_DOWN BIT(30)
196f3a5b56cSVictor Shih
1970e92aec2SVictor Shih #define PCIE_GLI_9767_SDHC_CAP 0x91C
1980e92aec2SVictor Shih #define PCIE_GLI_9767_SDHC_CAP_SDEI_RESULT BIT(5)
1990e92aec2SVictor Shih
200d2754355SVictor Shih #define PCIE_GLI_9767_SD_PLL_CTL 0x938
201d2754355SVictor Shih #define PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV GENMASK(9, 0)
202d2754355SVictor Shih #define PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV GENMASK(15, 12)
203d2754355SVictor Shih #define PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN BIT(16)
204d2754355SVictor Shih #define PCIE_GLI_9767_SD_PLL_CTL_SSC_EN BIT(19)
205d2754355SVictor Shih #define PCIE_GLI_9767_SD_PLL_CTL_SSC_STEP_SETTING GENMASK(28, 24)
206d2754355SVictor Shih
207d2754355SVictor Shih #define PCIE_GLI_9767_SD_PLL_CTL2 0x93C
208d2754355SVictor Shih #define PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM GENMASK(31, 16)
209d2754355SVictor Shih
2100e92aec2SVictor Shih #define PCIE_GLI_9767_SD_EXPRESS_CTL 0x940
2110e92aec2SVictor Shih #define PCIE_GLI_9767_SD_EXPRESS_CTL_SDEI_EXE BIT(0)
2120e92aec2SVictor Shih #define PCIE_GLI_9767_SD_EXPRESS_CTL_SD_EXPRESS_MODE BIT(1)
2130e92aec2SVictor Shih
2140e92aec2SVictor Shih #define PCIE_GLI_9767_SD_DATA_MULTI_CTL 0x944
2150e92aec2SVictor Shih #define PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME GENMASK(23, 16)
2160e92aec2SVictor Shih #define PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME_VALUE 0x64
2170e92aec2SVictor Shih
2180e92aec2SVictor Shih #define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2 0x950
2190e92aec2SVictor Shih #define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2_SDEI_COMPLETE BIT(0)
2200e92aec2SVictor Shih
2210e92aec2SVictor Shih #define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2 0x954
2220e92aec2SVictor Shih #define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2_SDEI_COMPLETE_STATUS_EN BIT(0)
2230e92aec2SVictor Shih
2240e92aec2SVictor Shih #define PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2 0x958
2250e92aec2SVictor Shih #define PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2_SDEI_COMPLETE_SIGNAL_EN BIT(0)
2260e92aec2SVictor Shih
227e51df6ceSBen Chuang #define GLI_MAX_TUNING_LOOP 40
228e51df6ceSBen Chuang
229e51df6ceSBen Chuang /* Genesys Logic chipset */
gl9750_wt_on(struct sdhci_host * host)230e51df6ceSBen Chuang static inline void gl9750_wt_on(struct sdhci_host *host)
231e51df6ceSBen Chuang {
232e51df6ceSBen Chuang u32 wt_value;
233e51df6ceSBen Chuang u32 wt_enable;
234e51df6ceSBen Chuang
235e51df6ceSBen Chuang wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT);
236e51df6ceSBen Chuang wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value);
237e51df6ceSBen Chuang
238e51df6ceSBen Chuang if (wt_enable == GLI_9750_WT_EN_ON)
239e51df6ceSBen Chuang return;
240e51df6ceSBen Chuang
241e51df6ceSBen Chuang wt_value &= ~SDHCI_GLI_9750_WT_EN;
242e51df6ceSBen Chuang wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_ON);
243e51df6ceSBen Chuang
244e51df6ceSBen Chuang sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT);
245e51df6ceSBen Chuang }
246e51df6ceSBen Chuang
gl9750_wt_off(struct sdhci_host * host)247e51df6ceSBen Chuang static inline void gl9750_wt_off(struct sdhci_host *host)
248e51df6ceSBen Chuang {
249e51df6ceSBen Chuang u32 wt_value;
250e51df6ceSBen Chuang u32 wt_enable;
251e51df6ceSBen Chuang
252e51df6ceSBen Chuang wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT);
253e51df6ceSBen Chuang wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value);
254e51df6ceSBen Chuang
255e51df6ceSBen Chuang if (wt_enable == GLI_9750_WT_EN_OFF)
256e51df6ceSBen Chuang return;
257e51df6ceSBen Chuang
258e51df6ceSBen Chuang wt_value &= ~SDHCI_GLI_9750_WT_EN;
259e51df6ceSBen Chuang wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_OFF);
260e51df6ceSBen Chuang
261e51df6ceSBen Chuang sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT);
262e51df6ceSBen Chuang }
263e51df6ceSBen Chuang
gli_set_9750(struct sdhci_host * host)264e51df6ceSBen Chuang static void gli_set_9750(struct sdhci_host *host)
265e51df6ceSBen Chuang {
266e51df6ceSBen Chuang u32 driving_value;
267e51df6ceSBen Chuang u32 pll_value;
268e51df6ceSBen Chuang u32 sw_ctrl_value;
269e51df6ceSBen Chuang u32 misc_value;
270e51df6ceSBen Chuang u32 parameter_value;
271e51df6ceSBen Chuang u32 control_value;
272e51df6ceSBen Chuang u16 ctrl2;
273e51df6ceSBen Chuang
274e51df6ceSBen Chuang gl9750_wt_on(host);
275e51df6ceSBen Chuang
276e51df6ceSBen Chuang driving_value = sdhci_readl(host, SDHCI_GLI_9750_DRIVING);
277e51df6ceSBen Chuang pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL);
278e51df6ceSBen Chuang sw_ctrl_value = sdhci_readl(host, SDHCI_GLI_9750_SW_CTRL);
279e51df6ceSBen Chuang misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC);
280e51df6ceSBen Chuang parameter_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_PARAMETERS);
281e51df6ceSBen Chuang control_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_CONTROL);
282e51df6ceSBen Chuang
283e51df6ceSBen Chuang driving_value &= ~(SDHCI_GLI_9750_DRIVING_1);
284e51df6ceSBen Chuang driving_value &= ~(SDHCI_GLI_9750_DRIVING_2);
285e51df6ceSBen Chuang driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_1,
286e51df6ceSBen Chuang GLI_9750_DRIVING_1_VALUE);
287e51df6ceSBen Chuang driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_2,
288e51df6ceSBen Chuang GLI_9750_DRIVING_2_VALUE);
289b56ff195SBen Chuang driving_value &= ~(SDHCI_GLI_9750_SEL_1|SDHCI_GLI_9750_SEL_2|SDHCI_GLI_9750_ALL_RST);
290b56ff195SBen Chuang driving_value |= SDHCI_GLI_9750_SEL_2;
291e51df6ceSBen Chuang sdhci_writel(host, driving_value, SDHCI_GLI_9750_DRIVING);
292e51df6ceSBen Chuang
293e51df6ceSBen Chuang sw_ctrl_value &= ~SDHCI_GLI_9750_SW_CTRL_4;
294e51df6ceSBen Chuang sw_ctrl_value |= FIELD_PREP(SDHCI_GLI_9750_SW_CTRL_4,
295e51df6ceSBen Chuang GLI_9750_SW_CTRL_4_VALUE);
296e51df6ceSBen Chuang sdhci_writel(host, sw_ctrl_value, SDHCI_GLI_9750_SW_CTRL);
297e51df6ceSBen Chuang
298e51df6ceSBen Chuang /* reset the tuning flow after reinit and before starting tuning */
299e51df6ceSBen Chuang pll_value &= ~SDHCI_GLI_9750_PLL_TX2_INV;
300e51df6ceSBen Chuang pll_value &= ~SDHCI_GLI_9750_PLL_TX2_DLY;
301e51df6ceSBen Chuang pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_INV,
302e51df6ceSBen Chuang GLI_9750_PLL_TX2_INV_VALUE);
303e51df6ceSBen Chuang pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_DLY,
304e51df6ceSBen Chuang GLI_9750_PLL_TX2_DLY_VALUE);
305e51df6ceSBen Chuang
306e51df6ceSBen Chuang misc_value &= ~SDHCI_GLI_9750_MISC_TX1_INV;
307e51df6ceSBen Chuang misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV;
308e51df6ceSBen Chuang misc_value &= ~SDHCI_GLI_9750_MISC_TX1_DLY;
309e51df6ceSBen Chuang misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_INV,
310e51df6ceSBen Chuang GLI_9750_MISC_TX1_INV_VALUE);
311e51df6ceSBen Chuang misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV,
312e51df6ceSBen Chuang GLI_9750_MISC_RX_INV_VALUE);
313e51df6ceSBen Chuang misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_DLY,
314e51df6ceSBen Chuang GLI_9750_MISC_TX1_DLY_VALUE);
315e51df6ceSBen Chuang
316e51df6ceSBen Chuang parameter_value &= ~SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY;
317e51df6ceSBen Chuang parameter_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY,
318e51df6ceSBen Chuang GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE);
319e51df6ceSBen Chuang
320e51df6ceSBen Chuang control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1;
321e51df6ceSBen Chuang control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2;
322e51df6ceSBen Chuang control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1,
323e51df6ceSBen Chuang GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE);
324e51df6ceSBen Chuang control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2,
325e51df6ceSBen Chuang GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE);
326e51df6ceSBen Chuang
327e51df6ceSBen Chuang sdhci_writel(host, pll_value, SDHCI_GLI_9750_PLL);
328e51df6ceSBen Chuang sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC);
329e51df6ceSBen Chuang
330e51df6ceSBen Chuang /* disable tuned clk */
331e51df6ceSBen Chuang ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
332e51df6ceSBen Chuang ctrl2 &= ~SDHCI_CTRL_TUNED_CLK;
333e51df6ceSBen Chuang sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
334e51df6ceSBen Chuang
335e51df6ceSBen Chuang /* enable tuning parameters control */
336e51df6ceSBen Chuang control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN;
337e51df6ceSBen Chuang control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN,
338e51df6ceSBen Chuang GLI_9750_TUNING_CONTROL_EN_ON);
339e51df6ceSBen Chuang sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL);
340e51df6ceSBen Chuang
341e51df6ceSBen Chuang /* write tuning parameters */
342e51df6ceSBen Chuang sdhci_writel(host, parameter_value, SDHCI_GLI_9750_TUNING_PARAMETERS);
343e51df6ceSBen Chuang
344e51df6ceSBen Chuang /* disable tuning parameters control */
345e51df6ceSBen Chuang control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN;
346e51df6ceSBen Chuang control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN,
347e51df6ceSBen Chuang GLI_9750_TUNING_CONTROL_EN_OFF);
348e51df6ceSBen Chuang sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL);
349e51df6ceSBen Chuang
350e51df6ceSBen Chuang /* clear tuned clk */
351e51df6ceSBen Chuang ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
352e51df6ceSBen Chuang ctrl2 &= ~SDHCI_CTRL_TUNED_CLK;
353e51df6ceSBen Chuang sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
354e51df6ceSBen Chuang
355e51df6ceSBen Chuang gl9750_wt_off(host);
356e51df6ceSBen Chuang }
357e51df6ceSBen Chuang
gli_set_9750_rx_inv(struct sdhci_host * host,bool b)358e51df6ceSBen Chuang static void gli_set_9750_rx_inv(struct sdhci_host *host, bool b)
359e51df6ceSBen Chuang {
360e51df6ceSBen Chuang u32 misc_value;
361e51df6ceSBen Chuang
362e51df6ceSBen Chuang gl9750_wt_on(host);
363e51df6ceSBen Chuang
364e51df6ceSBen Chuang misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC);
365e51df6ceSBen Chuang misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV;
366e51df6ceSBen Chuang if (b) {
367e51df6ceSBen Chuang misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV,
368e51df6ceSBen Chuang GLI_9750_MISC_RX_INV_ON);
369e51df6ceSBen Chuang } else {
370e51df6ceSBen Chuang misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV,
371e51df6ceSBen Chuang GLI_9750_MISC_RX_INV_OFF);
372e51df6ceSBen Chuang }
373e51df6ceSBen Chuang sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC);
374e51df6ceSBen Chuang
375e51df6ceSBen Chuang gl9750_wt_off(host);
376e51df6ceSBen Chuang }
377e51df6ceSBen Chuang
__sdhci_execute_tuning_9750(struct sdhci_host * host,u32 opcode)378e51df6ceSBen Chuang static int __sdhci_execute_tuning_9750(struct sdhci_host *host, u32 opcode)
379e51df6ceSBen Chuang {
380e51df6ceSBen Chuang int i;
381e51df6ceSBen Chuang int rx_inv;
382e51df6ceSBen Chuang
383e51df6ceSBen Chuang for (rx_inv = 0; rx_inv < 2; rx_inv++) {
384e51df6ceSBen Chuang gli_set_9750_rx_inv(host, !!rx_inv);
385e51df6ceSBen Chuang sdhci_start_tuning(host);
386e51df6ceSBen Chuang
387e51df6ceSBen Chuang for (i = 0; i < GLI_MAX_TUNING_LOOP; i++) {
388e51df6ceSBen Chuang u16 ctrl;
389e51df6ceSBen Chuang
390e51df6ceSBen Chuang sdhci_send_tuning(host, opcode);
391e51df6ceSBen Chuang
392e51df6ceSBen Chuang if (!host->tuning_done) {
393e51df6ceSBen Chuang sdhci_abort_tuning(host, opcode);
394e51df6ceSBen Chuang break;
395e51df6ceSBen Chuang }
396e51df6ceSBen Chuang
397e51df6ceSBen Chuang ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
398e51df6ceSBen Chuang if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
399e51df6ceSBen Chuang if (ctrl & SDHCI_CTRL_TUNED_CLK)
400e51df6ceSBen Chuang return 0; /* Success! */
401e51df6ceSBen Chuang break;
402e51df6ceSBen Chuang }
403e51df6ceSBen Chuang }
404e51df6ceSBen Chuang }
405e51df6ceSBen Chuang if (!host->tuning_done) {
406e51df6ceSBen Chuang pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n",
407e51df6ceSBen Chuang mmc_hostname(host->mmc));
408e51df6ceSBen Chuang return -ETIMEDOUT;
409e51df6ceSBen Chuang }
410e51df6ceSBen Chuang
411e51df6ceSBen Chuang pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
412e51df6ceSBen Chuang mmc_hostname(host->mmc));
413e51df6ceSBen Chuang sdhci_reset_tuning(host);
414e51df6ceSBen Chuang
415e51df6ceSBen Chuang return -EAGAIN;
416e51df6ceSBen Chuang }
417e51df6ceSBen Chuang
gl9750_execute_tuning(struct sdhci_host * host,u32 opcode)418e51df6ceSBen Chuang static int gl9750_execute_tuning(struct sdhci_host *host, u32 opcode)
419e51df6ceSBen Chuang {
420e51df6ceSBen Chuang host->mmc->retune_period = 0;
421e51df6ceSBen Chuang if (host->tuning_mode == SDHCI_TUNING_MODE_1)
422e51df6ceSBen Chuang host->mmc->retune_period = host->tuning_count;
423e51df6ceSBen Chuang
424e51df6ceSBen Chuang gli_set_9750(host);
425e51df6ceSBen Chuang host->tuning_err = __sdhci_execute_tuning_9750(host, opcode);
426e51df6ceSBen Chuang sdhci_end_tuning(host);
427e51df6ceSBen Chuang
428e51df6ceSBen Chuang return 0;
429e51df6ceSBen Chuang }
430e51df6ceSBen Chuang
gl9750_disable_ssc_pll(struct sdhci_host * host)431786d33c8SBen Chuang static void gl9750_disable_ssc_pll(struct sdhci_host *host)
432786d33c8SBen Chuang {
433786d33c8SBen Chuang u32 pll;
434786d33c8SBen Chuang
435786d33c8SBen Chuang gl9750_wt_on(host);
436786d33c8SBen Chuang pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
437786d33c8SBen Chuang pll &= ~(SDHCI_GLI_9750_PLL_DIR | SDHCI_GLI_9750_PLLSSC_EN);
438786d33c8SBen Chuang sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
439786d33c8SBen Chuang gl9750_wt_off(host);
440786d33c8SBen Chuang }
441786d33c8SBen Chuang
gl9750_set_pll(struct sdhci_host * host,u8 dir,u16 ldiv,u8 pdiv)442786d33c8SBen Chuang static void gl9750_set_pll(struct sdhci_host *host, u8 dir, u16 ldiv, u8 pdiv)
443786d33c8SBen Chuang {
444786d33c8SBen Chuang u32 pll;
445786d33c8SBen Chuang
446786d33c8SBen Chuang gl9750_wt_on(host);
447786d33c8SBen Chuang pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
448786d33c8SBen Chuang pll &= ~(SDHCI_GLI_9750_PLL_LDIV |
449786d33c8SBen Chuang SDHCI_GLI_9750_PLL_PDIV |
450786d33c8SBen Chuang SDHCI_GLI_9750_PLL_DIR);
451786d33c8SBen Chuang pll |= FIELD_PREP(SDHCI_GLI_9750_PLL_LDIV, ldiv) |
452786d33c8SBen Chuang FIELD_PREP(SDHCI_GLI_9750_PLL_PDIV, pdiv) |
453786d33c8SBen Chuang FIELD_PREP(SDHCI_GLI_9750_PLL_DIR, dir);
454786d33c8SBen Chuang sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
455786d33c8SBen Chuang gl9750_wt_off(host);
456786d33c8SBen Chuang
457786d33c8SBen Chuang /* wait for pll stable */
458786d33c8SBen Chuang mdelay(1);
459786d33c8SBen Chuang }
460786d33c8SBen Chuang
gl9750_ssc_enable(struct sdhci_host * host)46108df1a50SBen Chuang static bool gl9750_ssc_enable(struct sdhci_host *host)
46208df1a50SBen Chuang {
46308df1a50SBen Chuang u32 misc;
46408df1a50SBen Chuang u8 off;
46508df1a50SBen Chuang
46608df1a50SBen Chuang gl9750_wt_on(host);
46708df1a50SBen Chuang misc = sdhci_readl(host, SDHCI_GLI_9750_MISC);
46808df1a50SBen Chuang off = FIELD_GET(SDHCI_GLI_9750_MISC_SSC_OFF, misc);
46908df1a50SBen Chuang gl9750_wt_off(host);
47008df1a50SBen Chuang
47108df1a50SBen Chuang return !off;
47208df1a50SBen Chuang }
47308df1a50SBen Chuang
gl9750_set_ssc(struct sdhci_host * host,u8 enable,u8 step,u16 ppm)474786d33c8SBen Chuang static void gl9750_set_ssc(struct sdhci_host *host, u8 enable, u8 step, u16 ppm)
475786d33c8SBen Chuang {
476786d33c8SBen Chuang u32 pll;
477786d33c8SBen Chuang u32 ssc;
478786d33c8SBen Chuang
479786d33c8SBen Chuang gl9750_wt_on(host);
480786d33c8SBen Chuang pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
481786d33c8SBen Chuang ssc = sdhci_readl(host, SDHCI_GLI_9750_PLLSSC);
482786d33c8SBen Chuang pll &= ~(SDHCI_GLI_9750_PLLSSC_STEP |
483786d33c8SBen Chuang SDHCI_GLI_9750_PLLSSC_EN);
484786d33c8SBen Chuang ssc &= ~SDHCI_GLI_9750_PLLSSC_PPM;
485786d33c8SBen Chuang pll |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_STEP, step) |
486786d33c8SBen Chuang FIELD_PREP(SDHCI_GLI_9750_PLLSSC_EN, enable);
487786d33c8SBen Chuang ssc |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_PPM, ppm);
488786d33c8SBen Chuang sdhci_writel(host, ssc, SDHCI_GLI_9750_PLLSSC);
489786d33c8SBen Chuang sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
490786d33c8SBen Chuang gl9750_wt_off(host);
491786d33c8SBen Chuang }
492786d33c8SBen Chuang
gl9750_set_ssc_pll_205mhz(struct sdhci_host * host)493786d33c8SBen Chuang static void gl9750_set_ssc_pll_205mhz(struct sdhci_host *host)
494786d33c8SBen Chuang {
49508df1a50SBen Chuang bool enable = gl9750_ssc_enable(host);
49608df1a50SBen Chuang
49708df1a50SBen Chuang /* set pll to 205MHz and ssc */
49808df1a50SBen Chuang gl9750_set_ssc(host, enable, 0xF, 0x5A1D);
499786d33c8SBen Chuang gl9750_set_pll(host, 0x1, 0x246, 0x0);
500786d33c8SBen Chuang }
501786d33c8SBen Chuang
gl9750_set_ssc_pll_100mhz(struct sdhci_host * host)502d3c6bdb6SBen Chuang static void gl9750_set_ssc_pll_100mhz(struct sdhci_host *host)
503d3c6bdb6SBen Chuang {
50408df1a50SBen Chuang bool enable = gl9750_ssc_enable(host);
50508df1a50SBen Chuang
50608df1a50SBen Chuang /* set pll to 100MHz and ssc */
50708df1a50SBen Chuang gl9750_set_ssc(host, enable, 0xE, 0x51EC);
508d3c6bdb6SBen Chuang gl9750_set_pll(host, 0x1, 0x244, 0x1);
509d3c6bdb6SBen Chuang }
510d3c6bdb6SBen Chuang
gl9750_set_ssc_pll_50mhz(struct sdhci_host * host)511d3c6bdb6SBen Chuang static void gl9750_set_ssc_pll_50mhz(struct sdhci_host *host)
512d3c6bdb6SBen Chuang {
51308df1a50SBen Chuang bool enable = gl9750_ssc_enable(host);
51408df1a50SBen Chuang
51508df1a50SBen Chuang /* set pll to 50MHz and ssc */
51608df1a50SBen Chuang gl9750_set_ssc(host, enable, 0xE, 0x51EC);
517d3c6bdb6SBen Chuang gl9750_set_pll(host, 0x1, 0x244, 0x3);
518d3c6bdb6SBen Chuang }
519d3c6bdb6SBen Chuang
sdhci_gl9750_set_clock(struct sdhci_host * host,unsigned int clock)520786d33c8SBen Chuang static void sdhci_gl9750_set_clock(struct sdhci_host *host, unsigned int clock)
521786d33c8SBen Chuang {
522786d33c8SBen Chuang struct mmc_ios *ios = &host->mmc->ios;
523786d33c8SBen Chuang u16 clk;
524786d33c8SBen Chuang
525786d33c8SBen Chuang host->mmc->actual_clock = 0;
526786d33c8SBen Chuang
527786d33c8SBen Chuang gl9750_disable_ssc_pll(host);
528786d33c8SBen Chuang sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
529786d33c8SBen Chuang
530786d33c8SBen Chuang if (clock == 0)
531786d33c8SBen Chuang return;
532786d33c8SBen Chuang
533786d33c8SBen Chuang clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
534786d33c8SBen Chuang if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) {
535786d33c8SBen Chuang host->mmc->actual_clock = 205000000;
536786d33c8SBen Chuang gl9750_set_ssc_pll_205mhz(host);
537d3c6bdb6SBen Chuang } else if (clock == 100000000) {
538d3c6bdb6SBen Chuang gl9750_set_ssc_pll_100mhz(host);
539d3c6bdb6SBen Chuang } else if (clock == 50000000) {
540d3c6bdb6SBen Chuang gl9750_set_ssc_pll_50mhz(host);
541786d33c8SBen Chuang }
542786d33c8SBen Chuang
543786d33c8SBen Chuang sdhci_enable_clk(host, clk);
544786d33c8SBen Chuang }
545786d33c8SBen Chuang
gl9750_hw_setting(struct sdhci_host * host)5469751baccSBen Chuang static void gl9750_hw_setting(struct sdhci_host *host)
5479751baccSBen Chuang {
548cd93b795SVictor Shih struct sdhci_pci_slot *slot = sdhci_priv(host);
549cd93b795SVictor Shih struct pci_dev *pdev;
5509751baccSBen Chuang u32 value;
5519751baccSBen Chuang
552cd93b795SVictor Shih pdev = slot->chip->pdev;
553cd93b795SVictor Shih
5549751baccSBen Chuang gl9750_wt_on(host);
5559751baccSBen Chuang
5569751baccSBen Chuang value = sdhci_readl(host, SDHCI_GLI_9750_CFG2);
5579751baccSBen Chuang value &= ~SDHCI_GLI_9750_CFG2_L1DLY;
5589751baccSBen Chuang /* set ASPM L1 entry delay to 7.9us */
5599751baccSBen Chuang value |= FIELD_PREP(SDHCI_GLI_9750_CFG2_L1DLY,
5609751baccSBen Chuang GLI_9750_CFG2_L1DLY_VALUE);
5619751baccSBen Chuang sdhci_writel(host, value, SDHCI_GLI_9750_CFG2);
5629751baccSBen Chuang
563cd93b795SVictor Shih /* toggle PM state to allow GL9750 to enter ASPM L1.2 */
564cd93b795SVictor Shih pci_read_config_dword(pdev, PCI_GLI_9750_PM_CTRL, &value);
565cd93b795SVictor Shih value |= PCI_GLI_9750_PM_STATE;
566cd93b795SVictor Shih pci_write_config_dword(pdev, PCI_GLI_9750_PM_CTRL, value);
567cd93b795SVictor Shih value &= ~PCI_GLI_9750_PM_STATE;
568cd93b795SVictor Shih pci_write_config_dword(pdev, PCI_GLI_9750_PM_CTRL, value);
569cd93b795SVictor Shih
570ea672572SVictor Shih /* mask the replay timer timeout of AER */
571ea672572SVictor Shih pci_read_config_dword(pdev, PCI_GLI_9750_CORRERR_MASK, &value);
572ea672572SVictor Shih value |= PCI_GLI_9750_CORRERR_MASK_REPLAY_TIMER_TIMEOUT;
573ea672572SVictor Shih pci_write_config_dword(pdev, PCI_GLI_9750_CORRERR_MASK, value);
574ea672572SVictor Shih
5759751baccSBen Chuang gl9750_wt_off(host);
5769751baccSBen Chuang }
5779751baccSBen Chuang
gli_pcie_enable_msi(struct sdhci_pci_slot * slot)57831e43f31SBen Chuang static void gli_pcie_enable_msi(struct sdhci_pci_slot *slot)
57931e43f31SBen Chuang {
58031e43f31SBen Chuang int ret;
58131e43f31SBen Chuang
58231e43f31SBen Chuang ret = pci_alloc_irq_vectors(slot->chip->pdev, 1, 1,
58331e43f31SBen Chuang PCI_IRQ_MSI | PCI_IRQ_MSIX);
58431e43f31SBen Chuang if (ret < 0) {
58531e43f31SBen Chuang pr_warn("%s: enable PCI MSI failed, error=%d\n",
58631e43f31SBen Chuang mmc_hostname(slot->host->mmc), ret);
58731e43f31SBen Chuang return;
58831e43f31SBen Chuang }
58931e43f31SBen Chuang
59031e43f31SBen Chuang slot->host->irq = pci_irq_vector(slot->chip->pdev, 0);
59131e43f31SBen Chuang }
59231e43f31SBen Chuang
gl9755_wt_on(struct pci_dev * pdev)593786d33c8SBen Chuang static inline void gl9755_wt_on(struct pci_dev *pdev)
594786d33c8SBen Chuang {
595786d33c8SBen Chuang u32 wt_value;
596786d33c8SBen Chuang u32 wt_enable;
597786d33c8SBen Chuang
598786d33c8SBen Chuang pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value);
599786d33c8SBen Chuang wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value);
600786d33c8SBen Chuang
601786d33c8SBen Chuang if (wt_enable == GLI_9755_WT_EN_ON)
602786d33c8SBen Chuang return;
603786d33c8SBen Chuang
604786d33c8SBen Chuang wt_value &= ~PCI_GLI_9755_WT_EN;
605786d33c8SBen Chuang wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_ON);
606786d33c8SBen Chuang
607786d33c8SBen Chuang pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value);
608786d33c8SBen Chuang }
609786d33c8SBen Chuang
gl9755_wt_off(struct pci_dev * pdev)610786d33c8SBen Chuang static inline void gl9755_wt_off(struct pci_dev *pdev)
611786d33c8SBen Chuang {
612786d33c8SBen Chuang u32 wt_value;
613786d33c8SBen Chuang u32 wt_enable;
614786d33c8SBen Chuang
615786d33c8SBen Chuang pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value);
616786d33c8SBen Chuang wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value);
617786d33c8SBen Chuang
618786d33c8SBen Chuang if (wt_enable == GLI_9755_WT_EN_OFF)
619786d33c8SBen Chuang return;
620786d33c8SBen Chuang
621786d33c8SBen Chuang wt_value &= ~PCI_GLI_9755_WT_EN;
622786d33c8SBen Chuang wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_OFF);
623786d33c8SBen Chuang
624786d33c8SBen Chuang pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value);
625786d33c8SBen Chuang }
626786d33c8SBen Chuang
gl9755_disable_ssc_pll(struct pci_dev * pdev)627786d33c8SBen Chuang static void gl9755_disable_ssc_pll(struct pci_dev *pdev)
628786d33c8SBen Chuang {
629786d33c8SBen Chuang u32 pll;
630786d33c8SBen Chuang
631786d33c8SBen Chuang gl9755_wt_on(pdev);
632786d33c8SBen Chuang pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
633786d33c8SBen Chuang pll &= ~(PCI_GLI_9755_PLL_DIR | PCI_GLI_9755_PLLSSC_EN);
634786d33c8SBen Chuang pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
635786d33c8SBen Chuang gl9755_wt_off(pdev);
636786d33c8SBen Chuang }
637786d33c8SBen Chuang
gl9755_set_pll(struct pci_dev * pdev,u8 dir,u16 ldiv,u8 pdiv)638786d33c8SBen Chuang static void gl9755_set_pll(struct pci_dev *pdev, u8 dir, u16 ldiv, u8 pdiv)
639786d33c8SBen Chuang {
640786d33c8SBen Chuang u32 pll;
641786d33c8SBen Chuang
642786d33c8SBen Chuang gl9755_wt_on(pdev);
643786d33c8SBen Chuang pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
644786d33c8SBen Chuang pll &= ~(PCI_GLI_9755_PLL_LDIV |
645786d33c8SBen Chuang PCI_GLI_9755_PLL_PDIV |
646786d33c8SBen Chuang PCI_GLI_9755_PLL_DIR);
647786d33c8SBen Chuang pll |= FIELD_PREP(PCI_GLI_9755_PLL_LDIV, ldiv) |
648786d33c8SBen Chuang FIELD_PREP(PCI_GLI_9755_PLL_PDIV, pdiv) |
649786d33c8SBen Chuang FIELD_PREP(PCI_GLI_9755_PLL_DIR, dir);
650786d33c8SBen Chuang pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
651786d33c8SBen Chuang gl9755_wt_off(pdev);
652786d33c8SBen Chuang
653786d33c8SBen Chuang /* wait for pll stable */
654786d33c8SBen Chuang mdelay(1);
655786d33c8SBen Chuang }
656786d33c8SBen Chuang
gl9755_ssc_enable(struct pci_dev * pdev)65708df1a50SBen Chuang static bool gl9755_ssc_enable(struct pci_dev *pdev)
65808df1a50SBen Chuang {
65908df1a50SBen Chuang u32 misc;
66008df1a50SBen Chuang u8 off;
66108df1a50SBen Chuang
66208df1a50SBen Chuang gl9755_wt_on(pdev);
66308df1a50SBen Chuang pci_read_config_dword(pdev, PCI_GLI_9755_MISC, &misc);
66408df1a50SBen Chuang off = FIELD_GET(PCI_GLI_9755_MISC_SSC_OFF, misc);
66508df1a50SBen Chuang gl9755_wt_off(pdev);
66608df1a50SBen Chuang
66708df1a50SBen Chuang return !off;
66808df1a50SBen Chuang }
66908df1a50SBen Chuang
gl9755_set_ssc(struct pci_dev * pdev,u8 enable,u8 step,u16 ppm)670786d33c8SBen Chuang static void gl9755_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm)
671786d33c8SBen Chuang {
672786d33c8SBen Chuang u32 pll;
673786d33c8SBen Chuang u32 ssc;
674786d33c8SBen Chuang
675786d33c8SBen Chuang gl9755_wt_on(pdev);
676786d33c8SBen Chuang pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
677786d33c8SBen Chuang pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &ssc);
678786d33c8SBen Chuang pll &= ~(PCI_GLI_9755_PLLSSC_STEP |
679786d33c8SBen Chuang PCI_GLI_9755_PLLSSC_EN);
680786d33c8SBen Chuang ssc &= ~PCI_GLI_9755_PLLSSC_PPM;
681786d33c8SBen Chuang pll |= FIELD_PREP(PCI_GLI_9755_PLLSSC_STEP, step) |
682786d33c8SBen Chuang FIELD_PREP(PCI_GLI_9755_PLLSSC_EN, enable);
683786d33c8SBen Chuang ssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_PPM, ppm);
684786d33c8SBen Chuang pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, ssc);
685786d33c8SBen Chuang pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
686786d33c8SBen Chuang gl9755_wt_off(pdev);
687786d33c8SBen Chuang }
688786d33c8SBen Chuang
gl9755_set_ssc_pll_205mhz(struct pci_dev * pdev)689786d33c8SBen Chuang static void gl9755_set_ssc_pll_205mhz(struct pci_dev *pdev)
690786d33c8SBen Chuang {
69108df1a50SBen Chuang bool enable = gl9755_ssc_enable(pdev);
69208df1a50SBen Chuang
69308df1a50SBen Chuang /* set pll to 205MHz and ssc */
69408df1a50SBen Chuang gl9755_set_ssc(pdev, enable, 0xF, 0x5A1D);
695786d33c8SBen Chuang gl9755_set_pll(pdev, 0x1, 0x246, 0x0);
696786d33c8SBen Chuang }
697786d33c8SBen Chuang
gl9755_set_ssc_pll_100mhz(struct pci_dev * pdev)698d3c6bdb6SBen Chuang static void gl9755_set_ssc_pll_100mhz(struct pci_dev *pdev)
699d3c6bdb6SBen Chuang {
70008df1a50SBen Chuang bool enable = gl9755_ssc_enable(pdev);
70108df1a50SBen Chuang
70208df1a50SBen Chuang /* set pll to 100MHz and ssc */
70308df1a50SBen Chuang gl9755_set_ssc(pdev, enable, 0xE, 0x51EC);
704d3c6bdb6SBen Chuang gl9755_set_pll(pdev, 0x1, 0x244, 0x1);
705d3c6bdb6SBen Chuang }
706d3c6bdb6SBen Chuang
gl9755_set_ssc_pll_50mhz(struct pci_dev * pdev)707d3c6bdb6SBen Chuang static void gl9755_set_ssc_pll_50mhz(struct pci_dev *pdev)
708d3c6bdb6SBen Chuang {
70908df1a50SBen Chuang bool enable = gl9755_ssc_enable(pdev);
71008df1a50SBen Chuang
71108df1a50SBen Chuang /* set pll to 50MHz and ssc */
71208df1a50SBen Chuang gl9755_set_ssc(pdev, enable, 0xE, 0x51EC);
713d3c6bdb6SBen Chuang gl9755_set_pll(pdev, 0x1, 0x244, 0x3);
714d3c6bdb6SBen Chuang }
715d3c6bdb6SBen Chuang
sdhci_gl9755_set_clock(struct sdhci_host * host,unsigned int clock)716786d33c8SBen Chuang static void sdhci_gl9755_set_clock(struct sdhci_host *host, unsigned int clock)
717786d33c8SBen Chuang {
718786d33c8SBen Chuang struct sdhci_pci_slot *slot = sdhci_priv(host);
719786d33c8SBen Chuang struct mmc_ios *ios = &host->mmc->ios;
720786d33c8SBen Chuang struct pci_dev *pdev;
721786d33c8SBen Chuang u16 clk;
722786d33c8SBen Chuang
723786d33c8SBen Chuang pdev = slot->chip->pdev;
724786d33c8SBen Chuang host->mmc->actual_clock = 0;
725786d33c8SBen Chuang
726786d33c8SBen Chuang gl9755_disable_ssc_pll(pdev);
727786d33c8SBen Chuang sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
728786d33c8SBen Chuang
729786d33c8SBen Chuang if (clock == 0)
730786d33c8SBen Chuang return;
731786d33c8SBen Chuang
732786d33c8SBen Chuang clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
733786d33c8SBen Chuang if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) {
734786d33c8SBen Chuang host->mmc->actual_clock = 205000000;
735786d33c8SBen Chuang gl9755_set_ssc_pll_205mhz(pdev);
736d3c6bdb6SBen Chuang } else if (clock == 100000000) {
737d3c6bdb6SBen Chuang gl9755_set_ssc_pll_100mhz(pdev);
738d3c6bdb6SBen Chuang } else if (clock == 50000000) {
739d3c6bdb6SBen Chuang gl9755_set_ssc_pll_50mhz(pdev);
740786d33c8SBen Chuang }
741786d33c8SBen Chuang
742786d33c8SBen Chuang sdhci_enable_clk(host, clk);
743786d33c8SBen Chuang }
744786d33c8SBen Chuang
gl9755_hw_setting(struct sdhci_pci_slot * slot)7450f1d9961SBen Chuang static void gl9755_hw_setting(struct sdhci_pci_slot *slot)
7460f1d9961SBen Chuang {
7470f1d9961SBen Chuang struct pci_dev *pdev = slot->chip->pdev;
7480f1d9961SBen Chuang u32 value;
7490f1d9961SBen Chuang
7500f1d9961SBen Chuang gl9755_wt_on(pdev);
7510f1d9961SBen Chuang
7520f1d9961SBen Chuang pci_read_config_dword(pdev, PCI_GLI_9755_PECONF, &value);
753189f1d9bSHector Martin /*
754189f1d9bSHector Martin * Apple ARM64 platforms using these chips may have
755189f1d9bSHector Martin * inverted CD/WP detection.
756189f1d9bSHector Martin */
757189f1d9bSHector Martin if (of_property_read_bool(pdev->dev.of_node, "cd-inverted"))
758189f1d9bSHector Martin value |= PCI_GLI_9755_INVERT_CD;
759189f1d9bSHector Martin if (of_property_read_bool(pdev->dev.of_node, "wp-inverted"))
760189f1d9bSHector Martin value |= PCI_GLI_9755_INVERT_WP;
7610f1d9961SBen Chuang value &= ~PCI_GLI_9755_LFCLK;
7620f1d9961SBen Chuang value &= ~PCI_GLI_9755_DMACLK;
7630f1d9961SBen Chuang pci_write_config_dword(pdev, PCI_GLI_9755_PECONF, value);
7640f1d9961SBen Chuang
765f46b54ccSRenius Chen /* enable short circuit protection */
766f46b54ccSRenius Chen pci_read_config_dword(pdev, PCI_GLI_9755_SerDes, &value);
767f46b54ccSRenius Chen value &= ~PCI_GLI_9755_SCP_DIS;
768f46b54ccSRenius Chen pci_write_config_dword(pdev, PCI_GLI_9755_SerDes, value);
769f46b54ccSRenius Chen
7709751baccSBen Chuang pci_read_config_dword(pdev, PCI_GLI_9755_CFG2, &value);
7719751baccSBen Chuang value &= ~PCI_GLI_9755_CFG2_L1DLY;
7729751baccSBen Chuang /* set ASPM L1 entry delay to 7.9us */
7739751baccSBen Chuang value |= FIELD_PREP(PCI_GLI_9755_CFG2_L1DLY,
7749751baccSBen Chuang GLI_9755_CFG2_L1DLY_VALUE);
7759751baccSBen Chuang pci_write_config_dword(pdev, PCI_GLI_9755_CFG2, value);
7769751baccSBen Chuang
77736ed2fd3SBen Chuang /* toggle PM state to allow GL9755 to enter ASPM L1.2 */
77836ed2fd3SBen Chuang pci_read_config_dword(pdev, PCI_GLI_9755_PM_CTRL, &value);
77936ed2fd3SBen Chuang value |= PCI_GLI_9755_PM_STATE;
78036ed2fd3SBen Chuang pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value);
78136ed2fd3SBen Chuang value &= ~PCI_GLI_9755_PM_STATE;
78236ed2fd3SBen Chuang pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value);
78336ed2fd3SBen Chuang
784fcf890ecSVictor Shih /* mask the replay timer timeout of AER */
785fcf890ecSVictor Shih pci_read_config_dword(pdev, PCI_GLI_9755_CORRERR_MASK, &value);
786fcf890ecSVictor Shih value |= PCI_GLI_9755_CORRERR_MASK_REPLAY_TIMER_TIMEOUT;
787fcf890ecSVictor Shih pci_write_config_dword(pdev, PCI_GLI_9755_CORRERR_MASK, value);
788fcf890ecSVictor Shih
7890f1d9961SBen Chuang gl9755_wt_off(pdev);
7900f1d9961SBen Chuang }
7910f1d9961SBen Chuang
gl9767_vhs_read(struct pci_dev * pdev)792f3a5b56cSVictor Shih static inline void gl9767_vhs_read(struct pci_dev *pdev)
793f3a5b56cSVictor Shih {
794f3a5b56cSVictor Shih u32 vhs_enable;
795f3a5b56cSVictor Shih u32 vhs_value;
796f3a5b56cSVictor Shih
797f3a5b56cSVictor Shih pci_read_config_dword(pdev, PCIE_GLI_9767_VHS, &vhs_value);
798f3a5b56cSVictor Shih vhs_enable = FIELD_GET(GLI_9767_VHS_REV, vhs_value);
799f3a5b56cSVictor Shih
800f3a5b56cSVictor Shih if (vhs_enable == GLI_9767_VHS_REV_R)
801f3a5b56cSVictor Shih return;
802f3a5b56cSVictor Shih
803f3a5b56cSVictor Shih vhs_value &= ~GLI_9767_VHS_REV;
804f3a5b56cSVictor Shih vhs_value |= FIELD_PREP(GLI_9767_VHS_REV, GLI_9767_VHS_REV_R);
805f3a5b56cSVictor Shih
806f3a5b56cSVictor Shih pci_write_config_dword(pdev, PCIE_GLI_9767_VHS, vhs_value);
807f3a5b56cSVictor Shih }
808f3a5b56cSVictor Shih
gl9767_vhs_write(struct pci_dev * pdev)809f3a5b56cSVictor Shih static inline void gl9767_vhs_write(struct pci_dev *pdev)
810f3a5b56cSVictor Shih {
811f3a5b56cSVictor Shih u32 vhs_enable;
812f3a5b56cSVictor Shih u32 vhs_value;
813f3a5b56cSVictor Shih
814f3a5b56cSVictor Shih pci_read_config_dword(pdev, PCIE_GLI_9767_VHS, &vhs_value);
815f3a5b56cSVictor Shih vhs_enable = FIELD_GET(GLI_9767_VHS_REV, vhs_value);
816f3a5b56cSVictor Shih
817f3a5b56cSVictor Shih if (vhs_enable == GLI_9767_VHS_REV_W)
818f3a5b56cSVictor Shih return;
819f3a5b56cSVictor Shih
820f3a5b56cSVictor Shih vhs_value &= ~GLI_9767_VHS_REV;
821f3a5b56cSVictor Shih vhs_value |= FIELD_PREP(GLI_9767_VHS_REV, GLI_9767_VHS_REV_W);
822f3a5b56cSVictor Shih
823f3a5b56cSVictor Shih pci_write_config_dword(pdev, PCIE_GLI_9767_VHS, vhs_value);
824f3a5b56cSVictor Shih }
825f3a5b56cSVictor Shih
gl9767_ssc_enable(struct pci_dev * pdev)826d2754355SVictor Shih static bool gl9767_ssc_enable(struct pci_dev *pdev)
827d2754355SVictor Shih {
828d2754355SVictor Shih u32 value;
829d2754355SVictor Shih u8 enable;
830d2754355SVictor Shih
831d2754355SVictor Shih gl9767_vhs_write(pdev);
832d2754355SVictor Shih
833d2754355SVictor Shih pci_read_config_dword(pdev, PCIE_GLI_9767_COM_MAILBOX, &value);
834d2754355SVictor Shih enable = FIELD_GET(PCIE_GLI_9767_COM_MAILBOX_SSC_EN, value);
835d2754355SVictor Shih
836d2754355SVictor Shih gl9767_vhs_read(pdev);
837d2754355SVictor Shih
838d2754355SVictor Shih return enable;
839d2754355SVictor Shih }
840d2754355SVictor Shih
gl9767_set_ssc(struct pci_dev * pdev,u8 enable,u8 step,u16 ppm)841d2754355SVictor Shih static void gl9767_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm)
842d2754355SVictor Shih {
843d2754355SVictor Shih u32 pll;
844d2754355SVictor Shih u32 ssc;
845d2754355SVictor Shih
846d2754355SVictor Shih gl9767_vhs_write(pdev);
847d2754355SVictor Shih
848d2754355SVictor Shih pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll);
849d2754355SVictor Shih pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL2, &ssc);
850d2754355SVictor Shih pll &= ~(PCIE_GLI_9767_SD_PLL_CTL_SSC_STEP_SETTING |
851d2754355SVictor Shih PCIE_GLI_9767_SD_PLL_CTL_SSC_EN);
852d2754355SVictor Shih ssc &= ~PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM;
853d2754355SVictor Shih pll |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_SSC_STEP_SETTING, step) |
854d2754355SVictor Shih FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_SSC_EN, enable);
855d2754355SVictor Shih ssc |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM, ppm);
856d2754355SVictor Shih pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL2, ssc);
857d2754355SVictor Shih pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll);
858d2754355SVictor Shih
859d2754355SVictor Shih gl9767_vhs_read(pdev);
860d2754355SVictor Shih }
861d2754355SVictor Shih
gl9767_set_pll(struct pci_dev * pdev,u8 dir,u16 ldiv,u8 pdiv)862d2754355SVictor Shih static void gl9767_set_pll(struct pci_dev *pdev, u8 dir, u16 ldiv, u8 pdiv)
863d2754355SVictor Shih {
864d2754355SVictor Shih u32 pll;
865d2754355SVictor Shih
866d2754355SVictor Shih gl9767_vhs_write(pdev);
867d2754355SVictor Shih
868d2754355SVictor Shih pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll);
869d2754355SVictor Shih pll &= ~(PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV |
870d2754355SVictor Shih PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV |
871d2754355SVictor Shih PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN);
872d2754355SVictor Shih pll |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV, ldiv) |
873d2754355SVictor Shih FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV, pdiv) |
874d2754355SVictor Shih FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN, dir);
875d2754355SVictor Shih pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll);
876d2754355SVictor Shih
877d2754355SVictor Shih gl9767_vhs_read(pdev);
878d2754355SVictor Shih
879d2754355SVictor Shih /* wait for pll stable */
880d2754355SVictor Shih usleep_range(1000, 1100);
881d2754355SVictor Shih }
882d2754355SVictor Shih
gl9767_set_ssc_pll_205mhz(struct pci_dev * pdev)883d2754355SVictor Shih static void gl9767_set_ssc_pll_205mhz(struct pci_dev *pdev)
884d2754355SVictor Shih {
885d2754355SVictor Shih bool enable = gl9767_ssc_enable(pdev);
886d2754355SVictor Shih
887d2754355SVictor Shih /* set pll to 205MHz and ssc */
888d2754355SVictor Shih gl9767_set_ssc(pdev, enable, 0x1F, 0xF5C3);
889d2754355SVictor Shih gl9767_set_pll(pdev, 0x1, 0x246, 0x0);
890d2754355SVictor Shih }
891d2754355SVictor Shih
gl9767_disable_ssc_pll(struct pci_dev * pdev)892d2754355SVictor Shih static void gl9767_disable_ssc_pll(struct pci_dev *pdev)
893d2754355SVictor Shih {
894d2754355SVictor Shih u32 pll;
895d2754355SVictor Shih
896d2754355SVictor Shih gl9767_vhs_write(pdev);
897d2754355SVictor Shih
898d2754355SVictor Shih pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll);
899d2754355SVictor Shih pll &= ~(PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN | PCIE_GLI_9767_SD_PLL_CTL_SSC_EN);
900d2754355SVictor Shih pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll);
901d2754355SVictor Shih
902d2754355SVictor Shih gl9767_vhs_read(pdev);
903d2754355SVictor Shih }
904d2754355SVictor Shih
sdhci_gl9767_set_clock(struct sdhci_host * host,unsigned int clock)905d2754355SVictor Shih static void sdhci_gl9767_set_clock(struct sdhci_host *host, unsigned int clock)
906d2754355SVictor Shih {
907d2754355SVictor Shih struct sdhci_pci_slot *slot = sdhci_priv(host);
908d2754355SVictor Shih struct mmc_ios *ios = &host->mmc->ios;
909d2754355SVictor Shih struct pci_dev *pdev;
910d2754355SVictor Shih u32 value;
911d2754355SVictor Shih u16 clk;
912d2754355SVictor Shih
913d2754355SVictor Shih pdev = slot->chip->pdev;
914d2754355SVictor Shih host->mmc->actual_clock = 0;
915d2754355SVictor Shih
916d2754355SVictor Shih gl9767_vhs_write(pdev);
917d2754355SVictor Shih
918d2754355SVictor Shih pci_read_config_dword(pdev, PCIE_GLI_9767_CFG, &value);
919d2754355SVictor Shih value |= PCIE_GLI_9767_CFG_LOW_PWR_OFF;
920d2754355SVictor Shih pci_write_config_dword(pdev, PCIE_GLI_9767_CFG, value);
921d2754355SVictor Shih
922d2754355SVictor Shih gl9767_disable_ssc_pll(pdev);
923d2754355SVictor Shih sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
924d2754355SVictor Shih
925d2754355SVictor Shih if (clock == 0)
926d2754355SVictor Shih return;
927d2754355SVictor Shih
928d2754355SVictor Shih clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
929d2754355SVictor Shih if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) {
930d2754355SVictor Shih host->mmc->actual_clock = 205000000;
931d2754355SVictor Shih gl9767_set_ssc_pll_205mhz(pdev);
932d2754355SVictor Shih }
933d2754355SVictor Shih
934d2754355SVictor Shih sdhci_enable_clk(host, clk);
935d2754355SVictor Shih
936d2754355SVictor Shih pci_read_config_dword(pdev, PCIE_GLI_9767_CFG, &value);
937d2754355SVictor Shih value &= ~PCIE_GLI_9767_CFG_LOW_PWR_OFF;
938d2754355SVictor Shih pci_write_config_dword(pdev, PCIE_GLI_9767_CFG, value);
939d2754355SVictor Shih
940d2754355SVictor Shih gl9767_vhs_read(pdev);
941d2754355SVictor Shih }
942d2754355SVictor Shih
gli_set_9767(struct sdhci_host * host)943f3a5b56cSVictor Shih static void gli_set_9767(struct sdhci_host *host)
944f3a5b56cSVictor Shih {
945f3a5b56cSVictor Shih u32 value;
946f3a5b56cSVictor Shih
947f3a5b56cSVictor Shih value = sdhci_readl(host, SDHCI_GLI_9767_GM_BURST_SIZE);
948f3a5b56cSVictor Shih value &= ~SDHCI_GLI_9767_GM_BURST_SIZE_AXI_ALWAYS_SET;
949f3a5b56cSVictor Shih sdhci_writel(host, value, SDHCI_GLI_9767_GM_BURST_SIZE);
950f3a5b56cSVictor Shih }
951f3a5b56cSVictor Shih
gl9767_hw_setting(struct sdhci_pci_slot * slot)952f3a5b56cSVictor Shih static void gl9767_hw_setting(struct sdhci_pci_slot *slot)
953f3a5b56cSVictor Shih {
954f3a5b56cSVictor Shih struct pci_dev *pdev = slot->chip->pdev;
955f3a5b56cSVictor Shih u32 value;
956f3a5b56cSVictor Shih
957f3a5b56cSVictor Shih gl9767_vhs_write(pdev);
958f3a5b56cSVictor Shih
959f3a5b56cSVictor Shih pci_read_config_dword(pdev, PCIE_GLI_9767_PWR_MACRO_CTL, &value);
960f3a5b56cSVictor Shih value &= ~(PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE |
961f3a5b56cSVictor Shih PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE |
962f3a5b56cSVictor Shih PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL);
963f3a5b56cSVictor Shih
964f3a5b56cSVictor Shih value |= PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE |
965f3a5b56cSVictor Shih FIELD_PREP(PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE,
966f3a5b56cSVictor Shih PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE_VALUE) |
967f3a5b56cSVictor Shih FIELD_PREP(PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL,
968f3a5b56cSVictor Shih PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL_VALUE);
969f3a5b56cSVictor Shih pci_write_config_dword(pdev, PCIE_GLI_9767_PWR_MACRO_CTL, value);
970f3a5b56cSVictor Shih
971f3a5b56cSVictor Shih pci_read_config_dword(pdev, PCIE_GLI_9767_SCR, &value);
972f3a5b56cSVictor Shih value &= ~(PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE0 |
973f3a5b56cSVictor Shih PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE1 |
974f3a5b56cSVictor Shih PCIE_GLI_9767_SCR_CFG_RST_DATA_LINK_DOWN);
975f3a5b56cSVictor Shih
976f3a5b56cSVictor Shih value |= PCIE_GLI_9767_SCR_AUTO_AXI_W_BURST |
977f3a5b56cSVictor Shih PCIE_GLI_9767_SCR_AUTO_AXI_R_BURST |
978f3a5b56cSVictor Shih PCIE_GLI_9767_SCR_AXI_REQ |
979f3a5b56cSVictor Shih PCIE_GLI_9767_SCR_CARD_DET_PWR_SAVING_EN |
980f3a5b56cSVictor Shih PCIE_GLI_9767_SCR_CORE_PWR_D3_OFF;
981f3a5b56cSVictor Shih pci_write_config_dword(pdev, PCIE_GLI_9767_SCR, value);
982f3a5b56cSVictor Shih
983f3a5b56cSVictor Shih gl9767_vhs_read(pdev);
984f3a5b56cSVictor Shih }
985f3a5b56cSVictor Shih
sdhci_gl9767_reset(struct sdhci_host * host,u8 mask)986f3a5b56cSVictor Shih static void sdhci_gl9767_reset(struct sdhci_host *host, u8 mask)
987f3a5b56cSVictor Shih {
988f3a5b56cSVictor Shih sdhci_reset(host, mask);
989f3a5b56cSVictor Shih gli_set_9767(host);
990f3a5b56cSVictor Shih }
991f3a5b56cSVictor Shih
gl9767_init_sd_express(struct mmc_host * mmc,struct mmc_ios * ios)9920e92aec2SVictor Shih static int gl9767_init_sd_express(struct mmc_host *mmc, struct mmc_ios *ios)
9930e92aec2SVictor Shih {
9940e92aec2SVictor Shih struct sdhci_host *host = mmc_priv(mmc);
9950e92aec2SVictor Shih struct sdhci_pci_slot *slot = sdhci_priv(host);
9960e92aec2SVictor Shih struct pci_dev *pdev;
9970e92aec2SVictor Shih u32 value;
9980e92aec2SVictor Shih int i;
9990e92aec2SVictor Shih
10000e92aec2SVictor Shih pdev = slot->chip->pdev;
10010e92aec2SVictor Shih
10020e92aec2SVictor Shih if (mmc->ops->get_ro(mmc)) {
10030e92aec2SVictor Shih mmc->ios.timing &= ~(MMC_TIMING_SD_EXP | MMC_TIMING_SD_EXP_1_2V);
10040e92aec2SVictor Shih return 0;
10050e92aec2SVictor Shih }
10060e92aec2SVictor Shih
10070e92aec2SVictor Shih gl9767_vhs_write(pdev);
10080e92aec2SVictor Shih
10090e92aec2SVictor Shih pci_read_config_dword(pdev, PCIE_GLI_9767_COMBO_MUX_CTL, &value);
10100e92aec2SVictor Shih value &= ~(PCIE_GLI_9767_COMBO_MUX_CTL_RST_EN | PCIE_GLI_9767_COMBO_MUX_CTL_WAIT_PERST_EN);
10110e92aec2SVictor Shih pci_write_config_dword(pdev, PCIE_GLI_9767_COMBO_MUX_CTL, value);
10120e92aec2SVictor Shih
10130e92aec2SVictor Shih pci_read_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, &value);
10140e92aec2SVictor Shih value &= ~PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME;
10150e92aec2SVictor Shih value |= FIELD_PREP(PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME,
10160e92aec2SVictor Shih PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME_VALUE);
10170e92aec2SVictor Shih pci_write_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, value);
10180e92aec2SVictor Shih
10190e92aec2SVictor Shih pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2, &value);
10200e92aec2SVictor Shih value |= PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2_SDEI_COMPLETE;
10210e92aec2SVictor Shih pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2, value);
10220e92aec2SVictor Shih
10230e92aec2SVictor Shih pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2, &value);
10240e92aec2SVictor Shih value |= PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2_SDEI_COMPLETE_STATUS_EN;
10250e92aec2SVictor Shih pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2, value);
10260e92aec2SVictor Shih
10270e92aec2SVictor Shih pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2, &value);
10280e92aec2SVictor Shih value |= PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2_SDEI_COMPLETE_SIGNAL_EN;
10290e92aec2SVictor Shih pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2, value);
10300e92aec2SVictor Shih
10310e92aec2SVictor Shih pci_read_config_dword(pdev, PCIE_GLI_9767_CFG, &value);
10320e92aec2SVictor Shih value |= PCIE_GLI_9767_CFG_LOW_PWR_OFF;
10330e92aec2SVictor Shih pci_write_config_dword(pdev, PCIE_GLI_9767_CFG, value);
10340e92aec2SVictor Shih
10350e92aec2SVictor Shih value = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
10360e92aec2SVictor Shih value &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_PLL_EN);
10370e92aec2SVictor Shih sdhci_writew(host, value, SDHCI_CLOCK_CONTROL);
10380e92aec2SVictor Shih
10390e92aec2SVictor Shih value = sdhci_readb(host, SDHCI_POWER_CONTROL);
10400e92aec2SVictor Shih value |= (SDHCI_VDD2_POWER_180 | SDHCI_VDD2_POWER_ON);
10410e92aec2SVictor Shih sdhci_writeb(host, value, SDHCI_POWER_CONTROL);
10420e92aec2SVictor Shih
10430e92aec2SVictor Shih pci_read_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, &value);
10440e92aec2SVictor Shih value |= PCIE_GLI_9767_SD_EXPRESS_CTL_SDEI_EXE;
10450e92aec2SVictor Shih pci_write_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, value);
10460e92aec2SVictor Shih
10470e92aec2SVictor Shih for (i = 0; i < 2; i++) {
10480e92aec2SVictor Shih usleep_range(10000, 10100);
10490e92aec2SVictor Shih pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2, &value);
10500e92aec2SVictor Shih if (value & PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2_SDEI_COMPLETE) {
10510e92aec2SVictor Shih pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2,
10520e92aec2SVictor Shih value);
10530e92aec2SVictor Shih break;
10540e92aec2SVictor Shih }
10550e92aec2SVictor Shih }
10560e92aec2SVictor Shih
10570e92aec2SVictor Shih pci_read_config_dword(pdev, PCIE_GLI_9767_SDHC_CAP, &value);
10580e92aec2SVictor Shih if (value & PCIE_GLI_9767_SDHC_CAP_SDEI_RESULT) {
10590e92aec2SVictor Shih pci_read_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, &value);
10600e92aec2SVictor Shih value |= PCIE_GLI_9767_SD_EXPRESS_CTL_SD_EXPRESS_MODE;
10610e92aec2SVictor Shih pci_write_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, value);
10620e92aec2SVictor Shih } else {
10630e92aec2SVictor Shih mmc->ios.timing &= ~(MMC_TIMING_SD_EXP | MMC_TIMING_SD_EXP_1_2V);
10640e92aec2SVictor Shih
10650e92aec2SVictor Shih value = sdhci_readb(host, SDHCI_POWER_CONTROL);
10660e92aec2SVictor Shih value &= ~(SDHCI_VDD2_POWER_180 | SDHCI_VDD2_POWER_ON);
10670e92aec2SVictor Shih sdhci_writeb(host, value, SDHCI_POWER_CONTROL);
10680e92aec2SVictor Shih
10690e92aec2SVictor Shih value = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
10700e92aec2SVictor Shih value |= (SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_PLL_EN);
10710e92aec2SVictor Shih sdhci_writew(host, value, SDHCI_CLOCK_CONTROL);
10720e92aec2SVictor Shih }
10730e92aec2SVictor Shih
10740e92aec2SVictor Shih gl9767_vhs_read(pdev);
10750e92aec2SVictor Shih
10760e92aec2SVictor Shih return 0;
10770e92aec2SVictor Shih }
10780e92aec2SVictor Shih
gli_probe_slot_gl9750(struct sdhci_pci_slot * slot)1079e51df6ceSBen Chuang static int gli_probe_slot_gl9750(struct sdhci_pci_slot *slot)
1080e51df6ceSBen Chuang {
1081e51df6ceSBen Chuang struct sdhci_host *host = slot->host;
1082e51df6ceSBen Chuang
10839751baccSBen Chuang gl9750_hw_setting(host);
108431e43f31SBen Chuang gli_pcie_enable_msi(slot);
1085e51df6ceSBen Chuang slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
1086e51df6ceSBen Chuang sdhci_enable_v4_mode(host);
1087e51df6ceSBen Chuang
1088e51df6ceSBen Chuang return 0;
1089e51df6ceSBen Chuang }
1090e51df6ceSBen Chuang
gli_probe_slot_gl9755(struct sdhci_pci_slot * slot)1091e51df6ceSBen Chuang static int gli_probe_slot_gl9755(struct sdhci_pci_slot *slot)
1092e51df6ceSBen Chuang {
1093e51df6ceSBen Chuang struct sdhci_host *host = slot->host;
1094e51df6ceSBen Chuang
10950f1d9961SBen Chuang gl9755_hw_setting(slot);
109631e43f31SBen Chuang gli_pcie_enable_msi(slot);
1097e51df6ceSBen Chuang slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
1098e51df6ceSBen Chuang sdhci_enable_v4_mode(host);
1099e51df6ceSBen Chuang
1100e51df6ceSBen Chuang return 0;
1101e51df6ceSBen Chuang }
1102e51df6ceSBen Chuang
gli_probe_slot_gl9767(struct sdhci_pci_slot * slot)1103f3a5b56cSVictor Shih static int gli_probe_slot_gl9767(struct sdhci_pci_slot *slot)
1104f3a5b56cSVictor Shih {
1105f3a5b56cSVictor Shih struct sdhci_host *host = slot->host;
1106f3a5b56cSVictor Shih
1107f3a5b56cSVictor Shih gli_set_9767(host);
1108f3a5b56cSVictor Shih gl9767_hw_setting(slot);
1109f3a5b56cSVictor Shih gli_pcie_enable_msi(slot);
1110f3a5b56cSVictor Shih slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
11110e92aec2SVictor Shih host->mmc->caps2 |= MMC_CAP2_SD_EXP;
11120e92aec2SVictor Shih host->mmc_host_ops.init_sd_express = gl9767_init_sd_express;
1113f3a5b56cSVictor Shih sdhci_enable_v4_mode(host);
1114f3a5b56cSVictor Shih
1115f3a5b56cSVictor Shih return 0;
1116f3a5b56cSVictor Shih }
1117f3a5b56cSVictor Shih
sdhci_gli_voltage_switch(struct sdhci_host * host)1118e51df6ceSBen Chuang static void sdhci_gli_voltage_switch(struct sdhci_host *host)
1119e51df6ceSBen Chuang {
1120e51df6ceSBen Chuang /*
1121e51df6ceSBen Chuang * According to Section 3.6.1 signal voltage switch procedure in
1122e51df6ceSBen Chuang * SD Host Controller Simplified Spec. 4.20, steps 6~8 are as
1123e51df6ceSBen Chuang * follows:
1124e51df6ceSBen Chuang * (6) Set 1.8V Signal Enable in the Host Control 2 register.
1125e51df6ceSBen Chuang * (7) Wait 5ms. 1.8V voltage regulator shall be stable within this
1126e51df6ceSBen Chuang * period.
1127e51df6ceSBen Chuang * (8) If 1.8V Signal Enable is cleared by Host Controller, go to
1128e51df6ceSBen Chuang * step (12).
1129e51df6ceSBen Chuang *
1130e51df6ceSBen Chuang * Wait 5ms after set 1.8V signal enable in Host Control 2 register
1131e51df6ceSBen Chuang * to ensure 1.8V signal enable bit is set by GL9750/GL9755.
1132a1149a6cSDaniel Beer *
1133a1149a6cSDaniel Beer * ...however, the controller in the NUC10i3FNK4 (a 9755) requires
1134a1149a6cSDaniel Beer * slightly longer than 5ms before the control register reports that
1135a1149a6cSDaniel Beer * 1.8V is ready, and far longer still before the card will actually
1136a1149a6cSDaniel Beer * work reliably.
1137e51df6ceSBen Chuang */
1138a1149a6cSDaniel Beer usleep_range(100000, 110000);
1139e51df6ceSBen Chuang }
1140e51df6ceSBen Chuang
sdhci_gl9767_voltage_switch(struct sdhci_host * host)1141f3a5b56cSVictor Shih static void sdhci_gl9767_voltage_switch(struct sdhci_host *host)
1142f3a5b56cSVictor Shih {
1143f3a5b56cSVictor Shih /*
1144f3a5b56cSVictor Shih * According to Section 3.6.1 signal voltage switch procedure in
1145f3a5b56cSVictor Shih * SD Host Controller Simplified Spec. 4.20, steps 6~8 are as
1146f3a5b56cSVictor Shih * follows:
1147f3a5b56cSVictor Shih * (6) Set 1.8V Signal Enable in the Host Control 2 register.
1148f3a5b56cSVictor Shih * (7) Wait 5ms. 1.8V voltage regulator shall be stable within this
1149f3a5b56cSVictor Shih * period.
1150f3a5b56cSVictor Shih * (8) If 1.8V Signal Enable is cleared by Host Controller, go to
1151f3a5b56cSVictor Shih * step (12).
1152f3a5b56cSVictor Shih *
1153f3a5b56cSVictor Shih * Wait 5ms after set 1.8V signal enable in Host Control 2 register
1154f3a5b56cSVictor Shih * to ensure 1.8V signal enable bit is set by GL9767.
1155f3a5b56cSVictor Shih *
1156f3a5b56cSVictor Shih */
1157f3a5b56cSVictor Shih usleep_range(5000, 5500);
1158f3a5b56cSVictor Shih }
1159f3a5b56cSVictor Shih
sdhci_gl9750_reset(struct sdhci_host * host,u8 mask)1160e51df6ceSBen Chuang static void sdhci_gl9750_reset(struct sdhci_host *host, u8 mask)
1161e51df6ceSBen Chuang {
1162e51df6ceSBen Chuang sdhci_reset(host, mask);
1163e51df6ceSBen Chuang gli_set_9750(host);
1164e51df6ceSBen Chuang }
1165e51df6ceSBen Chuang
sdhci_gl9750_readl(struct sdhci_host * host,int reg)1166e51df6ceSBen Chuang static u32 sdhci_gl9750_readl(struct sdhci_host *host, int reg)
1167e51df6ceSBen Chuang {
1168e51df6ceSBen Chuang u32 value;
1169e51df6ceSBen Chuang
1170e51df6ceSBen Chuang value = readl(host->ioaddr + reg);
1171e51df6ceSBen Chuang if (unlikely(reg == SDHCI_MAX_CURRENT && !(value & 0xff)))
1172e51df6ceSBen Chuang value |= 0xc8;
1173e51df6ceSBen Chuang
1174e51df6ceSBen Chuang return value;
1175e51df6ceSBen Chuang }
1176e51df6ceSBen Chuang
gl9763e_hs400_enhanced_strobe(struct mmc_host * mmc,struct mmc_ios * ios)11771ae1d2d6SBen Chuang static void gl9763e_hs400_enhanced_strobe(struct mmc_host *mmc,
11781ae1d2d6SBen Chuang struct mmc_ios *ios)
11791ae1d2d6SBen Chuang {
11801ae1d2d6SBen Chuang struct sdhci_host *host = mmc_priv(mmc);
11811ae1d2d6SBen Chuang u32 val;
11821ae1d2d6SBen Chuang
11831ae1d2d6SBen Chuang val = sdhci_readl(host, SDHCI_GLI_9763E_HS400_ES_REG);
11841ae1d2d6SBen Chuang if (ios->enhanced_strobe)
11851ae1d2d6SBen Chuang val |= SDHCI_GLI_9763E_HS400_ES_BIT;
11861ae1d2d6SBen Chuang else
11871ae1d2d6SBen Chuang val &= ~SDHCI_GLI_9763E_HS400_ES_BIT;
11881ae1d2d6SBen Chuang
11891ae1d2d6SBen Chuang sdhci_writel(host, val, SDHCI_GLI_9763E_HS400_ES_REG);
11901ae1d2d6SBen Chuang }
11911ae1d2d6SBen Chuang
gl9763e_set_low_power_negotiation(struct sdhci_pci_slot * slot,bool enable)1192*a488e3e5SKornel Dulęba static void gl9763e_set_low_power_negotiation(struct sdhci_pci_slot *slot,
1193*a488e3e5SKornel Dulęba bool enable)
1194*a488e3e5SKornel Dulęba {
1195*a488e3e5SKornel Dulęba struct pci_dev *pdev = slot->chip->pdev;
1196*a488e3e5SKornel Dulęba u32 value;
1197*a488e3e5SKornel Dulęba
1198*a488e3e5SKornel Dulęba pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);
1199*a488e3e5SKornel Dulęba value &= ~GLI_9763E_VHS_REV;
1200*a488e3e5SKornel Dulęba value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_W);
1201*a488e3e5SKornel Dulęba pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);
1202*a488e3e5SKornel Dulęba
1203*a488e3e5SKornel Dulęba pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG, &value);
1204*a488e3e5SKornel Dulęba
1205*a488e3e5SKornel Dulęba if (enable)
1206*a488e3e5SKornel Dulęba value &= ~GLI_9763E_CFG_LPSN_DIS;
1207*a488e3e5SKornel Dulęba else
1208*a488e3e5SKornel Dulęba value |= GLI_9763E_CFG_LPSN_DIS;
1209*a488e3e5SKornel Dulęba
1210*a488e3e5SKornel Dulęba pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG, value);
1211*a488e3e5SKornel Dulęba
1212*a488e3e5SKornel Dulęba pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);
1213*a488e3e5SKornel Dulęba value &= ~GLI_9763E_VHS_REV;
1214*a488e3e5SKornel Dulęba value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R);
1215*a488e3e5SKornel Dulęba pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);
1216*a488e3e5SKornel Dulęba }
1217*a488e3e5SKornel Dulęba
sdhci_set_gl9763e_signaling(struct sdhci_host * host,unsigned int timing)12181ae1d2d6SBen Chuang static void sdhci_set_gl9763e_signaling(struct sdhci_host *host,
12191ae1d2d6SBen Chuang unsigned int timing)
12201ae1d2d6SBen Chuang {
12211ae1d2d6SBen Chuang u16 ctrl_2;
12221ae1d2d6SBen Chuang
12231ae1d2d6SBen Chuang ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
12241ae1d2d6SBen Chuang ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
12251ae1d2d6SBen Chuang if (timing == MMC_TIMING_MMC_HS200)
12261ae1d2d6SBen Chuang ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
12271ae1d2d6SBen Chuang else if (timing == MMC_TIMING_MMC_HS)
12281ae1d2d6SBen Chuang ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
12291ae1d2d6SBen Chuang else if (timing == MMC_TIMING_MMC_DDR52)
12301ae1d2d6SBen Chuang ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
12311ae1d2d6SBen Chuang else if (timing == MMC_TIMING_MMC_HS400)
12321ae1d2d6SBen Chuang ctrl_2 |= SDHCI_GLI_9763E_CTRL_HS400;
12331ae1d2d6SBen Chuang
12341ae1d2d6SBen Chuang sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
12351ae1d2d6SBen Chuang }
12361ae1d2d6SBen Chuang
sdhci_gl9763e_dumpregs(struct mmc_host * mmc)1237347f6be1SBen Chuang static void sdhci_gl9763e_dumpregs(struct mmc_host *mmc)
1238347f6be1SBen Chuang {
1239347f6be1SBen Chuang sdhci_dumpregs(mmc_priv(mmc));
1240347f6be1SBen Chuang }
1241347f6be1SBen Chuang
sdhci_gl9763e_cqe_pre_enable(struct mmc_host * mmc)1242347f6be1SBen Chuang static void sdhci_gl9763e_cqe_pre_enable(struct mmc_host *mmc)
1243347f6be1SBen Chuang {
1244347f6be1SBen Chuang struct cqhci_host *cq_host = mmc->cqe_private;
1245347f6be1SBen Chuang u32 value;
1246347f6be1SBen Chuang
1247347f6be1SBen Chuang value = cqhci_readl(cq_host, CQHCI_CFG);
1248347f6be1SBen Chuang value |= CQHCI_ENABLE;
1249347f6be1SBen Chuang cqhci_writel(cq_host, value, CQHCI_CFG);
1250347f6be1SBen Chuang }
1251347f6be1SBen Chuang
sdhci_gl9763e_cqe_enable(struct mmc_host * mmc)1252347f6be1SBen Chuang static void sdhci_gl9763e_cqe_enable(struct mmc_host *mmc)
1253347f6be1SBen Chuang {
1254347f6be1SBen Chuang struct sdhci_host *host = mmc_priv(mmc);
1255347f6be1SBen Chuang
1256347f6be1SBen Chuang sdhci_writew(host, GLI_9763E_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE);
1257347f6be1SBen Chuang sdhci_cqe_enable(mmc);
1258347f6be1SBen Chuang }
1259347f6be1SBen Chuang
sdhci_gl9763e_cqhci_irq(struct sdhci_host * host,u32 intmask)1260347f6be1SBen Chuang static u32 sdhci_gl9763e_cqhci_irq(struct sdhci_host *host, u32 intmask)
1261347f6be1SBen Chuang {
1262347f6be1SBen Chuang int cmd_error = 0;
1263347f6be1SBen Chuang int data_error = 0;
1264347f6be1SBen Chuang
1265347f6be1SBen Chuang if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
1266347f6be1SBen Chuang return intmask;
1267347f6be1SBen Chuang
1268347f6be1SBen Chuang cqhci_irq(host->mmc, intmask, cmd_error, data_error);
1269347f6be1SBen Chuang
1270347f6be1SBen Chuang return 0;
1271347f6be1SBen Chuang }
1272347f6be1SBen Chuang
sdhci_gl9763e_cqe_post_disable(struct mmc_host * mmc)1273347f6be1SBen Chuang static void sdhci_gl9763e_cqe_post_disable(struct mmc_host *mmc)
1274347f6be1SBen Chuang {
1275347f6be1SBen Chuang struct sdhci_host *host = mmc_priv(mmc);
1276347f6be1SBen Chuang struct cqhci_host *cq_host = mmc->cqe_private;
1277347f6be1SBen Chuang u32 value;
1278347f6be1SBen Chuang
1279347f6be1SBen Chuang value = cqhci_readl(cq_host, CQHCI_CFG);
1280347f6be1SBen Chuang value &= ~CQHCI_ENABLE;
1281347f6be1SBen Chuang cqhci_writel(cq_host, value, CQHCI_CFG);
1282347f6be1SBen Chuang sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
1283347f6be1SBen Chuang }
1284347f6be1SBen Chuang
1285347f6be1SBen Chuang static const struct cqhci_host_ops sdhci_gl9763e_cqhci_ops = {
1286347f6be1SBen Chuang .enable = sdhci_gl9763e_cqe_enable,
1287347f6be1SBen Chuang .disable = sdhci_cqe_disable,
1288347f6be1SBen Chuang .dumpregs = sdhci_gl9763e_dumpregs,
1289347f6be1SBen Chuang .pre_enable = sdhci_gl9763e_cqe_pre_enable,
1290347f6be1SBen Chuang .post_disable = sdhci_gl9763e_cqe_post_disable,
1291347f6be1SBen Chuang };
1292347f6be1SBen Chuang
gl9763e_add_host(struct sdhci_pci_slot * slot)1293347f6be1SBen Chuang static int gl9763e_add_host(struct sdhci_pci_slot *slot)
1294347f6be1SBen Chuang {
1295347f6be1SBen Chuang struct device *dev = &slot->chip->pdev->dev;
1296347f6be1SBen Chuang struct sdhci_host *host = slot->host;
1297347f6be1SBen Chuang struct cqhci_host *cq_host;
1298347f6be1SBen Chuang bool dma64;
1299347f6be1SBen Chuang int ret;
1300347f6be1SBen Chuang
1301347f6be1SBen Chuang ret = sdhci_setup_host(host);
1302347f6be1SBen Chuang if (ret)
1303347f6be1SBen Chuang return ret;
1304347f6be1SBen Chuang
1305347f6be1SBen Chuang cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL);
1306347f6be1SBen Chuang if (!cq_host) {
1307347f6be1SBen Chuang ret = -ENOMEM;
1308347f6be1SBen Chuang goto cleanup;
1309347f6be1SBen Chuang }
1310347f6be1SBen Chuang
1311347f6be1SBen Chuang cq_host->mmio = host->ioaddr + SDHCI_GLI_9763E_CQE_BASE_ADDR;
1312347f6be1SBen Chuang cq_host->ops = &sdhci_gl9763e_cqhci_ops;
1313347f6be1SBen Chuang
1314347f6be1SBen Chuang dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
1315347f6be1SBen Chuang if (dma64)
1316347f6be1SBen Chuang cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
1317347f6be1SBen Chuang
1318347f6be1SBen Chuang ret = cqhci_init(cq_host, host->mmc, dma64);
1319347f6be1SBen Chuang if (ret)
1320347f6be1SBen Chuang goto cleanup;
1321347f6be1SBen Chuang
1322347f6be1SBen Chuang ret = __sdhci_add_host(host);
1323347f6be1SBen Chuang if (ret)
1324347f6be1SBen Chuang goto cleanup;
1325347f6be1SBen Chuang
1326*a488e3e5SKornel Dulęba /* Disable LPM negotiation to avoid entering L1 state. */
1327*a488e3e5SKornel Dulęba gl9763e_set_low_power_negotiation(slot, false);
1328*a488e3e5SKornel Dulęba
1329347f6be1SBen Chuang return 0;
1330347f6be1SBen Chuang
1331347f6be1SBen Chuang cleanup:
1332347f6be1SBen Chuang sdhci_cleanup_host(host);
1333347f6be1SBen Chuang return ret;
1334347f6be1SBen Chuang }
1335347f6be1SBen Chuang
gli_set_gl9763e(struct sdhci_pci_slot * slot)13361ae1d2d6SBen Chuang static void gli_set_gl9763e(struct sdhci_pci_slot *slot)
13371ae1d2d6SBen Chuang {
13381ae1d2d6SBen Chuang struct pci_dev *pdev = slot->chip->pdev;
13391ae1d2d6SBen Chuang u32 value;
13401ae1d2d6SBen Chuang
13411ae1d2d6SBen Chuang pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);
13421ae1d2d6SBen Chuang value &= ~GLI_9763E_VHS_REV;
13431ae1d2d6SBen Chuang value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_W);
13441ae1d2d6SBen Chuang pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);
13451ae1d2d6SBen Chuang
13461ae1d2d6SBen Chuang pci_read_config_dword(pdev, PCIE_GLI_9763E_SCR, &value);
13471ae1d2d6SBen Chuang value |= GLI_9763E_SCR_AXI_REQ;
13481ae1d2d6SBen Chuang pci_write_config_dword(pdev, PCIE_GLI_9763E_SCR, value);
13491ae1d2d6SBen Chuang
135098991b18SBen Chuang pci_read_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, &value);
135198991b18SBen Chuang value &= ~GLI_9763E_HS400_SLOW;
135298991b18SBen Chuang pci_write_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, value);
135398991b18SBen Chuang
1354edee82f7SRenius Chen pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG2, &value);
1355edee82f7SRenius Chen value &= ~GLI_9763E_CFG2_L1DLY;
135634dd3cccSBen Chuang /* set ASPM L1 entry delay to 21us */
1357baaaf55dSBen Chuang value |= FIELD_PREP(GLI_9763E_CFG2_L1DLY, GLI_9763E_CFG2_L1DLY_MID);
1358edee82f7SRenius Chen pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG2, value);
1359edee82f7SRenius Chen
1360c58c5950SRenius Chen pci_read_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, &value);
1361c58c5950SRenius Chen value &= ~GLI_9763E_HS400_RXDLY;
1362c58c5950SRenius Chen value |= FIELD_PREP(GLI_9763E_HS400_RXDLY, GLI_9763E_HS400_RXDLY_5);
1363c58c5950SRenius Chen pci_write_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, value);
1364c58c5950SRenius Chen
13651ae1d2d6SBen Chuang pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);
13661ae1d2d6SBen Chuang value &= ~GLI_9763E_VHS_REV;
13671ae1d2d6SBen Chuang value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R);
13681ae1d2d6SBen Chuang pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);
13691ae1d2d6SBen Chuang }
13701ae1d2d6SBen Chuang
1371d607667bSBen Chuang #ifdef CONFIG_PM
gl9763e_runtime_suspend(struct sdhci_pci_chip * chip)1372d607667bSBen Chuang static int gl9763e_runtime_suspend(struct sdhci_pci_chip *chip)
1373d607667bSBen Chuang {
1374d607667bSBen Chuang struct sdhci_pci_slot *slot = chip->slots[0];
1375d607667bSBen Chuang struct sdhci_host *host = slot->host;
1376d607667bSBen Chuang u16 clock;
1377d607667bSBen Chuang
1378f9e5b339SJason Lai /* Enable LPM negotiation to allow entering L1 state */
1379f9e5b339SJason Lai gl9763e_set_low_power_negotiation(slot, true);
1380f9e5b339SJason Lai
1381d607667bSBen Chuang clock = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1382d607667bSBen Chuang clock &= ~(SDHCI_CLOCK_PLL_EN | SDHCI_CLOCK_CARD_EN);
1383d607667bSBen Chuang sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL);
1384d607667bSBen Chuang
1385d607667bSBen Chuang return 0;
1386d607667bSBen Chuang }
1387d607667bSBen Chuang
gl9763e_runtime_resume(struct sdhci_pci_chip * chip)1388d607667bSBen Chuang static int gl9763e_runtime_resume(struct sdhci_pci_chip *chip)
1389d607667bSBen Chuang {
1390d607667bSBen Chuang struct sdhci_pci_slot *slot = chip->slots[0];
1391d607667bSBen Chuang struct sdhci_host *host = slot->host;
1392d607667bSBen Chuang u16 clock;
1393d607667bSBen Chuang
1394291e7d52SBen Chuang if (host->mmc->ios.power_mode != MMC_POWER_ON)
1395291e7d52SBen Chuang return 0;
1396291e7d52SBen Chuang
1397d607667bSBen Chuang clock = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1398d607667bSBen Chuang
1399d607667bSBen Chuang clock |= SDHCI_CLOCK_PLL_EN;
1400d607667bSBen Chuang clock &= ~SDHCI_CLOCK_INT_STABLE;
1401d607667bSBen Chuang sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL);
1402d607667bSBen Chuang
1403d607667bSBen Chuang /* Wait max 150 ms */
1404d607667bSBen Chuang if (read_poll_timeout(sdhci_readw, clock, (clock & SDHCI_CLOCK_INT_STABLE),
1405d607667bSBen Chuang 1000, 150000, false, host, SDHCI_CLOCK_CONTROL)) {
1406d607667bSBen Chuang pr_err("%s: PLL clock never stabilised.\n",
1407d607667bSBen Chuang mmc_hostname(host->mmc));
1408d607667bSBen Chuang sdhci_dumpregs(host);
1409d607667bSBen Chuang }
1410d607667bSBen Chuang
1411d607667bSBen Chuang clock |= SDHCI_CLOCK_CARD_EN;
1412d607667bSBen Chuang sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL);
1413d607667bSBen Chuang
1414f9e5b339SJason Lai /* Disable LPM negotiation to avoid entering L1 state. */
1415f9e5b339SJason Lai gl9763e_set_low_power_negotiation(slot, false);
1416f9e5b339SJason Lai
1417d607667bSBen Chuang return 0;
1418d607667bSBen Chuang }
1419d607667bSBen Chuang #endif
1420d607667bSBen Chuang
14211202d617SSven van Ashbrook #ifdef CONFIG_PM_SLEEP
sdhci_pci_gli_resume(struct sdhci_pci_chip * chip)14221202d617SSven van Ashbrook static int sdhci_pci_gli_resume(struct sdhci_pci_chip *chip)
14231202d617SSven van Ashbrook {
14241202d617SSven van Ashbrook struct sdhci_pci_slot *slot = chip->slots[0];
14251202d617SSven van Ashbrook
14261202d617SSven van Ashbrook pci_free_irq_vectors(slot->chip->pdev);
14271202d617SSven van Ashbrook gli_pcie_enable_msi(slot);
14281202d617SSven van Ashbrook
14291202d617SSven van Ashbrook return sdhci_pci_resume_host(chip);
14301202d617SSven van Ashbrook }
14311202d617SSven van Ashbrook
gl9763e_resume(struct sdhci_pci_chip * chip)14321202d617SSven van Ashbrook static int gl9763e_resume(struct sdhci_pci_chip *chip)
14331202d617SSven van Ashbrook {
14341202d617SSven van Ashbrook struct sdhci_pci_slot *slot = chip->slots[0];
14351202d617SSven van Ashbrook int ret;
14361202d617SSven van Ashbrook
14371202d617SSven van Ashbrook ret = sdhci_pci_gli_resume(chip);
14381202d617SSven van Ashbrook if (ret)
14391202d617SSven van Ashbrook return ret;
14401202d617SSven van Ashbrook
14411202d617SSven van Ashbrook ret = cqhci_resume(slot->host->mmc);
14421202d617SSven van Ashbrook if (ret)
14431202d617SSven van Ashbrook return ret;
14441202d617SSven van Ashbrook
14451202d617SSven van Ashbrook /*
14461202d617SSven van Ashbrook * Disable LPM negotiation to bring device back in sync
14471202d617SSven van Ashbrook * with its runtime_pm state.
14481202d617SSven van Ashbrook */
14491202d617SSven van Ashbrook gl9763e_set_low_power_negotiation(slot, false);
14501202d617SSven van Ashbrook
14511202d617SSven van Ashbrook return 0;
14521202d617SSven van Ashbrook }
14531202d617SSven van Ashbrook
gl9763e_suspend(struct sdhci_pci_chip * chip)14541202d617SSven van Ashbrook static int gl9763e_suspend(struct sdhci_pci_chip *chip)
14551202d617SSven van Ashbrook {
14561202d617SSven van Ashbrook struct sdhci_pci_slot *slot = chip->slots[0];
14571202d617SSven van Ashbrook int ret;
14581202d617SSven van Ashbrook
14591202d617SSven van Ashbrook /*
14601202d617SSven van Ashbrook * Certain SoCs can suspend only with the bus in low-
14611202d617SSven van Ashbrook * power state, notably x86 SoCs when using S0ix.
14621202d617SSven van Ashbrook * Re-enable LPM negotiation to allow entering L1 state
14631202d617SSven van Ashbrook * and entering system suspend.
14641202d617SSven van Ashbrook */
14651202d617SSven van Ashbrook gl9763e_set_low_power_negotiation(slot, true);
14661202d617SSven van Ashbrook
14671202d617SSven van Ashbrook ret = cqhci_suspend(slot->host->mmc);
14681202d617SSven van Ashbrook if (ret)
14691202d617SSven van Ashbrook goto err_suspend;
14701202d617SSven van Ashbrook
14711202d617SSven van Ashbrook ret = sdhci_suspend_host(slot->host);
14721202d617SSven van Ashbrook if (ret)
14731202d617SSven van Ashbrook goto err_suspend_host;
14741202d617SSven van Ashbrook
14751202d617SSven van Ashbrook return 0;
14761202d617SSven van Ashbrook
14771202d617SSven van Ashbrook err_suspend_host:
14781202d617SSven van Ashbrook cqhci_resume(slot->host->mmc);
14791202d617SSven van Ashbrook err_suspend:
14801202d617SSven van Ashbrook gl9763e_set_low_power_negotiation(slot, false);
14811202d617SSven van Ashbrook return ret;
14821202d617SSven van Ashbrook }
14831202d617SSven van Ashbrook #endif
14841202d617SSven van Ashbrook
gli_probe_slot_gl9763e(struct sdhci_pci_slot * slot)14851ae1d2d6SBen Chuang static int gli_probe_slot_gl9763e(struct sdhci_pci_slot *slot)
14861ae1d2d6SBen Chuang {
1487347f6be1SBen Chuang struct pci_dev *pdev = slot->chip->pdev;
14881ae1d2d6SBen Chuang struct sdhci_host *host = slot->host;
1489347f6be1SBen Chuang u32 value;
14901ae1d2d6SBen Chuang
14911ae1d2d6SBen Chuang host->mmc->caps |= MMC_CAP_8_BIT_DATA |
14921ae1d2d6SBen Chuang MMC_CAP_1_8V_DDR |
14931ae1d2d6SBen Chuang MMC_CAP_NONREMOVABLE;
14941ae1d2d6SBen Chuang host->mmc->caps2 |= MMC_CAP2_HS200_1_8V_SDR |
14951ae1d2d6SBen Chuang MMC_CAP2_HS400_1_8V |
14961ae1d2d6SBen Chuang MMC_CAP2_HS400_ES |
14971ae1d2d6SBen Chuang MMC_CAP2_NO_SDIO |
14981ae1d2d6SBen Chuang MMC_CAP2_NO_SD;
1499347f6be1SBen Chuang
1500347f6be1SBen Chuang pci_read_config_dword(pdev, PCIE_GLI_9763E_MB, &value);
1501347f6be1SBen Chuang if (!(value & GLI_9763E_MB_CMDQ_OFF))
150215f908faSRenius Chen if (value & GLI_9763E_MB_ERP_ON)
1503347f6be1SBen Chuang host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
1504347f6be1SBen Chuang
15051ae1d2d6SBen Chuang gli_pcie_enable_msi(slot);
15061ae1d2d6SBen Chuang host->mmc_host_ops.hs400_enhanced_strobe =
15071ae1d2d6SBen Chuang gl9763e_hs400_enhanced_strobe;
15081ae1d2d6SBen Chuang gli_set_gl9763e(slot);
15091ae1d2d6SBen Chuang sdhci_enable_v4_mode(host);
15101ae1d2d6SBen Chuang
15111ae1d2d6SBen Chuang return 0;
15121ae1d2d6SBen Chuang }
15131ae1d2d6SBen Chuang
1514c064bb5cSHector Martin #define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18)
1515c064bb5cSHector Martin
sdhci_gli_readw(struct sdhci_host * host,int reg)1516c064bb5cSHector Martin static u16 sdhci_gli_readw(struct sdhci_host *host, int reg)
1517c064bb5cSHector Martin {
1518c064bb5cSHector Martin u32 val = readl(host->ioaddr + (reg & ~3));
1519c064bb5cSHector Martin u16 word;
1520c064bb5cSHector Martin
1521c064bb5cSHector Martin word = (val >> REG_OFFSET_IN_BITS(reg)) & 0xffff;
1522c064bb5cSHector Martin return word;
1523c064bb5cSHector Martin }
1524c064bb5cSHector Martin
sdhci_gli_readb(struct sdhci_host * host,int reg)1525c064bb5cSHector Martin static u8 sdhci_gli_readb(struct sdhci_host *host, int reg)
1526c064bb5cSHector Martin {
1527c064bb5cSHector Martin u32 val = readl(host->ioaddr + (reg & ~3));
1528c064bb5cSHector Martin u8 byte = (val >> REG_OFFSET_IN_BITS(reg)) & 0xff;
1529c064bb5cSHector Martin
1530c064bb5cSHector Martin return byte;
1531c064bb5cSHector Martin }
1532c064bb5cSHector Martin
1533e51df6ceSBen Chuang static const struct sdhci_ops sdhci_gl9755_ops = {
1534c064bb5cSHector Martin .read_w = sdhci_gli_readw,
1535c064bb5cSHector Martin .read_b = sdhci_gli_readb,
1536786d33c8SBen Chuang .set_clock = sdhci_gl9755_set_clock,
1537e51df6ceSBen Chuang .enable_dma = sdhci_pci_enable_dma,
1538e51df6ceSBen Chuang .set_bus_width = sdhci_set_bus_width,
1539e51df6ceSBen Chuang .reset = sdhci_reset,
1540e51df6ceSBen Chuang .set_uhs_signaling = sdhci_set_uhs_signaling,
1541e51df6ceSBen Chuang .voltage_switch = sdhci_gli_voltage_switch,
1542e51df6ceSBen Chuang };
1543e51df6ceSBen Chuang
1544e51df6ceSBen Chuang const struct sdhci_pci_fixes sdhci_gl9755 = {
1545e51df6ceSBen Chuang .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
1546e51df6ceSBen Chuang .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50,
1547e51df6ceSBen Chuang .probe_slot = gli_probe_slot_gl9755,
1548e51df6ceSBen Chuang .ops = &sdhci_gl9755_ops,
1549282ede76SBen Chuang #ifdef CONFIG_PM_SLEEP
1550282ede76SBen Chuang .resume = sdhci_pci_gli_resume,
1551282ede76SBen Chuang #endif
1552e51df6ceSBen Chuang };
1553e51df6ceSBen Chuang
1554e51df6ceSBen Chuang static const struct sdhci_ops sdhci_gl9750_ops = {
1555c064bb5cSHector Martin .read_w = sdhci_gli_readw,
1556c064bb5cSHector Martin .read_b = sdhci_gli_readb,
1557e51df6ceSBen Chuang .read_l = sdhci_gl9750_readl,
1558786d33c8SBen Chuang .set_clock = sdhci_gl9750_set_clock,
1559e51df6ceSBen Chuang .enable_dma = sdhci_pci_enable_dma,
1560e51df6ceSBen Chuang .set_bus_width = sdhci_set_bus_width,
1561e51df6ceSBen Chuang .reset = sdhci_gl9750_reset,
1562e51df6ceSBen Chuang .set_uhs_signaling = sdhci_set_uhs_signaling,
1563e51df6ceSBen Chuang .voltage_switch = sdhci_gli_voltage_switch,
1564e51df6ceSBen Chuang .platform_execute_tuning = gl9750_execute_tuning,
1565e51df6ceSBen Chuang };
1566e51df6ceSBen Chuang
1567e51df6ceSBen Chuang const struct sdhci_pci_fixes sdhci_gl9750 = {
1568e51df6ceSBen Chuang .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
1569e51df6ceSBen Chuang .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50,
1570e51df6ceSBen Chuang .probe_slot = gli_probe_slot_gl9750,
1571e51df6ceSBen Chuang .ops = &sdhci_gl9750_ops,
1572282ede76SBen Chuang #ifdef CONFIG_PM_SLEEP
1573282ede76SBen Chuang .resume = sdhci_pci_gli_resume,
1574282ede76SBen Chuang #endif
1575e51df6ceSBen Chuang };
15761ae1d2d6SBen Chuang
15771ae1d2d6SBen Chuang static const struct sdhci_ops sdhci_gl9763e_ops = {
15781ae1d2d6SBen Chuang .set_clock = sdhci_set_clock,
15791ae1d2d6SBen Chuang .enable_dma = sdhci_pci_enable_dma,
15801ae1d2d6SBen Chuang .set_bus_width = sdhci_set_bus_width,
158108b863bbSBrian Norris .reset = sdhci_and_cqhci_reset,
15821ae1d2d6SBen Chuang .set_uhs_signaling = sdhci_set_gl9763e_signaling,
15831ae1d2d6SBen Chuang .voltage_switch = sdhci_gli_voltage_switch,
1584347f6be1SBen Chuang .irq = sdhci_gl9763e_cqhci_irq,
15851ae1d2d6SBen Chuang };
15861ae1d2d6SBen Chuang
15871ae1d2d6SBen Chuang const struct sdhci_pci_fixes sdhci_gl9763e = {
15881ae1d2d6SBen Chuang .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
15891ae1d2d6SBen Chuang .probe_slot = gli_probe_slot_gl9763e,
15901ae1d2d6SBen Chuang .ops = &sdhci_gl9763e_ops,
15911ae1d2d6SBen Chuang #ifdef CONFIG_PM_SLEEP
15921202d617SSven van Ashbrook .resume = gl9763e_resume,
15931202d617SSven van Ashbrook .suspend = gl9763e_suspend,
15941ae1d2d6SBen Chuang #endif
1595d607667bSBen Chuang #ifdef CONFIG_PM
1596d607667bSBen Chuang .runtime_suspend = gl9763e_runtime_suspend,
1597d607667bSBen Chuang .runtime_resume = gl9763e_runtime_resume,
1598d607667bSBen Chuang .allow_runtime_pm = true,
1599d607667bSBen Chuang #endif
1600347f6be1SBen Chuang .add_host = gl9763e_add_host,
16011ae1d2d6SBen Chuang };
1602f3a5b56cSVictor Shih
1603f3a5b56cSVictor Shih static const struct sdhci_ops sdhci_gl9767_ops = {
1604d2754355SVictor Shih .set_clock = sdhci_gl9767_set_clock,
1605f3a5b56cSVictor Shih .enable_dma = sdhci_pci_enable_dma,
1606f3a5b56cSVictor Shih .set_bus_width = sdhci_set_bus_width,
1607f3a5b56cSVictor Shih .reset = sdhci_gl9767_reset,
1608f3a5b56cSVictor Shih .set_uhs_signaling = sdhci_set_uhs_signaling,
1609f3a5b56cSVictor Shih .voltage_switch = sdhci_gl9767_voltage_switch,
1610f3a5b56cSVictor Shih };
1611f3a5b56cSVictor Shih
1612f3a5b56cSVictor Shih const struct sdhci_pci_fixes sdhci_gl9767 = {
1613f3a5b56cSVictor Shih .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
1614f3a5b56cSVictor Shih .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50,
1615f3a5b56cSVictor Shih .probe_slot = gli_probe_slot_gl9767,
1616f3a5b56cSVictor Shih .ops = &sdhci_gl9767_ops,
1617f3a5b56cSVictor Shih #ifdef CONFIG_PM_SLEEP
1618f3a5b56cSVictor Shih .resume = sdhci_pci_gli_resume,
1619f3a5b56cSVictor Shih #endif
1620f3a5b56cSVictor Shih };
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