|
Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2 |
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| #
a488e3e5 |
| 14-Nov-2023 |
Kornel Dulęba <korneld@chromium.org> |
mmc: sdhci-pci-gli: Disable LPM during initialization
commit d9ed644f58670865cf067351deb71010bd87a52f upstream.
To address IO performance commit f9e5b33934ce
("mmc: host: Improve I/O read/write per
mmc: sdhci-pci-gli: Disable LPM during initialization
commit d9ed644f58670865cf067351deb71010bd87a52f upstream.
To address IO performance commit f9e5b33934ce
("mmc: host: Improve I/O read/write performance for GL9763E")
limited LPM negotiation to runtime suspend state.
The problem is that it only flips the switch in the runtime PM
resume/suspend logic.
Disable LPM negotiation in gl9763e_add_host.
This helps in two ways:
1. It was found that the LPM switch stays in the same position after
warm reboot. Having it set in init helps with consistency.
2. Disabling LPM during the first runtime resume leaves us susceptible
to the performance issue in the time window between boot and the
first runtime suspend.
Fixes: f9e5b33934ce ("mmc: host: Improve I/O read/write performance for GL9763E")
Cc: stable@vger.kernel.org
Signed-off-by: Kornel Dulęba <korneld@chromium.org>
Reviewed-by: Sven van Ashbrook <svenva@chromium.org>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/20231114115516.1585361-1-korneld@chromium.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
show more ...
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Revision tags: v6.5.11, v6.6.1 |
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| #
ea672572 |
| 07-Nov-2023 |
Victor Shih <victor.shih@genesyslogic.com.tw> |
mmc: sdhci-pci-gli: GL9750: Mask the replay timer timeout of AER
commit 015c9cbcf0ad709079117d27c2094a46e0eadcdb upstream.
Due to a flaw in the hardware design, the GL9750 replay timer frequently
t
mmc: sdhci-pci-gli: GL9750: Mask the replay timer timeout of AER
commit 015c9cbcf0ad709079117d27c2094a46e0eadcdb upstream.
Due to a flaw in the hardware design, the GL9750 replay timer frequently
times out when ASPM is enabled. As a result, the warning messages will
often appear in the system log when the system accesses the GL9750
PCI config. Therefore, the replay timer timeout must be masked.
Fixes: d7133797e9e1 ("mmc: sdhci-pci-gli: A workaround to allow GL9750 to enter ASPM L1.2")
Signed-off-by: Victor Shih <victor.shih@genesyslogic.com.tw>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Acked-by: Kai-Heng Feng <kai.heng.geng@canonical.com>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20231107095741.8832-2-victorshihgli@gmail.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
show more ...
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|
Revision tags: v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3 |
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| #
cd93b795 |
| 12-Sep-2023 |
Victor Shih <victor.shih@genesyslogic.com.tw> |
mmc: sdhci-pci-gli: A workaround to allow GL9750 to enter ASPM L1.2
commit d7133797e9e1b72fd89237f68cb36d745599ed86 upstream.
When GL9750 enters ASPM L1 sub-states, it will stay at L1.1 and will no
mmc: sdhci-pci-gli: A workaround to allow GL9750 to enter ASPM L1.2
commit d7133797e9e1b72fd89237f68cb36d745599ed86 upstream.
When GL9750 enters ASPM L1 sub-states, it will stay at L1.1 and will not
enter L1.2. The workaround is to toggle PM state to allow GL9750 to enter
ASPM L1.2.
Signed-off-by: Victor Shih <victor.shih@genesyslogic.com.tw>
Link: https://lore.kernel.org/r/20230912091710.7797-1-victorshihgli@gmail.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
show more ...
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| #
fcf890ec |
| 07-Nov-2023 |
Victor Shih <victor.shih@genesyslogic.com.tw> |
mmc: sdhci-pci-gli: GL9755: Mask the replay timer timeout of AER
commit 85dd3af64965c1c0eb7373b340a1b1f7773586b0 upstream.
Due to a flaw in the hardware design, the GL9755 replay timer frequently
t
mmc: sdhci-pci-gli: GL9755: Mask the replay timer timeout of AER
commit 85dd3af64965c1c0eb7373b340a1b1f7773586b0 upstream.
Due to a flaw in the hardware design, the GL9755 replay timer frequently
times out when ASPM is enabled. As a result, the warning messages will
often appear in the system log when the system accesses the GL9755
PCI config. Therefore, the replay timer timeout must be masked.
Fixes: 36ed2fd32b2c ("mmc: sdhci-pci-gli: A workaround to allow GL9755 to enter ASPM L1.2")
Signed-off-by: Victor Shih <victor.shih@genesyslogic.com.tw>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Acked-by: Kai-Heng Feng <kai.heng.geng@canonical.com>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20231107095741.8832-3-victorshihgli@gmail.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
show more ...
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|
Revision tags: v6.5.2, v6.1.51, v6.5.1 |
|
| #
1202d617 |
| 31-Aug-2023 |
Sven van Ashbrook <svenva@chromium.org> |
mmc: sdhci-pci-gli: fix LPM negotiation so x86/S0ix SoCs can suspend
To improve the r/w performance of GL9763E, the current driver inhibits LPM
negotiation while the device is active.
This prevents
mmc: sdhci-pci-gli: fix LPM negotiation so x86/S0ix SoCs can suspend
To improve the r/w performance of GL9763E, the current driver inhibits LPM
negotiation while the device is active.
This prevents a large number of SoCs from suspending, notably x86 systems
which commonly use S0ix as the suspend mechanism - for example, Intel
Alder Lake and Raptor Lake processors.
Failure description:
1. Userspace initiates s2idle suspend (e.g. via writing to
/sys/power/state)
2. This switches the runtime_pm device state to active, which disables
LPM negotiation, then calls the "regular" suspend callback
3. With LPM negotiation disabled, the bus cannot enter low-power state
4. On a large number of SoCs, if the bus not in a low-power state, S0ix
cannot be entered, which in turn prevents the SoC from entering
suspend.
Fix by re-enabling LPM negotiation in the device's suspend callback.
Suggested-by: Stanislaw Kardach <skardach@google.com>
Fixes: f9e5b33934ce ("mmc: host: Improve I/O read/write performance for GL9763E")
Cc: stable@vger.kernel.org
Signed-off-by: Sven van Ashbrook <svenva@chromium.org>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/20230831160055.v3.1.I7ed1ca09797be2dd76ca914c57d88b32d24dac88@changeid
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
show more ...
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|
Revision tags: v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33 |
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| #
0e92aec2 |
| 09-Jun-2023 |
Victor Shih <victor.shih@genesyslogic.com.tw> |
mmc: sdhci-pci-gli: Add support SD Express card for GL9767
Add support SD Express card for GL9767. The workflow of the
SD Express card in GL9767 is as below.
1. GL9767 operates in SD mode and set MM
mmc: sdhci-pci-gli: Add support SD Express card for GL9767
Add support SD Express card for GL9767. The workflow of the
SD Express card in GL9767 is as below.
1. GL9767 operates in SD mode and set MMC_CAP2_SD_EXP flag.
2. If card is inserted, Host send CMD8 to ask the capabilities
of the card.
3. If the card has PCIe capability, then init_sd_express()
will be invoked.
4. If the card has been put in write protect state then the
SD features supported by SD mode but not supported by
PCIe mode, therefore GL9767 switch to SD mode.
5. If the card has not been put in write protect state then
GL9767 switch from SD mode to PCIe/NVMe mode and mmc driver
handover control to NVMe driver.
6. If card is removed, GL9767 will return to SD mode.
Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw>
Signed-off-by: Victor Shih <victor.shih@genesyslogic.com.tw>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/20230609071441.451464-5-victorshihgli@gmail.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
show more ...
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| #
d2754355 |
| 09-Jun-2023 |
Victor Shih <victor.shih@genesyslogic.com.tw> |
mmc: sdhci-pci-gli: Set SDR104's clock to 205MHz and enable SSC for GL9767
Set GL9767 SDR104's clock to 205MHz and enable SSC feature
depend on register 0x888 BIT(1).
Signed-off-by: Ben Chuang <ben
mmc: sdhci-pci-gli: Set SDR104's clock to 205MHz and enable SSC for GL9767
Set GL9767 SDR104's clock to 205MHz and enable SSC feature
depend on register 0x888 BIT(1).
Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw>
Signed-off-by: Victor Shih <victor.shih@genesyslogic.com.tw>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/20230609071441.451464-3-victorshihgli@gmail.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
show more ...
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| #
f3a5b56c |
| 09-Jun-2023 |
Victor Shih <victor.shih@genesyslogic.com.tw> |
mmc: sdhci-pci-gli: Add Genesys Logic GL9767 support
Add support for the GL9767 chipset. GL9767 supports
SD3 mode likes UHS-I SDR50, SDR104.
Enable MSI interrupt for GL9767. Some platform do not
sup
mmc: sdhci-pci-gli: Add Genesys Logic GL9767 support
Add support for the GL9767 chipset. GL9767 supports
SD3 mode likes UHS-I SDR50, SDR104.
Enable MSI interrupt for GL9767. Some platform do not
support PCI INTx and devices can not work without
interrupt.
Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw>
Signed-off-by: Victor Shih <victor.shih@genesyslogic.com.tw>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/20230609071441.451464-2-victorshihgli@gmail.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
show more ...
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|
Revision tags: v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79, v6.0.8, v5.15.78, v6.0.7, v5.15.77, v5.15.76, v6.0.6 |
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| #
08b863bb |
| 26-Oct-2022 |
Brian Norris <briannorris@chromium.org> |
mmc: sdhci-*: Convert drivers to new sdhci_and_cqhci_reset()
An earlier patch ("mmc: cqhci: Provide helper for resetting both SDHCI
and CQHCI") does these operations for us.
I keep these as a separ
mmc: sdhci-*: Convert drivers to new sdhci_and_cqhci_reset()
An earlier patch ("mmc: cqhci: Provide helper for resetting both SDHCI
and CQHCI") does these operations for us.
I keep these as a separate patch, since the earlier patch is a
prerequisite to some important bugfixes that need to be backported via
linux-stable.
Signed-off-by: Brian Norris <briannorris@chromium.org>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/20221026124150.v4.7.Ia91f031f5f770af7bd2ff3e28b398f277606d970@changeid
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
show more ...
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|
Revision tags: v6.0.5, v5.15.75, v6.0.4, v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71, v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64, v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58, v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49 |
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| #
1c5fd973 |
| 19-Jun-2022 |
Ren Zhijie <renzhijie2@huawei.com> |
mmc: sdhci-pci-gli: Fix build error unused-function
If CONFIG_PM is not set.
make ARCH=x86_64 CROSS_COMPILE=x86_64-linux-gnu-, will be failed, like this:
drivers/mmc/host/sdhci-pci-gli.c:834:13: e
mmc: sdhci-pci-gli: Fix build error unused-function
If CONFIG_PM is not set.
make ARCH=x86_64 CROSS_COMPILE=x86_64-linux-gnu-, will be failed, like this:
drivers/mmc/host/sdhci-pci-gli.c:834:13: error: ‘gl9763e_set_low_power_negotiation’ defined but not used [-Werror=unused-function]
static void gl9763e_set_low_power_negotiation(struct sdhci_pci_slot *slot, bool enable)
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
make[3]: *** [drivers/mmc/host/sdhci-pci-gli.o] Error 1
To fix building warning, wrap all related code with CONFIG_PM.
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Ren Zhijie <renzhijie2@huawei.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/20220619104712.125364-1-renzhijie2@huawei.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
show more ...
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|
Revision tags: v5.15.48, v5.15.47 |
|
| #
f9e5b339 |
| 13-Jun-2022 |
Jason Lai <jasonlai.genesyslogic@gmail.com> |
mmc: host: Improve I/O read/write performance for GL9763E
Due to flaws in hardware design, GL9763E takes long time to exit from L1
state. The I/O performance will suffer severe impact if it often en
mmc: host: Improve I/O read/write performance for GL9763E
Due to flaws in hardware design, GL9763E takes long time to exit from L1
state. The I/O performance will suffer severe impact if it often enter and
exit L1 state during I/O requests.
To improve I/O read/write performance and take battery life into account,
let's turn on GL9763E L1 negotiation before entering runtime suspend and
turn off GL9763E L1 negotiation while executing runtime resume. That is to
say, GL9763E will not enter L1 state when executing I/O requests and enter
L1 state when PCIe bus idle.
Signed-off-by: Renius Chen <reniuschengl@gmail.com>
Signed-off-by: Jason Lai <jason.lai@genesyslogic.com.tw>
Link: https://lore.kernel.org/r/20220613092907.2502-1-jason.lai@genesyslogic.com.tw
[Ulf: Improved the commit message a bit]
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
show more ...
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|
Revision tags: v5.15.46, v5.15.45, v5.15.44, v5.15.43, v5.15.42, v5.18 |
|
| #
291e7d52 |
| 20-May-2022 |
Ben Chuang <benchuanggli@gmail.com> |
mmc: sdhci-pci-gli: Fix GL9763E runtime PM when the system resumes from suspend
When the system resumes from suspend (S3 or S4), the power mode is
MMC_POWER_OFF. In this status, gl9763e_runtime_resu
mmc: sdhci-pci-gli: Fix GL9763E runtime PM when the system resumes from suspend
When the system resumes from suspend (S3 or S4), the power mode is
MMC_POWER_OFF. In this status, gl9763e_runtime_resume() should not enable
PLL. Add a condition to this function to enable PLL only when the power
mode is MMC_POWER_ON.
Fixes: d607667bb8fa (mmc: sdhci-pci-gli: Add runtime PM for GL9763E)
Signed-off-by: Ben Chuang <benchuanggli@gmail.com>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20220520114242.150235-1-benchuanggli@gmail.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
show more ...
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|
Revision tags: v5.15.41, v5.15.40, v5.15.39, v5.15.38, v5.15.37, v5.15.36, v5.15.35 |
|
| #
36ed2fd3 |
| 14-Apr-2022 |
Ben Chuang <ben.chuang@genesyslogic.com.tw> |
mmc: sdhci-pci-gli: A workaround to allow GL9755 to enter ASPM L1.2
When GL9755 enters ASPM L1 sub-states, it will stay at L1.1 and will not
enter L1.2. The workaround is to toggle PM state to allow
mmc: sdhci-pci-gli: A workaround to allow GL9755 to enter ASPM L1.2
When GL9755 enters ASPM L1 sub-states, it will stay at L1.1 and will not
enter L1.2. The workaround is to toggle PM state to allow GL9755 to enter
ASPM L1.2.
Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/20220414094945.457500-1-benchuanggli@gmail.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
show more ...
|
|
Revision tags: v5.15.34, v5.15.33, v5.15.32, v5.15.31, v5.17, v5.15.30, v5.15.29, v5.15.28, v5.15.27 |
|
| #
d607667b |
| 07-Mar-2022 |
Ben Chuang <ben.chuang@genesyslogic.com.tw> |
mmc: sdhci-pci-gli: Add runtime PM for GL9763E
Add runtime PM for GL9763E and disable PLL in runtime suspend. So power
gated of upstream port can be enabled. GL9763E has an auxiliary power
so it kee
mmc: sdhci-pci-gli: Add runtime PM for GL9763E
Add runtime PM for GL9763E and disable PLL in runtime suspend. So power
gated of upstream port can be enabled. GL9763E has an auxiliary power
so it keep states in runtime suspend. In runtime resume, PLL is enabled
and waits for it to stabilize.
Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw>
Tested-by: Kevin Chang <kevin.chang@lcfuturecenter.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/20220307090009.1386876-1-benchuanggli@gmail.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
show more ...
|
|
Revision tags: v5.15.26, v5.15.25, v5.15.24, v5.15.23, v5.15.22, v5.15.21, v5.15.20, v5.15.19, v5.15.18, v5.15.17, v5.4.173, v5.15.16 |
|
| #
08df1a50 |
| 19-Jan-2022 |
Ben Chuang <ben.chuang@genesyslogic.com.tw> |
mmc: sdhci-pci-gli: Add a switch to enable/disable SSC for GL9750 and GL9755
Add a vendor-specific bit at the bit26 of GL9750's register 878h and
GL9755's register 78h to decide whether to disable S
mmc: sdhci-pci-gli: Add a switch to enable/disable SSC for GL9750 and GL9755
Add a vendor-specific bit at the bit26 of GL9750's register 878h and
GL9755's register 78h to decide whether to disable SSC function. If
this bit is set, the SSC function will be disabled.
Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw>
Link: https://lore.kernel.org/r/20220119075406.36321-1-benchuanggli@gmail.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
show more ...
|
| #
d3c6bdb6 |
| 19-Jan-2022 |
Ben Chuang <ben.chuang@genesyslogic.com.tw> |
mmc: sdhci-pci-gli: Enable SSC at 50MHz and 100MHz for GL9750 and GL9755
Enable SSC function at 50MHz and 100MHz for GL9750 and GL9755.
Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw>
Li
mmc: sdhci-pci-gli: Enable SSC at 50MHz and 100MHz for GL9750 and GL9755
Enable SSC function at 50MHz and 100MHz for GL9750 and GL9755.
Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw>
Link: https://lore.kernel.org/r/20220119075339.36281-1-benchuanggli@gmail.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
show more ...
|
| #
d0ba932a |
| 19-Jan-2022 |
Ben Chuang <ben.chuang@genesyslogic.com.tw> |
mmc: sdhci-pci-gli: Reduce the SSC value at 205MHz for GL9750 and GL9755
The SSC value is 0xFFE7 at 205MHz and may be saturated. Reduce the SSC
value to 0x5A1D at 205MHz to reduce this situation for
mmc: sdhci-pci-gli: Reduce the SSC value at 205MHz for GL9750 and GL9755
The SSC value is 0xFFE7 at 205MHz and may be saturated. Reduce the SSC
value to 0x5A1D at 205MHz to reduce this situation for GL9750 and GL9755.
Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw>
Link: https://lore.kernel.org/r/20220119075306.36262-1-benchuanggli@gmail.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
show more ...
|
|
Revision tags: v5.15.15, v5.16, v5.15.10, v5.15.9 |
|
| #
c064bb5c |
| 15-Dec-2021 |
Hector Martin <marcan@marcan.st> |
mmc: sdhci-pci-gli: GL975[50]: Issue 8/16-bit MMIO reads as 32-bit reads.
For some reason, <32-bit reads do not work on Apple ARM64 platforms with
these chips (even though they do on other PCIe devi
mmc: sdhci-pci-gli: GL975[50]: Issue 8/16-bit MMIO reads as 32-bit reads.
For some reason, <32-bit reads do not work on Apple ARM64 platforms with
these chips (even though they do on other PCIe devices). Issue them as
32-bit reads instead. This is done unconditionally, as it shouldn't hurt
even if not necessary.
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Hector Martin <marcan@marcan.st>
Link: https://lore.kernel.org/r/20211215161045.38843-3-marcan@marcan.st
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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| #
189f1d9b |
| 15-Dec-2021 |
Hector Martin <marcan@marcan.st> |
mmc: sdhci-pci-gli: GL9755: Support for CD/WP inversion on OF platforms
This is required on some Apple ARM64 laptops using this controller.
As is typical on DT platforms, pull these quirks from the
mmc: sdhci-pci-gli: GL9755: Support for CD/WP inversion on OF platforms
This is required on some Apple ARM64 laptops using this controller.
As is typical on DT platforms, pull these quirks from the device tree
using the standard mmc bindings.
See Documentation/devicetree/bindings/mmc/mmc-controller.yaml
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Hector Martin <marcan@marcan.st>
Link: https://lore.kernel.org/r/20211215161045.38843-2-marcan@marcan.st
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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| #
89280513 |
| 15-Dec-2021 |
Hector Martin <marcan@marcan.st> |
mmc: sdhci-pci-gli: GL9755: Support for CD/WP inversion on OF platforms
[ Upstream commit 189f1d9bc3a5ea3e442e119e4a5deda63da8c462 ]
This is required on some Apple ARM64 laptops using this controll
mmc: sdhci-pci-gli: GL9755: Support for CD/WP inversion on OF platforms
[ Upstream commit 189f1d9bc3a5ea3e442e119e4a5deda63da8c462 ]
This is required on some Apple ARM64 laptops using this controller.
As is typical on DT platforms, pull these quirks from the device tree
using the standard mmc bindings.
See Documentation/devicetree/bindings/mmc/mmc-controller.yaml
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Hector Martin <marcan@marcan.st>
Link: https://lore.kernel.org/r/20211215161045.38843-2-marcan@marcan.st
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
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|
Revision tags: v5.15.8, v5.15.7, v5.15.6, v5.15.5, v5.15.4, v5.15.3, v5.15.2, v5.15.1, v5.15, v5.14.14, v5.14.13, v5.14.12, v5.14.11, v5.14.10, v5.14.9, v5.14.8, v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5, v5.14.4, v5.10.65, v5.14.3, v5.10.64, v5.14.2, v5.10.63, v5.14.1, v5.10.62, v5.14, v5.10.61, v5.10.60, v5.10.53, v5.10.52, v5.10.51, v5.10.50, v5.10.49, v5.13, v5.10.46, v5.10.43, v5.10.42, v5.10.41, v5.10.40, v5.10.39, v5.4.119, v5.10.36 |
|
| #
34dd3ccc |
| 11-May-2021 |
Ben Chuang <benchuanggli@gmail.com> |
mmc: sdhci-pci-gli: Fine tune GL9763E L1 entry delay
Fine tune the value to 21us in order to improve read/write performance.
Signed-off-by: Ben Chuang <benchuanggli@gmail.com>
Link: https://lore.ke
mmc: sdhci-pci-gli: Fine tune GL9763E L1 entry delay
Fine tune the value to 21us in order to improve read/write performance.
Signed-off-by: Ben Chuang <benchuanggli@gmail.com>
Link: https://lore.kernel.org/r/20210511061835.5559-1-benchuanggli@gmail.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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|
Revision tags: v5.10.35, v5.10.34, v5.4.116, v5.10.33, v5.12 |
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| #
a1149a6c |
| 24-Apr-2021 |
Daniel Beer <dlbeer@gmail.com> |
mmc: sdhci-pci-gli: increase 1.8V regulator wait
Inserting an SD-card on an Intel NUC10i3FNK4 (which contains a GL9755)
results in the message:
mmc0: 1.8V regulator output did not become stable
mmc: sdhci-pci-gli: increase 1.8V regulator wait
Inserting an SD-card on an Intel NUC10i3FNK4 (which contains a GL9755)
results in the message:
mmc0: 1.8V regulator output did not become stable
Following this message, some cards work (sometimes), but most cards fail
with EILSEQ. This behaviour is observed on Debian 10 running kernel
4.19.188, but also with 5.8.18 and 5.11.15.
The driver currently waits 5ms after switching on the 1.8V regulator for
it to become stable. Increasing this to 10ms gets rid of the warning
about stability, but most cards still fail. Increasing it to 20ms gets
some cards working (a 32GB Samsung micro SD works, a 128GB ADATA
doesn't). At 50ms, the ADATA works most of the time, and at 100ms both
cards work reliably.
Signed-off-by: Daniel Beer <dlbeer@gmail.com>
Acked-by: Ben Chuang <benchuanggli@gmail.com>
Fixes: e51df6ce668a ("mmc: host: sdhci-pci: Add Genesys Logic GL975x support")
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20210424081652.GA16047@nyquist.nev
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: v5.10.32, v5.10.31 |
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| #
9751bacc |
| 14-Apr-2021 |
Ben Chuang <benchuanggli@gmail.com> |
mmc: sdhci-pci-gli: Enlarge ASPM L1 entry delay of GL975x
GL975x enters ASPM L1 state after a short idle in default.
Enlarge the idle period to 7.9us for improving the R/W performance.
Signed-off-b
mmc: sdhci-pci-gli: Enlarge ASPM L1 entry delay of GL975x
GL975x enters ASPM L1 state after a short idle in default.
Enlarge the idle period to 7.9us for improving the R/W performance.
Signed-off-by: Ben Chuang <benchuanggli@gmail.com>
Link: https://lore.kernel.org/r/20210415032637.5219-1-benchuanggli@gmail.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: v5.10.30 |
|
| #
baaaf55d |
| 07-Apr-2021 |
Ben Chuang <ben.chuang@genesyslogic.com.tw> |
mmc: sdhci-pci-gli: Improve GL9763E L1 entry delay to increase battery life
For GL9763E, although there is the best performance at the maximum delay.
Change the value to 20us in order to have better
mmc: sdhci-pci-gli: Improve GL9763E L1 entry delay to increase battery life
For GL9763E, although there is the best performance at the maximum delay.
Change the value to 20us in order to have better power consumption.
This change may reduce the maximum performance by 10%.
Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw>
Link: https://lore.kernel.org/r/20210407093816.8863-1-benchuanggli@gmail.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: v5.10.27, v5.10.26, v5.10.25, v5.10.24, v5.10.23, v5.10.22, v5.10.21, v5.10.20, v5.10.19, v5.4.101 |
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| #
f46b54cc |
| 25-Feb-2021 |
Renius Chen <reniuschengl@gmail.com> |
mmc: sdhci-pci-gli: Enable short circuit protection mechanism of GL9755
Short circuit protection mechanism of GL9755 is disabled by HW default
setting. Enable short circuit protection to prevent GL9
mmc: sdhci-pci-gli: Enable short circuit protection mechanism of GL9755
Short circuit protection mechanism of GL9755 is disabled by HW default
setting. Enable short circuit protection to prevent GL9755 from being
damaged by short circuit or over current.
Signed-off-by: Renius Chen <reniuschengl@gmail.com>
Link: https://lore.kernel.org/r/20210225111307.62975-1-reniuschengl@gmail.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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