183d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */
2af62a557SLei Wen /*
3af62a557SLei Wen * Copyright 2011, Marvell Semiconductor Inc.
4af62a557SLei Wen * Lei Wen <leiwen@marvell.com>
5af62a557SLei Wen *
6af62a557SLei Wen * Back ported to the 8xx platform (from the 8260 platform) by
7af62a557SLei Wen * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
8af62a557SLei Wen */
9af62a557SLei Wen #ifndef __SDHCI_HW_H
10af62a557SLei Wen #define __SDHCI_HW_H
11af62a557SLei Wen
12af62a557SLei Wen #include <asm/io.h>
136cf1b17cSLei Wen #include <mmc.h>
140347960bSSimon Glass #include <asm/gpio.h>
156cf1b17cSLei Wen
16af62a557SLei Wen /*
17af62a557SLei Wen * Controller registers
18af62a557SLei Wen */
19af62a557SLei Wen
20af62a557SLei Wen #define SDHCI_DMA_ADDRESS 0x00
21af62a557SLei Wen
22af62a557SLei Wen #define SDHCI_BLOCK_SIZE 0x04
23af62a557SLei Wen #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
24af62a557SLei Wen
25af62a557SLei Wen #define SDHCI_BLOCK_COUNT 0x06
26af62a557SLei Wen
27af62a557SLei Wen #define SDHCI_ARGUMENT 0x08
28af62a557SLei Wen
29af62a557SLei Wen #define SDHCI_TRANSFER_MODE 0x0C
3091914581SJaehoon Chung #define SDHCI_TRNS_DMA BIT(0)
3191914581SJaehoon Chung #define SDHCI_TRNS_BLK_CNT_EN BIT(1)
3291914581SJaehoon Chung #define SDHCI_TRNS_ACMD12 BIT(2)
3391914581SJaehoon Chung #define SDHCI_TRNS_READ BIT(4)
3491914581SJaehoon Chung #define SDHCI_TRNS_MULTI BIT(5)
35af62a557SLei Wen
36af62a557SLei Wen #define SDHCI_COMMAND 0x0E
37af62a557SLei Wen #define SDHCI_CMD_RESP_MASK 0x03
38af62a557SLei Wen #define SDHCI_CMD_CRC 0x08
39af62a557SLei Wen #define SDHCI_CMD_INDEX 0x10
40af62a557SLei Wen #define SDHCI_CMD_DATA 0x20
41af62a557SLei Wen #define SDHCI_CMD_ABORTCMD 0xC0
42af62a557SLei Wen
43af62a557SLei Wen #define SDHCI_CMD_RESP_NONE 0x00
44af62a557SLei Wen #define SDHCI_CMD_RESP_LONG 0x01
45af62a557SLei Wen #define SDHCI_CMD_RESP_SHORT 0x02
46af62a557SLei Wen #define SDHCI_CMD_RESP_SHORT_BUSY 0x03
47af62a557SLei Wen
48af62a557SLei Wen #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
49af62a557SLei Wen #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
50af62a557SLei Wen
51af62a557SLei Wen #define SDHCI_RESPONSE 0x10
52af62a557SLei Wen
53af62a557SLei Wen #define SDHCI_BUFFER 0x20
54af62a557SLei Wen
55af62a557SLei Wen #define SDHCI_PRESENT_STATE 0x24
5691914581SJaehoon Chung #define SDHCI_CMD_INHIBIT BIT(0)
5791914581SJaehoon Chung #define SDHCI_DATA_INHIBIT BIT(1)
5891914581SJaehoon Chung #define SDHCI_DOING_WRITE BIT(8)
5991914581SJaehoon Chung #define SDHCI_DOING_READ BIT(9)
6091914581SJaehoon Chung #define SDHCI_SPACE_AVAILABLE BIT(10)
6191914581SJaehoon Chung #define SDHCI_DATA_AVAILABLE BIT(11)
6291914581SJaehoon Chung #define SDHCI_CARD_PRESENT BIT(16)
6391914581SJaehoon Chung #define SDHCI_CARD_STATE_STABLE BIT(17)
6491914581SJaehoon Chung #define SDHCI_CARD_DETECT_PIN_LEVEL BIT(18)
6591914581SJaehoon Chung #define SDHCI_WRITE_PROTECT BIT(19)
66af62a557SLei Wen
67af62a557SLei Wen #define SDHCI_HOST_CONTROL 0x28
6891914581SJaehoon Chung #define SDHCI_CTRL_LED BIT(0)
6991914581SJaehoon Chung #define SDHCI_CTRL_4BITBUS BIT(1)
7091914581SJaehoon Chung #define SDHCI_CTRL_HISPD BIT(2)
71af62a557SLei Wen #define SDHCI_CTRL_DMA_MASK 0x18
72af62a557SLei Wen #define SDHCI_CTRL_SDMA 0x00
73af62a557SLei Wen #define SDHCI_CTRL_ADMA1 0x08
74af62a557SLei Wen #define SDHCI_CTRL_ADMA32 0x10
75af62a557SLei Wen #define SDHCI_CTRL_ADMA64 0x18
7691914581SJaehoon Chung #define SDHCI_CTRL_8BITBUS BIT(5)
7791914581SJaehoon Chung #define SDHCI_CTRL_CD_TEST_INS BIT(6)
7891914581SJaehoon Chung #define SDHCI_CTRL_CD_TEST BIT(7)
79af62a557SLei Wen
80af62a557SLei Wen #define SDHCI_POWER_CONTROL 0x29
81af62a557SLei Wen #define SDHCI_POWER_ON 0x01
82af62a557SLei Wen #define SDHCI_POWER_180 0x0A
83af62a557SLei Wen #define SDHCI_POWER_300 0x0C
84af62a557SLei Wen #define SDHCI_POWER_330 0x0E
85af62a557SLei Wen
86af62a557SLei Wen #define SDHCI_BLOCK_GAP_CONTROL 0x2A
87af62a557SLei Wen
88af62a557SLei Wen #define SDHCI_WAKE_UP_CONTROL 0x2B
8991914581SJaehoon Chung #define SDHCI_WAKE_ON_INT BIT(0)
9091914581SJaehoon Chung #define SDHCI_WAKE_ON_INSERT BIT(1)
9191914581SJaehoon Chung #define SDHCI_WAKE_ON_REMOVE BIT(2)
92af62a557SLei Wen
93af62a557SLei Wen #define SDHCI_CLOCK_CONTROL 0x2C
94af62a557SLei Wen #define SDHCI_DIVIDER_SHIFT 8
95af62a557SLei Wen #define SDHCI_DIVIDER_HI_SHIFT 6
96af62a557SLei Wen #define SDHCI_DIV_MASK 0xFF
97af62a557SLei Wen #define SDHCI_DIV_MASK_LEN 8
98af62a557SLei Wen #define SDHCI_DIV_HI_MASK 0x300
9991914581SJaehoon Chung #define SDHCI_PROG_CLOCK_MODE BIT(5)
10091914581SJaehoon Chung #define SDHCI_CLOCK_CARD_EN BIT(2)
10191914581SJaehoon Chung #define SDHCI_CLOCK_INT_STABLE BIT(1)
10291914581SJaehoon Chung #define SDHCI_CLOCK_INT_EN BIT(0)
103af62a557SLei Wen
104af62a557SLei Wen #define SDHCI_TIMEOUT_CONTROL 0x2E
105af62a557SLei Wen
106af62a557SLei Wen #define SDHCI_SOFTWARE_RESET 0x2F
107af62a557SLei Wen #define SDHCI_RESET_ALL 0x01
108af62a557SLei Wen #define SDHCI_RESET_CMD 0x02
109af62a557SLei Wen #define SDHCI_RESET_DATA 0x04
110af62a557SLei Wen
111af62a557SLei Wen #define SDHCI_INT_STATUS 0x30
112af62a557SLei Wen #define SDHCI_INT_ENABLE 0x34
113af62a557SLei Wen #define SDHCI_SIGNAL_ENABLE 0x38
11491914581SJaehoon Chung #define SDHCI_INT_RESPONSE BIT(0)
11591914581SJaehoon Chung #define SDHCI_INT_DATA_END BIT(1)
11691914581SJaehoon Chung #define SDHCI_INT_DMA_END BIT(3)
11791914581SJaehoon Chung #define SDHCI_INT_SPACE_AVAIL BIT(4)
11891914581SJaehoon Chung #define SDHCI_INT_DATA_AVAIL BIT(5)
11991914581SJaehoon Chung #define SDHCI_INT_CARD_INSERT BIT(6)
12091914581SJaehoon Chung #define SDHCI_INT_CARD_REMOVE BIT(7)
12191914581SJaehoon Chung #define SDHCI_INT_CARD_INT BIT(8)
12291914581SJaehoon Chung #define SDHCI_INT_ERROR BIT(15)
12391914581SJaehoon Chung #define SDHCI_INT_TIMEOUT BIT(16)
12491914581SJaehoon Chung #define SDHCI_INT_CRC BIT(17)
12591914581SJaehoon Chung #define SDHCI_INT_END_BIT BIT(18)
12691914581SJaehoon Chung #define SDHCI_INT_INDEX BIT(19)
12791914581SJaehoon Chung #define SDHCI_INT_DATA_TIMEOUT BIT(20)
12891914581SJaehoon Chung #define SDHCI_INT_DATA_CRC BIT(21)
12991914581SJaehoon Chung #define SDHCI_INT_DATA_END_BIT BIT(22)
13091914581SJaehoon Chung #define SDHCI_INT_BUS_POWER BIT(23)
13191914581SJaehoon Chung #define SDHCI_INT_ACMD12ERR BIT(24)
13291914581SJaehoon Chung #define SDHCI_INT_ADMA_ERROR BIT(25)
133af62a557SLei Wen
134af62a557SLei Wen #define SDHCI_INT_NORMAL_MASK 0x00007FFF
135af62a557SLei Wen #define SDHCI_INT_ERROR_MASK 0xFFFF8000
136af62a557SLei Wen
137af62a557SLei Wen #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
138af62a557SLei Wen SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
139af62a557SLei Wen #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
140af62a557SLei Wen SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
141af62a557SLei Wen SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
142af62a557SLei Wen SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR)
143af62a557SLei Wen #define SDHCI_INT_ALL_MASK ((unsigned int)-1)
144af62a557SLei Wen
145af62a557SLei Wen #define SDHCI_ACMD12_ERR 0x3C
146af62a557SLei Wen
147*730fd353SChin-Ting Kuo #define SDHCI_HOST_CONTROL_2 0x3E
148*730fd353SChin-Ting Kuo #define SDHCI_DRIVER_STRENGTH_MASK 0x30
149*730fd353SChin-Ting Kuo #define SDHCI_DRIVER_STRENGTH_SHIFT 4
150*730fd353SChin-Ting Kuo
151*730fd353SChin-Ting Kuo /* 3F reserved */
152af62a557SLei Wen
153af62a557SLei Wen #define SDHCI_CAPABILITIES 0x40
154af62a557SLei Wen #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
155af62a557SLei Wen #define SDHCI_TIMEOUT_CLK_SHIFT 0
156af62a557SLei Wen #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
157af62a557SLei Wen #define SDHCI_CLOCK_BASE_MASK 0x00003F00
158af62a557SLei Wen #define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00
159af62a557SLei Wen #define SDHCI_CLOCK_BASE_SHIFT 8
160af62a557SLei Wen #define SDHCI_MAX_BLOCK_MASK 0x00030000
161af62a557SLei Wen #define SDHCI_MAX_BLOCK_SHIFT 16
16291914581SJaehoon Chung #define SDHCI_CAN_DO_8BIT BIT(18)
16391914581SJaehoon Chung #define SDHCI_CAN_DO_ADMA2 BIT(19)
16491914581SJaehoon Chung #define SDHCI_CAN_DO_ADMA1 BIT(20)
16591914581SJaehoon Chung #define SDHCI_CAN_DO_HISPD BIT(21)
16691914581SJaehoon Chung #define SDHCI_CAN_DO_SDMA BIT(22)
16791914581SJaehoon Chung #define SDHCI_CAN_VDD_330 BIT(24)
16891914581SJaehoon Chung #define SDHCI_CAN_VDD_300 BIT(25)
16991914581SJaehoon Chung #define SDHCI_CAN_VDD_180 BIT(26)
17091914581SJaehoon Chung #define SDHCI_CAN_64BIT BIT(28)
171af62a557SLei Wen
172af62a557SLei Wen #define SDHCI_CAPABILITIES_1 0x44
173b8e25ef1SSiva Durga Prasad Paladugu #define SDHCI_SUPPORT_SDR50 0x00000001
174b8e25ef1SSiva Durga Prasad Paladugu #define SDHCI_SUPPORT_SDR104 0x00000002
175b8e25ef1SSiva Durga Prasad Paladugu #define SDHCI_SUPPORT_DDR50 0x00000004
176b8e25ef1SSiva Durga Prasad Paladugu #define SDHCI_USE_SDR50_TUNING 0x00002000
177b8e25ef1SSiva Durga Prasad Paladugu
178a0d0d86fSWenyou Yang #define SDHCI_CLOCK_MUL_MASK 0x00FF0000
179a0d0d86fSWenyou Yang #define SDHCI_CLOCK_MUL_SHIFT 16
180af62a557SLei Wen
181af62a557SLei Wen #define SDHCI_MAX_CURRENT 0x48
182af62a557SLei Wen
183af62a557SLei Wen /* 4C-4F reserved for more max current */
184af62a557SLei Wen
185af62a557SLei Wen #define SDHCI_SET_ACMD12_ERROR 0x50
186af62a557SLei Wen #define SDHCI_SET_INT_ERROR 0x52
187af62a557SLei Wen
188af62a557SLei Wen #define SDHCI_ADMA_ERROR 0x54
189af62a557SLei Wen
190af62a557SLei Wen /* 55-57 reserved */
191af62a557SLei Wen
192af62a557SLei Wen #define SDHCI_ADMA_ADDRESS 0x58
193af62a557SLei Wen
194af62a557SLei Wen /* 60-FB reserved */
195af62a557SLei Wen
196af62a557SLei Wen #define SDHCI_SLOT_INT_STATUS 0xFC
197af62a557SLei Wen
198af62a557SLei Wen #define SDHCI_HOST_VERSION 0xFE
199af62a557SLei Wen #define SDHCI_VENDOR_VER_MASK 0xFF00
200af62a557SLei Wen #define SDHCI_VENDOR_VER_SHIFT 8
201af62a557SLei Wen #define SDHCI_SPEC_VER_MASK 0x00FF
202af62a557SLei Wen #define SDHCI_SPEC_VER_SHIFT 0
203af62a557SLei Wen #define SDHCI_SPEC_100 0
204af62a557SLei Wen #define SDHCI_SPEC_200 1
205af62a557SLei Wen #define SDHCI_SPEC_300 2
206af62a557SLei Wen
207113e5dfcSJaehoon Chung #define SDHCI_GET_VERSION(x) (x->version & SDHCI_SPEC_VER_MASK)
208113e5dfcSJaehoon Chung
209af62a557SLei Wen /*
210af62a557SLei Wen * End of controller registers.
211af62a557SLei Wen */
212af62a557SLei Wen
213af62a557SLei Wen #define SDHCI_MAX_DIV_SPEC_200 256
214af62a557SLei Wen #define SDHCI_MAX_DIV_SPEC_300 2046
215af62a557SLei Wen
216af62a557SLei Wen /*
217af62a557SLei Wen * quirks
218af62a557SLei Wen */
219af62a557SLei Wen #define SDHCI_QUIRK_32BIT_DMA_ADDR (1 << 0)
2205af9a569SAjay Bhargav #define SDHCI_QUIRK_REG32_RW (1 << 1)
2213a638320SJaehoon Chung #define SDHCI_QUIRK_BROKEN_R1B (1 << 2)
222236bfecfSJaehoon Chung #define SDHCI_QUIRK_NO_HISPD_BIT (1 << 3)
223236bfecfSJaehoon Chung #define SDHCI_QUIRK_BROKEN_VOLTAGE (1 << 4)
22488a57125SHannes Schmelzer /*
22588a57125SHannes Schmelzer * SDHCI_QUIRK_BROKEN_HISPD_MODE
22688a57125SHannes Schmelzer * the hardware cannot operate correctly in high-speed mode,
22788a57125SHannes Schmelzer * this quirk forces the sdhci host-controller to non high-speed mode
22888a57125SHannes Schmelzer */
22988a57125SHannes Schmelzer #define SDHCI_QUIRK_BROKEN_HISPD_MODE BIT(5)
23013243f2eSTushar Behera #define SDHCI_QUIRK_WAIT_SEND_CMD (1 << 6)
231113e5dfcSJaehoon Chung #define SDHCI_QUIRK_USE_WIDE8 (1 << 8)
232b8e25ef1SSiva Durga Prasad Paladugu #define SDHCI_QUIRK_NO_1_8_V (1 << 9)
233af62a557SLei Wen
2340d2f15f9SLei Wen /* to make gcc happy */
2350d2f15f9SLei Wen struct sdhci_host;
2360d2f15f9SLei Wen
237af62a557SLei Wen /*
238af62a557SLei Wen * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
239af62a557SLei Wen */
240af62a557SLei Wen #define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024)
241af62a557SLei Wen #define SDHCI_DEFAULT_BOUNDARY_ARG (7)
242af62a557SLei Wen struct sdhci_ops {
243af62a557SLei Wen #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
244af62a557SLei Wen u32 (*read_l)(struct sdhci_host *host, int reg);
245af62a557SLei Wen u16 (*read_w)(struct sdhci_host *host, int reg);
246af62a557SLei Wen u8 (*read_b)(struct sdhci_host *host, int reg);
247af62a557SLei Wen void (*write_l)(struct sdhci_host *host, u32 val, int reg);
248af62a557SLei Wen void (*write_w)(struct sdhci_host *host, u16 val, int reg);
249af62a557SLei Wen void (*write_b)(struct sdhci_host *host, u8 val, int reg);
250af62a557SLei Wen #endif
251309bf02cSJaehoon Chung int (*get_cd)(struct sdhci_host *host);
25262226b68SJaehoon Chung void (*set_control_reg)(struct sdhci_host *host);
253210841c6SStefan Roese void (*set_ios_post)(struct sdhci_host *host);
25462226b68SJaehoon Chung void (*set_clock)(struct sdhci_host *host, u32 div);
2552fc3ed5dSSiva Durga Prasad Paladugu int (*platform_execute_tuning)(struct mmc *host, u8 opcode);
2562fc3ed5dSSiva Durga Prasad Paladugu void (*set_delay)(struct sdhci_host *host);
257af62a557SLei Wen };
258af62a557SLei Wen
259af62a557SLei Wen struct sdhci_host {
260cacd1d2fSMasahiro Yamada const char *name;
261af62a557SLei Wen void *ioaddr;
262af62a557SLei Wen unsigned int quirks;
263236bfecfSJaehoon Chung unsigned int host_caps;
264af62a557SLei Wen unsigned int version;
2656d0e34bfSStefan Herbrechtsmeier unsigned int max_clk; /* Maximum Base Clock frequency */
2666dffdbc3SWenyou Yang unsigned int clk_mul; /* Clock Multiplier value */
267af62a557SLei Wen unsigned int clock;
2686cf1b17cSLei Wen struct mmc *mmc;
269af62a557SLei Wen const struct sdhci_ops *ops;
270b09ed6e4SJaehoon Chung int index;
271236bfecfSJaehoon Chung
2723577fe8bSPiotr Wilczek int bus_width;
2730347960bSSimon Glass struct gpio_desc pwr_gpio; /* Power GPIO */
27459490e5dSryan_chen struct gpio_desc pwr_sw_gpio; /* Power switch GPIO */
2750347960bSSimon Glass struct gpio_desc cd_gpio; /* Card Detect GPIO */
2763577fe8bSPiotr Wilczek
277236bfecfSJaehoon Chung uint voltages;
27893bfd616SPantelis Antoniou
27993bfd616SPantelis Antoniou struct mmc_config cfg;
280af62a557SLei Wen };
281af62a557SLei Wen
282af62a557SLei Wen #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
283af62a557SLei Wen
sdhci_writel(struct sdhci_host * host,u32 val,int reg)284af62a557SLei Wen static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
285af62a557SLei Wen {
286af62a557SLei Wen if (unlikely(host->ops->write_l))
287af62a557SLei Wen host->ops->write_l(host, val, reg);
288af62a557SLei Wen else
289af62a557SLei Wen writel(val, host->ioaddr + reg);
290af62a557SLei Wen }
291af62a557SLei Wen
sdhci_writew(struct sdhci_host * host,u16 val,int reg)292af62a557SLei Wen static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
293af62a557SLei Wen {
294af62a557SLei Wen if (unlikely(host->ops->write_w))
295af62a557SLei Wen host->ops->write_w(host, val, reg);
296af62a557SLei Wen else
297af62a557SLei Wen writew(val, host->ioaddr + reg);
298af62a557SLei Wen }
299af62a557SLei Wen
sdhci_writeb(struct sdhci_host * host,u8 val,int reg)300af62a557SLei Wen static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
301af62a557SLei Wen {
302af62a557SLei Wen if (unlikely(host->ops->write_b))
303af62a557SLei Wen host->ops->write_b(host, val, reg);
304af62a557SLei Wen else
305af62a557SLei Wen writeb(val, host->ioaddr + reg);
306af62a557SLei Wen }
307af62a557SLei Wen
sdhci_readl(struct sdhci_host * host,int reg)308af62a557SLei Wen static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
309af62a557SLei Wen {
310af62a557SLei Wen if (unlikely(host->ops->read_l))
311af62a557SLei Wen return host->ops->read_l(host, reg);
312af62a557SLei Wen else
313af62a557SLei Wen return readl(host->ioaddr + reg);
314af62a557SLei Wen }
315af62a557SLei Wen
sdhci_readw(struct sdhci_host * host,int reg)316af62a557SLei Wen static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
317af62a557SLei Wen {
318af62a557SLei Wen if (unlikely(host->ops->read_w))
319af62a557SLei Wen return host->ops->read_w(host, reg);
320af62a557SLei Wen else
321af62a557SLei Wen return readw(host->ioaddr + reg);
322af62a557SLei Wen }
323af62a557SLei Wen
sdhci_readb(struct sdhci_host * host,int reg)324af62a557SLei Wen static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
325af62a557SLei Wen {
326af62a557SLei Wen if (unlikely(host->ops->read_b))
327af62a557SLei Wen return host->ops->read_b(host, reg);
328af62a557SLei Wen else
329af62a557SLei Wen return readb(host->ioaddr + reg);
330af62a557SLei Wen }
331af62a557SLei Wen
332af62a557SLei Wen #else
333af62a557SLei Wen
sdhci_writel(struct sdhci_host * host,u32 val,int reg)334af62a557SLei Wen static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
335af62a557SLei Wen {
336af62a557SLei Wen writel(val, host->ioaddr + reg);
337af62a557SLei Wen }
338af62a557SLei Wen
sdhci_writew(struct sdhci_host * host,u16 val,int reg)339af62a557SLei Wen static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
340af62a557SLei Wen {
341af62a557SLei Wen writew(val, host->ioaddr + reg);
342af62a557SLei Wen }
343af62a557SLei Wen
sdhci_writeb(struct sdhci_host * host,u8 val,int reg)344af62a557SLei Wen static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
345af62a557SLei Wen {
346af62a557SLei Wen writeb(val, host->ioaddr + reg);
347af62a557SLei Wen }
sdhci_readl(struct sdhci_host * host,int reg)348af62a557SLei Wen static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
349af62a557SLei Wen {
350af62a557SLei Wen return readl(host->ioaddr + reg);
351af62a557SLei Wen }
352af62a557SLei Wen
sdhci_readw(struct sdhci_host * host,int reg)353af62a557SLei Wen static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
354af62a557SLei Wen {
355af62a557SLei Wen return readw(host->ioaddr + reg);
356af62a557SLei Wen }
357af62a557SLei Wen
sdhci_readb(struct sdhci_host * host,int reg)358af62a557SLei Wen static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
359af62a557SLei Wen {
360af62a557SLei Wen return readb(host->ioaddr + reg);
361af62a557SLei Wen }
362af62a557SLei Wen #endif
363af62a557SLei Wen
364ef1e4edaSSimon Glass #ifdef CONFIG_BLK
365ef1e4edaSSimon Glass /**
366ef1e4edaSSimon Glass * sdhci_setup_cfg() - Set up the configuration for DWMMC
367ef1e4edaSSimon Glass *
368ef1e4edaSSimon Glass * This is used to set up an SDHCI device when you are using CONFIG_BLK.
369ef1e4edaSSimon Glass *
370ef1e4edaSSimon Glass * This should be called from your MMC driver's probe() method once you have
371ef1e4edaSSimon Glass * the information required.
372ef1e4edaSSimon Glass *
373ef1e4edaSSimon Glass * Generally your driver will have a platform data structure which holds both
374ef1e4edaSSimon Glass * the configuration (struct mmc_config) and the MMC device info (struct mmc).
375ef1e4edaSSimon Glass * For example:
376ef1e4edaSSimon Glass *
377ef1e4edaSSimon Glass * struct msm_sdhc_plat {
378ef1e4edaSSimon Glass * struct mmc_config cfg;
379ef1e4edaSSimon Glass * struct mmc mmc;
380ef1e4edaSSimon Glass * };
381ef1e4edaSSimon Glass *
382ef1e4edaSSimon Glass * ...
383ef1e4edaSSimon Glass *
384ef1e4edaSSimon Glass * Inside U_BOOT_DRIVER():
385ef1e4edaSSimon Glass * .platdata_auto_alloc_size = sizeof(struct msm_sdhc_plat),
386ef1e4edaSSimon Glass *
387ef1e4edaSSimon Glass * To access platform data:
388ef1e4edaSSimon Glass * struct msm_sdhc_plat *plat = dev_get_platdata(dev);
389ef1e4edaSSimon Glass *
390ef1e4edaSSimon Glass * See msm_sdhci.c for an example.
391ef1e4edaSSimon Glass *
392ef1e4edaSSimon Glass * @cfg: Configuration structure to fill in (generally &plat->mmc)
39314bed52dSJaehoon Chung * @host: SDHCI host structure
3946d0e34bfSStefan Herbrechtsmeier * @f_max: Maximum supported clock frequency in HZ (0 for default)
3956d0e34bfSStefan Herbrechtsmeier * @f_min: Minimum supported clock frequency in HZ (0 for default)
396ef1e4edaSSimon Glass */
39714bed52dSJaehoon Chung int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
3986d0e34bfSStefan Herbrechtsmeier u32 f_max, u32 f_min);
399ef1e4edaSSimon Glass
400ef1e4edaSSimon Glass /**
401ef1e4edaSSimon Glass * sdhci_bind() - Set up a new MMC block device
402ef1e4edaSSimon Glass *
403ef1e4edaSSimon Glass * This is used to set up an SDHCI block device when you are using CONFIG_BLK.
404ef1e4edaSSimon Glass * It should be called from your driver's bind() method.
405ef1e4edaSSimon Glass *
406ef1e4edaSSimon Glass * See msm_sdhci.c for an example.
407ef1e4edaSSimon Glass *
408ef1e4edaSSimon Glass * @dev: Device to set up
409ef1e4edaSSimon Glass * @mmc: Pointer to mmc structure (normally &plat->mmc)
410ef1e4edaSSimon Glass * @cfg: Empty configuration structure (generally &plat->cfg). This is
411ef1e4edaSSimon Glass * normally all zeroes at this point. The only purpose of passing
412ef1e4edaSSimon Glass * this in is to set mmc->cfg to it.
413ef1e4edaSSimon Glass * @return 0 if OK, -ve if the block device could not be created
414ef1e4edaSSimon Glass */
415ef1e4edaSSimon Glass int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
416ef1e4edaSSimon Glass #else
417ef1e4edaSSimon Glass
418ef1e4edaSSimon Glass /**
419ef1e4edaSSimon Glass * add_sdhci() - Add a new SDHCI interface
420ef1e4edaSSimon Glass *
421ef1e4edaSSimon Glass * This is used when you are not using CONFIG_BLK. Convert your driver over!
422ef1e4edaSSimon Glass *
423ef1e4edaSSimon Glass * @host: SDHCI host structure
4246d0e34bfSStefan Herbrechtsmeier * @f_max: Maximum supported clock frequency in HZ (0 for default)
4256d0e34bfSStefan Herbrechtsmeier * @f_min: Minimum supported clock frequency in HZ (0 for default)
426ef1e4edaSSimon Glass * @return 0 if OK, -ve on error
427ef1e4edaSSimon Glass */
4286d0e34bfSStefan Herbrechtsmeier int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min);
429ef1e4edaSSimon Glass #endif /* !CONFIG_BLK */
430ef1e4edaSSimon Glass
431e7881d85SSimon Glass #ifdef CONFIG_DM_MMC
432ef1e4edaSSimon Glass /* Export the operations to drivers */
433ef1e4edaSSimon Glass int sdhci_probe(struct udevice *dev);
434ef1e4edaSSimon Glass extern const struct dm_mmc_ops sdhci_ops;
435ef1e4edaSSimon Glass #else
436ef1e4edaSSimon Glass #endif
437ef1e4edaSSimon Glass
438af62a557SLei Wen #endif /* __SDHCI_HW_H */
439