1a5a944d2SAngelo Dureghello // SPDX-License-Identifier: GPL-2.0
2a5a944d2SAngelo Dureghello /*
3a5a944d2SAngelo Dureghello * Freescale eSDHC ColdFire family controller driver, platform bus.
4a5a944d2SAngelo Dureghello *
5a5a944d2SAngelo Dureghello * Copyright (c) 2020 Timesys Corporation
6a5a944d2SAngelo Dureghello * Author: Angelo Dureghello <angelo.dureghello@timesys.it>
7a5a944d2SAngelo Dureghello */
8a5a944d2SAngelo Dureghello
9a5a944d2SAngelo Dureghello #include <linux/module.h>
10a5a944d2SAngelo Dureghello #include <linux/delay.h>
11a5a944d2SAngelo Dureghello #include <linux/platform_data/mmc-esdhc-mcf.h>
12a5a944d2SAngelo Dureghello #include <linux/mmc/mmc.h>
13a5a944d2SAngelo Dureghello #include "sdhci-pltfm.h"
14a5a944d2SAngelo Dureghello #include "sdhci-esdhc.h"
15a5a944d2SAngelo Dureghello
16a5a944d2SAngelo Dureghello #define ESDHC_PROCTL_D3CD 0x08
17a5a944d2SAngelo Dureghello #define ESDHC_SYS_CTRL_DTOCV_MASK 0x0f
18a5a944d2SAngelo Dureghello #define ESDHC_DEFAULT_HOST_CONTROL 0x28
19a5a944d2SAngelo Dureghello
20a5a944d2SAngelo Dureghello /*
21a5a944d2SAngelo Dureghello * Freescale eSDHC has DMA ERR flag at bit 28, not as std spec says, bit 25.
22a5a944d2SAngelo Dureghello */
23a5a944d2SAngelo Dureghello #define ESDHC_INT_VENDOR_SPEC_DMA_ERR BIT(28)
24a5a944d2SAngelo Dureghello
25a5a944d2SAngelo Dureghello struct pltfm_mcf_data {
26a5a944d2SAngelo Dureghello struct clk *clk_ipg;
27a5a944d2SAngelo Dureghello struct clk *clk_ahb;
28a5a944d2SAngelo Dureghello struct clk *clk_per;
29a5a944d2SAngelo Dureghello int aside;
30a5a944d2SAngelo Dureghello int current_bus_width;
31a5a944d2SAngelo Dureghello };
32a5a944d2SAngelo Dureghello
esdhc_mcf_buffer_swap32(u32 * buf,int len)33a5a944d2SAngelo Dureghello static inline void esdhc_mcf_buffer_swap32(u32 *buf, int len)
34a5a944d2SAngelo Dureghello {
35a5a944d2SAngelo Dureghello int i;
36a5a944d2SAngelo Dureghello u32 temp;
37a5a944d2SAngelo Dureghello
38a5a944d2SAngelo Dureghello len = (len + 3) >> 2;
39a5a944d2SAngelo Dureghello
40a5a944d2SAngelo Dureghello for (i = 0; i < len; i++) {
41a5a944d2SAngelo Dureghello temp = swab32(*buf);
42a5a944d2SAngelo Dureghello *buf++ = temp;
43a5a944d2SAngelo Dureghello }
44a5a944d2SAngelo Dureghello }
45a5a944d2SAngelo Dureghello
esdhc_clrset_be(struct sdhci_host * host,u32 mask,u32 val,int reg)46a5a944d2SAngelo Dureghello static inline void esdhc_clrset_be(struct sdhci_host *host,
47a5a944d2SAngelo Dureghello u32 mask, u32 val, int reg)
48a5a944d2SAngelo Dureghello {
49a5a944d2SAngelo Dureghello void __iomem *base = host->ioaddr + (reg & ~3);
50a5a944d2SAngelo Dureghello u8 shift = (reg & 3) << 3;
51a5a944d2SAngelo Dureghello
52a5a944d2SAngelo Dureghello mask <<= shift;
53a5a944d2SAngelo Dureghello val <<= shift;
54a5a944d2SAngelo Dureghello
55a5a944d2SAngelo Dureghello if (reg == SDHCI_HOST_CONTROL)
56a5a944d2SAngelo Dureghello val |= ESDHC_PROCTL_D3CD;
57a5a944d2SAngelo Dureghello
58a5a944d2SAngelo Dureghello writel((readl(base) & ~mask) | val, base);
59a5a944d2SAngelo Dureghello }
60a5a944d2SAngelo Dureghello
61a5a944d2SAngelo Dureghello /*
62a5a944d2SAngelo Dureghello * Note: mcf is big-endian, single bytes need to be accessed at big endian
63a5a944d2SAngelo Dureghello * offsets.
64a5a944d2SAngelo Dureghello */
esdhc_mcf_writeb_be(struct sdhci_host * host,u8 val,int reg)65a5a944d2SAngelo Dureghello static void esdhc_mcf_writeb_be(struct sdhci_host *host, u8 val, int reg)
66a5a944d2SAngelo Dureghello {
67a5a944d2SAngelo Dureghello void __iomem *base = host->ioaddr + (reg & ~3);
68a5a944d2SAngelo Dureghello u8 shift = (reg & 3) << 3;
69a5a944d2SAngelo Dureghello u32 mask = ~(0xff << shift);
70a5a944d2SAngelo Dureghello
71a5a944d2SAngelo Dureghello if (reg == SDHCI_HOST_CONTROL) {
72a5a944d2SAngelo Dureghello u32 host_ctrl = ESDHC_DEFAULT_HOST_CONTROL;
73a5a944d2SAngelo Dureghello u8 dma_bits = (val & SDHCI_CTRL_DMA_MASK) >> 3;
74a5a944d2SAngelo Dureghello u8 tmp = readb(host->ioaddr + SDHCI_HOST_CONTROL + 1);
75a5a944d2SAngelo Dureghello
76a5a944d2SAngelo Dureghello tmp &= ~0x03;
77a5a944d2SAngelo Dureghello tmp |= dma_bits;
78a5a944d2SAngelo Dureghello
79a5a944d2SAngelo Dureghello /*
80a5a944d2SAngelo Dureghello * Recomposition needed, restore always endianness and
81a5a944d2SAngelo Dureghello * keep D3CD and AI, just setting bus width.
82a5a944d2SAngelo Dureghello */
83a5a944d2SAngelo Dureghello host_ctrl |= val;
84a5a944d2SAngelo Dureghello host_ctrl |= (dma_bits << 8);
85a5a944d2SAngelo Dureghello writel(host_ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
86a5a944d2SAngelo Dureghello
87a5a944d2SAngelo Dureghello return;
88a5a944d2SAngelo Dureghello }
89a5a944d2SAngelo Dureghello
90a5a944d2SAngelo Dureghello writel((readl(base) & mask) | (val << shift), base);
91a5a944d2SAngelo Dureghello }
92a5a944d2SAngelo Dureghello
esdhc_mcf_writew_be(struct sdhci_host * host,u16 val,int reg)93a5a944d2SAngelo Dureghello static void esdhc_mcf_writew_be(struct sdhci_host *host, u16 val, int reg)
94a5a944d2SAngelo Dureghello {
95a5a944d2SAngelo Dureghello struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
96a5a944d2SAngelo Dureghello struct pltfm_mcf_data *mcf_data = sdhci_pltfm_priv(pltfm_host);
97a5a944d2SAngelo Dureghello void __iomem *base = host->ioaddr + (reg & ~3);
98a5a944d2SAngelo Dureghello u8 shift = (reg & 3) << 3;
99a5a944d2SAngelo Dureghello u32 mask = ~(0xffff << shift);
100a5a944d2SAngelo Dureghello
101a5a944d2SAngelo Dureghello switch (reg) {
102a5a944d2SAngelo Dureghello case SDHCI_TRANSFER_MODE:
103a5a944d2SAngelo Dureghello mcf_data->aside = val;
104a5a944d2SAngelo Dureghello return;
105a5a944d2SAngelo Dureghello case SDHCI_COMMAND:
106a5a944d2SAngelo Dureghello if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
107a5a944d2SAngelo Dureghello val |= SDHCI_CMD_ABORTCMD;
108a5a944d2SAngelo Dureghello
109a5a944d2SAngelo Dureghello /*
110a5a944d2SAngelo Dureghello * As for the fsl driver,
111a5a944d2SAngelo Dureghello * we have to set the mode in a single write here.
112a5a944d2SAngelo Dureghello */
113a5a944d2SAngelo Dureghello writel(val << 16 | mcf_data->aside,
114a5a944d2SAngelo Dureghello host->ioaddr + SDHCI_TRANSFER_MODE);
115a5a944d2SAngelo Dureghello return;
116a5a944d2SAngelo Dureghello }
117a5a944d2SAngelo Dureghello
118a5a944d2SAngelo Dureghello writel((readl(base) & mask) | (val << shift), base);
119a5a944d2SAngelo Dureghello }
120a5a944d2SAngelo Dureghello
esdhc_mcf_writel_be(struct sdhci_host * host,u32 val,int reg)121a5a944d2SAngelo Dureghello static void esdhc_mcf_writel_be(struct sdhci_host *host, u32 val, int reg)
122a5a944d2SAngelo Dureghello {
123a5a944d2SAngelo Dureghello writel(val, host->ioaddr + reg);
124a5a944d2SAngelo Dureghello }
125a5a944d2SAngelo Dureghello
esdhc_mcf_readb_be(struct sdhci_host * host,int reg)126a5a944d2SAngelo Dureghello static u8 esdhc_mcf_readb_be(struct sdhci_host *host, int reg)
127a5a944d2SAngelo Dureghello {
128a5a944d2SAngelo Dureghello if (reg == SDHCI_HOST_CONTROL) {
129a5a944d2SAngelo Dureghello u8 __iomem *base = host->ioaddr + (reg & ~3);
130a5a944d2SAngelo Dureghello u16 val = readw(base + 2);
131a5a944d2SAngelo Dureghello u8 dma_bits = (val >> 5) & SDHCI_CTRL_DMA_MASK;
132a5a944d2SAngelo Dureghello u8 host_ctrl = val & 0xff;
133a5a944d2SAngelo Dureghello
134a5a944d2SAngelo Dureghello host_ctrl &= ~SDHCI_CTRL_DMA_MASK;
135a5a944d2SAngelo Dureghello host_ctrl |= dma_bits;
136a5a944d2SAngelo Dureghello
137a5a944d2SAngelo Dureghello return host_ctrl;
138a5a944d2SAngelo Dureghello }
139a5a944d2SAngelo Dureghello
140a5a944d2SAngelo Dureghello return readb(host->ioaddr + (reg ^ 0x3));
141a5a944d2SAngelo Dureghello }
142a5a944d2SAngelo Dureghello
esdhc_mcf_readw_be(struct sdhci_host * host,int reg)143a5a944d2SAngelo Dureghello static u16 esdhc_mcf_readw_be(struct sdhci_host *host, int reg)
144a5a944d2SAngelo Dureghello {
145a5a944d2SAngelo Dureghello /*
146a5a944d2SAngelo Dureghello * For SDHCI_HOST_VERSION, sdhci specs defines 0xFE,
147a5a944d2SAngelo Dureghello * a wrong offset for us, we are at 0xFC.
148a5a944d2SAngelo Dureghello */
149a5a944d2SAngelo Dureghello if (reg == SDHCI_HOST_VERSION)
150a5a944d2SAngelo Dureghello reg -= 2;
151a5a944d2SAngelo Dureghello
152a5a944d2SAngelo Dureghello return readw(host->ioaddr + (reg ^ 0x2));
153a5a944d2SAngelo Dureghello }
154a5a944d2SAngelo Dureghello
esdhc_mcf_readl_be(struct sdhci_host * host,int reg)155a5a944d2SAngelo Dureghello static u32 esdhc_mcf_readl_be(struct sdhci_host *host, int reg)
156a5a944d2SAngelo Dureghello {
157a5a944d2SAngelo Dureghello u32 val;
158a5a944d2SAngelo Dureghello
159a5a944d2SAngelo Dureghello val = readl(host->ioaddr + reg);
160a5a944d2SAngelo Dureghello
161a5a944d2SAngelo Dureghello /*
162a5a944d2SAngelo Dureghello * RM (25.3.9) sd pin clock must never exceed 25Mhz.
163a5a944d2SAngelo Dureghello * So forcing legacy mode at 25Mhz.
164a5a944d2SAngelo Dureghello */
165a5a944d2SAngelo Dureghello if (unlikely(reg == SDHCI_CAPABILITIES))
166a5a944d2SAngelo Dureghello val &= ~SDHCI_CAN_DO_HISPD;
167a5a944d2SAngelo Dureghello
168a5a944d2SAngelo Dureghello if (unlikely(reg == SDHCI_INT_STATUS)) {
169a5a944d2SAngelo Dureghello if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
170a5a944d2SAngelo Dureghello val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
171a5a944d2SAngelo Dureghello val |= SDHCI_INT_ADMA_ERROR;
172a5a944d2SAngelo Dureghello }
173a5a944d2SAngelo Dureghello }
174a5a944d2SAngelo Dureghello
175a5a944d2SAngelo Dureghello return val;
176a5a944d2SAngelo Dureghello }
177a5a944d2SAngelo Dureghello
esdhc_mcf_get_max_timeout_count(struct sdhci_host * host)178a5a944d2SAngelo Dureghello static unsigned int esdhc_mcf_get_max_timeout_count(struct sdhci_host *host)
179a5a944d2SAngelo Dureghello {
180a5a944d2SAngelo Dureghello return 1 << 27;
181a5a944d2SAngelo Dureghello }
182a5a944d2SAngelo Dureghello
esdhc_mcf_set_timeout(struct sdhci_host * host,struct mmc_command * cmd)183a5a944d2SAngelo Dureghello static void esdhc_mcf_set_timeout(struct sdhci_host *host,
184a5a944d2SAngelo Dureghello struct mmc_command *cmd)
185a5a944d2SAngelo Dureghello {
186a5a944d2SAngelo Dureghello /* Use maximum timeout counter */
187a5a944d2SAngelo Dureghello esdhc_clrset_be(host, ESDHC_SYS_CTRL_DTOCV_MASK, 0xE,
188a5a944d2SAngelo Dureghello SDHCI_TIMEOUT_CONTROL);
189a5a944d2SAngelo Dureghello }
190a5a944d2SAngelo Dureghello
esdhc_mcf_reset(struct sdhci_host * host,u8 mask)191a5a944d2SAngelo Dureghello static void esdhc_mcf_reset(struct sdhci_host *host, u8 mask)
192a5a944d2SAngelo Dureghello {
193a5a944d2SAngelo Dureghello struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
194a5a944d2SAngelo Dureghello struct pltfm_mcf_data *mcf_data = sdhci_pltfm_priv(pltfm_host);
195a5a944d2SAngelo Dureghello
196a5a944d2SAngelo Dureghello sdhci_reset(host, mask);
197a5a944d2SAngelo Dureghello
198a5a944d2SAngelo Dureghello esdhc_clrset_be(host, ESDHC_CTRL_BUSWIDTH_MASK,
199a5a944d2SAngelo Dureghello mcf_data->current_bus_width, SDHCI_HOST_CONTROL);
200a5a944d2SAngelo Dureghello
201a5a944d2SAngelo Dureghello sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
202a5a944d2SAngelo Dureghello sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
203a5a944d2SAngelo Dureghello }
204a5a944d2SAngelo Dureghello
esdhc_mcf_pltfm_get_max_clock(struct sdhci_host * host)205a5a944d2SAngelo Dureghello static unsigned int esdhc_mcf_pltfm_get_max_clock(struct sdhci_host *host)
206a5a944d2SAngelo Dureghello {
207a5a944d2SAngelo Dureghello struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
208a5a944d2SAngelo Dureghello
209a5a944d2SAngelo Dureghello return pltfm_host->clock;
210a5a944d2SAngelo Dureghello }
211a5a944d2SAngelo Dureghello
esdhc_mcf_pltfm_get_min_clock(struct sdhci_host * host)212a5a944d2SAngelo Dureghello static unsigned int esdhc_mcf_pltfm_get_min_clock(struct sdhci_host *host)
213a5a944d2SAngelo Dureghello {
214a5a944d2SAngelo Dureghello struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
215a5a944d2SAngelo Dureghello
216a5a944d2SAngelo Dureghello return pltfm_host->clock / 256 / 16;
217a5a944d2SAngelo Dureghello }
218a5a944d2SAngelo Dureghello
esdhc_mcf_pltfm_set_clock(struct sdhci_host * host,unsigned int clock)219a5a944d2SAngelo Dureghello static void esdhc_mcf_pltfm_set_clock(struct sdhci_host *host,
220a5a944d2SAngelo Dureghello unsigned int clock)
221a5a944d2SAngelo Dureghello {
222a5a944d2SAngelo Dureghello struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
223a5a944d2SAngelo Dureghello unsigned long *pll_dr = (unsigned long *)MCF_PLL_DR;
224a5a944d2SAngelo Dureghello u32 fvco, fsys, fesdhc, temp;
225a5a944d2SAngelo Dureghello const int sdclkfs[] = {2, 4, 8, 16, 32, 64, 128, 256};
226a5a944d2SAngelo Dureghello int delta, old_delta = clock;
227a5a944d2SAngelo Dureghello int i, q, ri, rq;
228a5a944d2SAngelo Dureghello
229a5a944d2SAngelo Dureghello if (clock == 0) {
230a5a944d2SAngelo Dureghello host->mmc->actual_clock = 0;
231a5a944d2SAngelo Dureghello return;
232a5a944d2SAngelo Dureghello }
233a5a944d2SAngelo Dureghello
234a5a944d2SAngelo Dureghello /*
235a5a944d2SAngelo Dureghello * ColdFire eSDHC clock.s
236a5a944d2SAngelo Dureghello *
237a5a944d2SAngelo Dureghello * pll -+-> / outdiv1 --> fsys
238a5a944d2SAngelo Dureghello * +-> / outdiv3 --> eSDHC clock ---> / SDCCLKFS / DVS
239a5a944d2SAngelo Dureghello *
240a5a944d2SAngelo Dureghello * mcf5441x datasheet says:
241a5a944d2SAngelo Dureghello * (8.1.2) eSDHC should be 40 MHz max
242a5a944d2SAngelo Dureghello * (25.3.9) eSDHC input is, as example, 96 Mhz ...
243a5a944d2SAngelo Dureghello * (25.3.9) sd pin clock must never exceed 25Mhz
244a5a944d2SAngelo Dureghello *
245a5a944d2SAngelo Dureghello * fvco = fsys * outdvi1 + 1
246a5a944d2SAngelo Dureghello * fshdc = fvco / outdiv3 + 1
247a5a944d2SAngelo Dureghello */
248a5a944d2SAngelo Dureghello temp = readl(pll_dr);
249a5a944d2SAngelo Dureghello fsys = pltfm_host->clock;
250a5a944d2SAngelo Dureghello fvco = fsys * ((temp & 0x1f) + 1);
251a5a944d2SAngelo Dureghello fesdhc = fvco / (((temp >> 10) & 0x1f) + 1);
252a5a944d2SAngelo Dureghello
253a5a944d2SAngelo Dureghello for (i = 0; i < 8; ++i) {
254a5a944d2SAngelo Dureghello int result = fesdhc / sdclkfs[i];
255a5a944d2SAngelo Dureghello
256a5a944d2SAngelo Dureghello for (q = 1; q < 17; ++q) {
257a5a944d2SAngelo Dureghello int finale = result / q;
258a5a944d2SAngelo Dureghello
259a5a944d2SAngelo Dureghello delta = abs(clock - finale);
260a5a944d2SAngelo Dureghello
261a5a944d2SAngelo Dureghello if (delta < old_delta) {
262a5a944d2SAngelo Dureghello old_delta = delta;
263a5a944d2SAngelo Dureghello ri = i;
264a5a944d2SAngelo Dureghello rq = q;
265a5a944d2SAngelo Dureghello }
266a5a944d2SAngelo Dureghello }
267a5a944d2SAngelo Dureghello }
268a5a944d2SAngelo Dureghello
269a5a944d2SAngelo Dureghello /*
270a5a944d2SAngelo Dureghello * Apply divisors and re-enable all the clocks
271a5a944d2SAngelo Dureghello */
272a5a944d2SAngelo Dureghello temp = ((sdclkfs[ri] >> 1) << 8) | ((rq - 1) << 4) |
273a5a944d2SAngelo Dureghello (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN);
274a5a944d2SAngelo Dureghello esdhc_clrset_be(host, 0x0000fff7, temp, SDHCI_CLOCK_CONTROL);
275a5a944d2SAngelo Dureghello
276a5a944d2SAngelo Dureghello host->mmc->actual_clock = clock;
277a5a944d2SAngelo Dureghello
278a5a944d2SAngelo Dureghello mdelay(1);
279a5a944d2SAngelo Dureghello }
280a5a944d2SAngelo Dureghello
esdhc_mcf_pltfm_set_bus_width(struct sdhci_host * host,int width)281a5a944d2SAngelo Dureghello static void esdhc_mcf_pltfm_set_bus_width(struct sdhci_host *host, int width)
282a5a944d2SAngelo Dureghello {
283a5a944d2SAngelo Dureghello struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
284a5a944d2SAngelo Dureghello struct pltfm_mcf_data *mcf_data = sdhci_pltfm_priv(pltfm_host);
285a5a944d2SAngelo Dureghello
286a5a944d2SAngelo Dureghello switch (width) {
287a5a944d2SAngelo Dureghello case MMC_BUS_WIDTH_4:
288a5a944d2SAngelo Dureghello mcf_data->current_bus_width = ESDHC_CTRL_4BITBUS;
289a5a944d2SAngelo Dureghello break;
290a5a944d2SAngelo Dureghello default:
291a5a944d2SAngelo Dureghello mcf_data->current_bus_width = 0;
292a5a944d2SAngelo Dureghello break;
293a5a944d2SAngelo Dureghello }
294a5a944d2SAngelo Dureghello
295a5a944d2SAngelo Dureghello esdhc_clrset_be(host, ESDHC_CTRL_BUSWIDTH_MASK,
296a5a944d2SAngelo Dureghello mcf_data->current_bus_width, SDHCI_HOST_CONTROL);
297a5a944d2SAngelo Dureghello }
298a5a944d2SAngelo Dureghello
esdhc_mcf_request_done(struct sdhci_host * host,struct mmc_request * mrq)299a5a944d2SAngelo Dureghello static void esdhc_mcf_request_done(struct sdhci_host *host,
300a5a944d2SAngelo Dureghello struct mmc_request *mrq)
301a5a944d2SAngelo Dureghello {
302a5a944d2SAngelo Dureghello struct scatterlist *sg;
303a5a944d2SAngelo Dureghello u32 *buffer;
304a5a944d2SAngelo Dureghello int i;
305a5a944d2SAngelo Dureghello
306a5a944d2SAngelo Dureghello if (!mrq->data || !mrq->data->bytes_xfered)
307a5a944d2SAngelo Dureghello goto exit_done;
308a5a944d2SAngelo Dureghello
309a5a944d2SAngelo Dureghello if (mmc_get_dma_dir(mrq->data) != DMA_FROM_DEVICE)
310a5a944d2SAngelo Dureghello goto exit_done;
311a5a944d2SAngelo Dureghello
312a5a944d2SAngelo Dureghello /*
313a5a944d2SAngelo Dureghello * On mcf5441x there is no hw sdma option/flag to select the dma
314a5a944d2SAngelo Dureghello * transfer endiannes. A swap after the transfer is needed.
315a5a944d2SAngelo Dureghello */
316a5a944d2SAngelo Dureghello for_each_sg(mrq->data->sg, sg, mrq->data->sg_len, i) {
317a5a944d2SAngelo Dureghello buffer = (u32 *)sg_virt(sg);
318a5a944d2SAngelo Dureghello esdhc_mcf_buffer_swap32(buffer, sg->length);
319a5a944d2SAngelo Dureghello }
320a5a944d2SAngelo Dureghello
321a5a944d2SAngelo Dureghello exit_done:
322a5a944d2SAngelo Dureghello mmc_request_done(host->mmc, mrq);
323a5a944d2SAngelo Dureghello }
324a5a944d2SAngelo Dureghello
esdhc_mcf_copy_to_bounce_buffer(struct sdhci_host * host,struct mmc_data * data,unsigned int length)325a5a944d2SAngelo Dureghello static void esdhc_mcf_copy_to_bounce_buffer(struct sdhci_host *host,
326a5a944d2SAngelo Dureghello struct mmc_data *data,
327a5a944d2SAngelo Dureghello unsigned int length)
328a5a944d2SAngelo Dureghello {
329a5a944d2SAngelo Dureghello sg_copy_to_buffer(data->sg, data->sg_len,
330a5a944d2SAngelo Dureghello host->bounce_buffer, length);
331a5a944d2SAngelo Dureghello
332a5a944d2SAngelo Dureghello esdhc_mcf_buffer_swap32((u32 *)host->bounce_buffer,
333a5a944d2SAngelo Dureghello data->blksz * data->blocks);
334a5a944d2SAngelo Dureghello }
335a5a944d2SAngelo Dureghello
336a5a944d2SAngelo Dureghello static struct sdhci_ops sdhci_esdhc_ops = {
337a5a944d2SAngelo Dureghello .reset = esdhc_mcf_reset,
338a5a944d2SAngelo Dureghello .set_clock = esdhc_mcf_pltfm_set_clock,
339a5a944d2SAngelo Dureghello .get_max_clock = esdhc_mcf_pltfm_get_max_clock,
340a5a944d2SAngelo Dureghello .get_min_clock = esdhc_mcf_pltfm_get_min_clock,
341a5a944d2SAngelo Dureghello .set_bus_width = esdhc_mcf_pltfm_set_bus_width,
342a5a944d2SAngelo Dureghello .get_max_timeout_count = esdhc_mcf_get_max_timeout_count,
343a5a944d2SAngelo Dureghello .set_timeout = esdhc_mcf_set_timeout,
344a5a944d2SAngelo Dureghello .write_b = esdhc_mcf_writeb_be,
345a5a944d2SAngelo Dureghello .write_w = esdhc_mcf_writew_be,
346a5a944d2SAngelo Dureghello .write_l = esdhc_mcf_writel_be,
347a5a944d2SAngelo Dureghello .read_b = esdhc_mcf_readb_be,
348a5a944d2SAngelo Dureghello .read_w = esdhc_mcf_readw_be,
349a5a944d2SAngelo Dureghello .read_l = esdhc_mcf_readl_be,
350a5a944d2SAngelo Dureghello .copy_to_bounce_buffer = esdhc_mcf_copy_to_bounce_buffer,
351a5a944d2SAngelo Dureghello .request_done = esdhc_mcf_request_done,
352a5a944d2SAngelo Dureghello };
353a5a944d2SAngelo Dureghello
354a5a944d2SAngelo Dureghello static const struct sdhci_pltfm_data sdhci_esdhc_mcf_pdata = {
355a5a944d2SAngelo Dureghello .ops = &sdhci_esdhc_ops,
356a5a944d2SAngelo Dureghello .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_FORCE_DMA,
357a5a944d2SAngelo Dureghello /*
358a5a944d2SAngelo Dureghello * Mandatory quirk,
359a5a944d2SAngelo Dureghello * controller does not support cmd23,
360a5a944d2SAngelo Dureghello * without, on > 8G cards cmd23 is used, and
361a5a944d2SAngelo Dureghello * driver times out.
362a5a944d2SAngelo Dureghello */
363a5a944d2SAngelo Dureghello SDHCI_QUIRK2_HOST_NO_CMD23,
364a5a944d2SAngelo Dureghello };
365a5a944d2SAngelo Dureghello
esdhc_mcf_plat_init(struct sdhci_host * host,struct pltfm_mcf_data * mcf_data)366a5a944d2SAngelo Dureghello static int esdhc_mcf_plat_init(struct sdhci_host *host,
367a5a944d2SAngelo Dureghello struct pltfm_mcf_data *mcf_data)
368a5a944d2SAngelo Dureghello {
369a5a944d2SAngelo Dureghello struct mcf_esdhc_platform_data *plat_data;
370bac53336SJisheng Zhang struct device *dev = mmc_dev(host->mmc);
371a5a944d2SAngelo Dureghello
372bac53336SJisheng Zhang if (!dev->platform_data) {
373bac53336SJisheng Zhang dev_err(dev, "no platform data!\n");
374a5a944d2SAngelo Dureghello return -EINVAL;
375a5a944d2SAngelo Dureghello }
376a5a944d2SAngelo Dureghello
377bac53336SJisheng Zhang plat_data = (struct mcf_esdhc_platform_data *)dev->platform_data;
378a5a944d2SAngelo Dureghello
379a5a944d2SAngelo Dureghello /* Card_detect */
380a5a944d2SAngelo Dureghello switch (plat_data->cd_type) {
381a5a944d2SAngelo Dureghello default:
382a5a944d2SAngelo Dureghello case ESDHC_CD_CONTROLLER:
383a5a944d2SAngelo Dureghello /* We have a working card_detect back */
384a5a944d2SAngelo Dureghello host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
385a5a944d2SAngelo Dureghello break;
386a5a944d2SAngelo Dureghello case ESDHC_CD_PERMANENT:
387a5a944d2SAngelo Dureghello host->mmc->caps |= MMC_CAP_NONREMOVABLE;
388a5a944d2SAngelo Dureghello break;
389a5a944d2SAngelo Dureghello case ESDHC_CD_NONE:
390a5a944d2SAngelo Dureghello break;
391a5a944d2SAngelo Dureghello }
392a5a944d2SAngelo Dureghello
393a5a944d2SAngelo Dureghello switch (plat_data->max_bus_width) {
394a5a944d2SAngelo Dureghello case 4:
395a5a944d2SAngelo Dureghello host->mmc->caps |= MMC_CAP_4_BIT_DATA;
396a5a944d2SAngelo Dureghello break;
397a5a944d2SAngelo Dureghello case 1:
398a5a944d2SAngelo Dureghello default:
399a5a944d2SAngelo Dureghello host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
400a5a944d2SAngelo Dureghello break;
401a5a944d2SAngelo Dureghello }
402a5a944d2SAngelo Dureghello
403a5a944d2SAngelo Dureghello return 0;
404a5a944d2SAngelo Dureghello }
405a5a944d2SAngelo Dureghello
sdhci_esdhc_mcf_probe(struct platform_device * pdev)406a5a944d2SAngelo Dureghello static int sdhci_esdhc_mcf_probe(struct platform_device *pdev)
407a5a944d2SAngelo Dureghello {
408a5a944d2SAngelo Dureghello struct sdhci_host *host;
409a5a944d2SAngelo Dureghello struct sdhci_pltfm_host *pltfm_host;
410a5a944d2SAngelo Dureghello struct pltfm_mcf_data *mcf_data;
411a5a944d2SAngelo Dureghello int err;
412a5a944d2SAngelo Dureghello
413a5a944d2SAngelo Dureghello host = sdhci_pltfm_init(pdev, &sdhci_esdhc_mcf_pdata,
414a5a944d2SAngelo Dureghello sizeof(*mcf_data));
415a5a944d2SAngelo Dureghello
416a5a944d2SAngelo Dureghello if (IS_ERR(host))
417a5a944d2SAngelo Dureghello return PTR_ERR(host);
418a5a944d2SAngelo Dureghello
419a5a944d2SAngelo Dureghello pltfm_host = sdhci_priv(host);
420a5a944d2SAngelo Dureghello mcf_data = sdhci_pltfm_priv(pltfm_host);
421a5a944d2SAngelo Dureghello
422a5a944d2SAngelo Dureghello host->sdma_boundary = 0;
423a5a944d2SAngelo Dureghello
424a5a944d2SAngelo Dureghello host->flags |= SDHCI_AUTO_CMD12;
425a5a944d2SAngelo Dureghello
426a5a944d2SAngelo Dureghello mcf_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
427a5a944d2SAngelo Dureghello if (IS_ERR(mcf_data->clk_ipg)) {
428a5a944d2SAngelo Dureghello err = PTR_ERR(mcf_data->clk_ipg);
429a5a944d2SAngelo Dureghello goto err_exit;
430a5a944d2SAngelo Dureghello }
431a5a944d2SAngelo Dureghello
432a5a944d2SAngelo Dureghello mcf_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
433a5a944d2SAngelo Dureghello if (IS_ERR(mcf_data->clk_ahb)) {
434a5a944d2SAngelo Dureghello err = PTR_ERR(mcf_data->clk_ahb);
435a5a944d2SAngelo Dureghello goto err_exit;
436a5a944d2SAngelo Dureghello }
437a5a944d2SAngelo Dureghello
438a5a944d2SAngelo Dureghello mcf_data->clk_per = devm_clk_get(&pdev->dev, "per");
439a5a944d2SAngelo Dureghello if (IS_ERR(mcf_data->clk_per)) {
440a5a944d2SAngelo Dureghello err = PTR_ERR(mcf_data->clk_per);
441a5a944d2SAngelo Dureghello goto err_exit;
442a5a944d2SAngelo Dureghello }
443a5a944d2SAngelo Dureghello
444a5a944d2SAngelo Dureghello pltfm_host->clk = mcf_data->clk_per;
445a5a944d2SAngelo Dureghello pltfm_host->clock = clk_get_rate(pltfm_host->clk);
446a5a944d2SAngelo Dureghello err = clk_prepare_enable(mcf_data->clk_per);
447a5a944d2SAngelo Dureghello if (err)
448a5a944d2SAngelo Dureghello goto err_exit;
449a5a944d2SAngelo Dureghello
450a5a944d2SAngelo Dureghello err = clk_prepare_enable(mcf_data->clk_ipg);
451a5a944d2SAngelo Dureghello if (err)
452a5a944d2SAngelo Dureghello goto unprep_per;
453a5a944d2SAngelo Dureghello
454a5a944d2SAngelo Dureghello err = clk_prepare_enable(mcf_data->clk_ahb);
455a5a944d2SAngelo Dureghello if (err)
456a5a944d2SAngelo Dureghello goto unprep_ipg;
457a5a944d2SAngelo Dureghello
458a5a944d2SAngelo Dureghello err = esdhc_mcf_plat_init(host, mcf_data);
459a5a944d2SAngelo Dureghello if (err)
460a5a944d2SAngelo Dureghello goto unprep_ahb;
461a5a944d2SAngelo Dureghello
462a5a944d2SAngelo Dureghello err = sdhci_setup_host(host);
463a5a944d2SAngelo Dureghello if (err)
464a5a944d2SAngelo Dureghello goto unprep_ahb;
465a5a944d2SAngelo Dureghello
466a5a944d2SAngelo Dureghello if (!host->bounce_buffer) {
467a5a944d2SAngelo Dureghello dev_err(&pdev->dev, "bounce buffer not allocated");
468a5a944d2SAngelo Dureghello err = -ENOMEM;
469a5a944d2SAngelo Dureghello goto cleanup;
470a5a944d2SAngelo Dureghello }
471a5a944d2SAngelo Dureghello
472a5a944d2SAngelo Dureghello err = __sdhci_add_host(host);
473a5a944d2SAngelo Dureghello if (err)
474a5a944d2SAngelo Dureghello goto cleanup;
475a5a944d2SAngelo Dureghello
476a5a944d2SAngelo Dureghello return 0;
477a5a944d2SAngelo Dureghello
478a5a944d2SAngelo Dureghello cleanup:
479a5a944d2SAngelo Dureghello sdhci_cleanup_host(host);
480a5a944d2SAngelo Dureghello unprep_ahb:
481a5a944d2SAngelo Dureghello clk_disable_unprepare(mcf_data->clk_ahb);
482a5a944d2SAngelo Dureghello unprep_ipg:
483a5a944d2SAngelo Dureghello clk_disable_unprepare(mcf_data->clk_ipg);
484a5a944d2SAngelo Dureghello unprep_per:
485a5a944d2SAngelo Dureghello clk_disable_unprepare(mcf_data->clk_per);
486a5a944d2SAngelo Dureghello err_exit:
487a5a944d2SAngelo Dureghello sdhci_pltfm_free(pdev);
488a5a944d2SAngelo Dureghello
489a5a944d2SAngelo Dureghello return err;
490a5a944d2SAngelo Dureghello }
491a5a944d2SAngelo Dureghello
sdhci_esdhc_mcf_remove(struct platform_device * pdev)492*bd0e512bSYangtao Li static void sdhci_esdhc_mcf_remove(struct platform_device *pdev)
493a5a944d2SAngelo Dureghello {
494a5a944d2SAngelo Dureghello struct sdhci_host *host = platform_get_drvdata(pdev);
495a5a944d2SAngelo Dureghello struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
496a5a944d2SAngelo Dureghello struct pltfm_mcf_data *mcf_data = sdhci_pltfm_priv(pltfm_host);
497a5a944d2SAngelo Dureghello
498a5a944d2SAngelo Dureghello sdhci_remove_host(host, 0);
499a5a944d2SAngelo Dureghello
500a5a944d2SAngelo Dureghello clk_disable_unprepare(mcf_data->clk_ipg);
501a5a944d2SAngelo Dureghello clk_disable_unprepare(mcf_data->clk_ahb);
502a5a944d2SAngelo Dureghello clk_disable_unprepare(mcf_data->clk_per);
503a5a944d2SAngelo Dureghello
504a5a944d2SAngelo Dureghello sdhci_pltfm_free(pdev);
505a5a944d2SAngelo Dureghello }
506a5a944d2SAngelo Dureghello
507a5a944d2SAngelo Dureghello static struct platform_driver sdhci_esdhc_mcf_driver = {
508a5a944d2SAngelo Dureghello .driver = {
509a5a944d2SAngelo Dureghello .name = "sdhci-esdhc-mcf",
51031ae4035SDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS,
511a5a944d2SAngelo Dureghello },
512a5a944d2SAngelo Dureghello .probe = sdhci_esdhc_mcf_probe,
513*bd0e512bSYangtao Li .remove_new = sdhci_esdhc_mcf_remove,
514a5a944d2SAngelo Dureghello };
515a5a944d2SAngelo Dureghello
516a5a944d2SAngelo Dureghello module_platform_driver(sdhci_esdhc_mcf_driver);
517a5a944d2SAngelo Dureghello
518a5a944d2SAngelo Dureghello MODULE_DESCRIPTION("SDHCI driver for Freescale ColdFire eSDHC");
519a5a944d2SAngelo Dureghello MODULE_AUTHOR("Angelo Dureghello <angelo.dureghello@timesys.com>");
520a5a944d2SAngelo Dureghello MODULE_LICENSE("GPL v2");
521