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/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls2080a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
5 * Copyright 2014-2016 Freescale Semiconductor, Inc.
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include "fsl-ls208xa.dtsi"
18 compatible = "arm,cortex-a57";
21 cpu-idle-states = <&CPU_PW20>;
22 next-level-cache = <&cluster0_l2>;
23 #cooling-cells = <2>;
28 compatible = "arm,cortex-a57";
[all …]
H A Dfsl-ls1028a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1028A family SoC.
5 * Copyright 2018-2020 NXP
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <1>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dv3-v360epc-pci.txt6 - compatible: should be one of:
7 "v3,v360epc-pci"
8 "arm,integrator-ap-pci", "v3,v360epc-pci"
9 - reg: should contain two register areas:
12 - interrupts: should contain a reference to the V3 error interrupt
14 - bus-range: see pci.txt
15 - ranges: this follows the standard PCI bindings in the IEEE Std
16 1275-1994 (see pci.txt) with the following restriction:
17 - The non-prefetchable and prefetchable memory windows must
19 - The prefetchable memory window must be immediately adjacent
[all …]
H A Dnvidia,tegra20-pcie.txt4 - compatible: Must be:
5 - "nvidia,tegra20-pcie": for Tegra20
6 - "nvidia,tegra30-pcie": for Tegra30
7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132
8 - "nvidia,tegra210-pcie": for Tegra210
9 - "nvidia,tegra186-pcie": for Tegra186
10 - power-domains: To ungate power partition by BPMP powergate driver. Must
13 - device_type: Must be "pci"
14 - reg: A list of physical base address and length for each set of controller
15 registers. Must contain an entry for each entry in the reg-names property.
[all …]
H A Dversatile.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
16 - $ref: /schemas/pci/pci-bus.yaml#
20 const: arm,versatile-pci
24 - description: Versatile-specific registers
25 - description: Self Config space
26 - description: Config space
31 "#interrupt-cells": true
[all …]
H A Dfaraday,ftpci100.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
21 The plain variant has 128MiB of non-prefetchable memory space, whereas the
27 and should point to respective interrupt in that controller in its interrupt-map.
29 The code which is the only documentation of how the Faraday PCI (the non-dual
34 interrupt-map-mask = <0xf800 0 0 7>;
35 interrupt-map =
54 - $ref: /schemas/pci/pci-bus.yaml#
[all …]
H A Dhost-generic-pci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/host-generic-pci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
13 Firmware-initialised PCI host controllers and PCI emulations, such as the
14 virtio-pci implementations found in kvmtool and other para-virtualised
21 Configuration Space is assumed to be memory-mapped (as opposed to being
26 For CAM, this 24-bit offset is:
41 - description:
[all …]
H A Dnvidia,tegra194-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
16 inherits all the common properties defined in snps,dw-pcie.yaml. Some of
20 See nvidia,tegra194-pcie-ep.yaml for details on the Endpoint mode device
26 - nvidia,tegra194-pcie
[all …]
H A Dpci-armada8k.txt4 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
7 - compatible: "marvell,armada8k-pcie"
8 - reg: must contain two register regions
9 - the control register region
10 - the config space region
11 - reg-names:
12 - "ctrl" for the control register region
13 - "config" for the config space region
14 - interrupts: Interrupt specifier for the PCIe controller
15 - clocks: reference to the PCIe controller clocks
[all …]
H A Dlayerscape-pci.txt4 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
7 which is used to describe the PLL settings at the time of chip-reset.
15 - compatible: should contain the platform identifier such as:
17 "fsl,ls1021a-pcie"
18 "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"
19 "fsl,ls2088a-pcie"
20 "fsl,ls1088a-pcie"
21 "fsl,ls1046a-pcie"
22 "fsl,ls1043a-pcie"
23 "fsl,ls1012a-pcie"
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dfsl-ls2080a.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR X11
5 * Copyright 2013-2015 Freescale Semiconductor, Inc.
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
17 /* DRAM space - 1, size : 2 GB DRAM */
20 gic: interrupt-controller@6000000 {
21 compatible = "arm,gic-v3";
24 #interrupt-cells = <3>;
25 interrupt-controller;
[all …]
H A Dfsl-ls1088a.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR X11
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
17 /* DRAM space - 1, size : 2 GB DRAM */
20 gic: interrupt-controller@6000000 {
21 compatible = "arm,gic-v3";
24 #interrupt-cells = <3>;
25 interrupt-controller;
30 compatible = "arm,armv8-timer";
[all …]
H A Dfsl-ls1043a.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
5 * Copyright (C) 2014-2015, Freescale Semiconductor
14 interrupt-parent = <&gic>;
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
19 clock-frequency = <100000000>;
20 clock-output-names = "sysclk";
23 gic: interrupt-controller@1400000 {
24 compatible = "arm,gic-400";
[all …]
H A Dfsl-ls1046a.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
14 interrupt-parent = <&gic>;
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
19 clock-frequency = <100000000>;
20 clock-output-names = "sysclk";
23 gic: interrupt-controller@1400000 {
24 compatible = "arm,gic-400";
25 #interrupt-cells = <3>;
[all …]
H A Darmada-cp110-slave.dtsi4 * This file is dual-licensed: you can use it either under the terms
47 #include <dt-bindings/comphy/comphy_data.h>
50 cp110-slave {
51 #address-cells = <2>;
52 #size-cells = <2>;
53 compatible = "simple-bus";
54 interrupt-parent = <&gic>;
57 config-space {
58 #address-cells = <1>;
59 #size-cells = <1>;
[all …]
H A Darmada-cp110-master.dtsi4 * This file is dual-licensed: you can use it either under the terms
47 #include <dt-bindings/comphy/comphy_data.h>
50 cp110-master {
51 #address-cells = <2>;
52 #size-cells = <2>;
53 compatible = "simple-bus";
54 interrupt-parent = <&gic>;
57 config-space {
58 #address-cells = <1>;
59 #size-cells = <1>;
[all …]
/openbmc/linux/drivers/pci/
H A Dsetup-bus.c1 // SPDX-License-Identifier: GPL-2.0
11 * PCI-PCI bridges cleanup, sorted resource allocation.
14 * tighter packing. Prefetchable range support.
47 list_del(&dev_res->list); in free_list()
53 * add_to_list() - Add a new resource tracker to the list
68 return -ENOMEM; in add_to_list()
70 tmp->res = res; in add_to_list()
71 tmp->dev = dev; in add_to_list()
72 tmp->start = res->start; in add_to_list()
73 tmp->end = res->end; in add_to_list()
[all …]
H A Dsetup-res.c1 // SPDX-License-Identifier: GPL-2.0
32 struct resource *res = dev->resource + resno; in pci_std_update_resource()
34 /* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */ in pci_std_update_resource()
35 if (dev->is_virtfn) in pci_std_update_resource()
42 if (!res->flags) in pci_std_update_resource()
45 if (res->flags & IORESOURCE_UNSET) in pci_std_update_resource()
49 * Ignore non-moveable resources. This might be legacy resources for in pci_std_update_resource()
53 if (res->flags & IORESOURCE_PCI_FIXED) in pci_std_update_resource()
56 pcibios_resource_to_bus(dev->bus, &region, res); in pci_std_update_resource()
59 if (res->flags & IORESOURCE_IO) { in pci_std_update_resource()
[all …]
/openbmc/linux/drivers/pci/controller/
H A Dpci-v3-semi.c1 // SPDX-License-Identifier: GPL-2.0
6 * Based on the code from arch/arm/mach-integrator/pci_v3.c
8 * Copyright (C) 2000-2001 Deep Blue Solutions Ltd
134 /* PCI BASE bits (PCI -> Local Bus) */
141 /* PCI MAP bits (PCI -> Local bus) */
150 /* LB_BASE0,1 bits (Local bus -> PCI) */
172 /* LB_MAP0,1 bits (Local bus -> PCI) */
185 /* LB_BASE2 bits (Local bus -> PCI IO) */
192 /* LB_MAP2 bits (Local bus -> PCI IO) */
229 /* ARM Integrator-specific extended control registers */
[all …]
/openbmc/u-boot/board/armltd/integrator/
H A Dpci.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
25 #include "integrator-sc.h"
33 * where we read and write stuff - you don't want to try to
46 * range that devices actually use - what would they be doing at
106 * Linux calls the thing U-Boot calls "DEV" "SLOT" in v3_open_config_window()
114 * build the PCI configuration "address" with one-hot in in v3_open_config_window()
115 * A31-A11 in v3_open_config_window()
128 mapaddress |= 1 << (slot - 5); in v3_open_config_window()
153 * prefetchable), this frees up base1 for re-use by in v3_open_config_window()
[all …]
/openbmc/qemu/docs/
H A Dpcie_pci_bridge.txt6 PCIE-to-PCI bridge is a new method for legacy PCI
9 Previously Intel DMI-to-PCI bridge was used for this purpose.
10 But due to its strict limitations - no support of hot-plug,
11 no cross-platform and cross-architecture support - a new generic
12 PCIE-to-PCI bridge should now be used for any legacy PCI device usage
15 This generic PCIE-PCI bridge is a cross-platform device,
16 can be hot-plugged into appropriate root port (requires additional actions,
17 see 'PCIE-PCI bridge hot-plug' section),
18 and supports devices hot-plug into the bridge itself
21 Hot-plug of legacy PCI devices into the bridge
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dspear1310.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
15 compatible = "st,spear-spics-gpio";
17 st-spics,peripcfg-reg = <0x3b0>;
18 st-spics,sw-enable-bit = <12>;
19 st-spics,cs-value-bit = <11>;
20 st-spics,cs-enable-mask = <3>;
21 st-spics,cs-enable-shift = <8>;
22 gpio-controller;
23 #gpio-cells = <2>;
27 compatible = "st,spear1310-miphy";
[all …]
/openbmc/qemu/include/hw/pci/
H A Dpci_bridge.h18 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
54 #define TYPE_PCI_BRIDGE "base-pci-bridge"
70 * The regions are as large as the entire address space -
107 #define TYPE_PXB_CXL_BUS "pxb-cxl-bus"
120 #define TYPE_PXB_CXL_DEV "pxb-cxl"
158 #define PCI_BRIDGE_CTL_VGA_16BIT 0x10 /* VGA 16-bit decode */
167 uint8_t len; /* Standard PCI vendor-specific capability header field */
168 uint8_t type; /* Red Hat vendor-specific capability type.
173 uint32_t mem; /* Non-prefetchable memory to reserve */
175 * different from -1 */
[all …]
/openbmc/linux/arch/arm/boot/dts/arm/
H A Dversatile-pb.dts1 // SPDX-License-Identifier: GPL-2.0
2 #include "versatile-ab.dts"
6 compatible = "arm,versatile-pb";
10 sic: interrupt-controller@10003000 {
11 clear-mask = <0xffffffff>;
14 * figure 3-30 page 3-74 of ARM DUI 0224B
16 valid-mask = <0x7fe003ff>;
23 gpio-controller;
24 #gpio-cells = <2>;
25 interrupt-controller;
[all …]
/openbmc/linux/arch/x86/pci/
H A Dbroadcom_bus.c1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #include <asm/pci-direct.h>
45 /* read the non-prefetchable memory window */ in cnb20le_res()
55 /* read the prefetchable memory window */ in cnb20le_res()
81 list_for_each_entry(root_res, &info->resources, list) in cnb20le_res()
82 printk(KERN_INFO "host bridge window %pR\n", &root_res->res); in cnb20le_res()

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