10d09e41aSPaolo Bonzini /* 20d09e41aSPaolo Bonzini * QEMU PCI bridge 30d09e41aSPaolo Bonzini * 40d09e41aSPaolo Bonzini * Copyright (c) 2004 Fabrice Bellard 50d09e41aSPaolo Bonzini * 60d09e41aSPaolo Bonzini * This program is free software; you can redistribute it and/or modify 70d09e41aSPaolo Bonzini * it under the terms of the GNU General Public License as published by 80d09e41aSPaolo Bonzini * the Free Software Foundation; either version 2 of the License, or 90d09e41aSPaolo Bonzini * (at your option) any later version. 100d09e41aSPaolo Bonzini * 110d09e41aSPaolo Bonzini * This program is distributed in the hope that it will be useful, 120d09e41aSPaolo Bonzini * but WITHOUT ANY WARRANTY; without even the implied warranty of 130d09e41aSPaolo Bonzini * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 140d09e41aSPaolo Bonzini * GNU General Public License for more details. 150d09e41aSPaolo Bonzini * 160d09e41aSPaolo Bonzini * You should have received a copy of the GNU General Public License 170d09e41aSPaolo Bonzini * along with this program; if not, write to the Free Software 180d09e41aSPaolo Bonzini * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 190d09e41aSPaolo Bonzini * 200d09e41aSPaolo Bonzini * split out pci bus specific stuff from pci.[hc] to pci_bridge.[hc] 210d09e41aSPaolo Bonzini * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp> 220d09e41aSPaolo Bonzini * VA Linux Systems Japan K.K. 230d09e41aSPaolo Bonzini * 240d09e41aSPaolo Bonzini */ 250d09e41aSPaolo Bonzini 260d09e41aSPaolo Bonzini #ifndef QEMU_PCI_BRIDGE_H 270d09e41aSPaolo Bonzini #define QEMU_PCI_BRIDGE_H 280d09e41aSPaolo Bonzini 29edf5ca5dSMarkus Armbruster #include "hw/pci/pci_device.h" 30791bf3c8SDavid Gibson #include "hw/pci/pci_bus.h" 313d6a69b6SBen Widawsky #include "hw/cxl/cxl.h" 32db1015e9SEduardo Habkost #include "qom/object.h" 33791bf3c8SDavid Gibson 34791bf3c8SDavid Gibson typedef struct PCIBridgeWindows PCIBridgeWindows; 35791bf3c8SDavid Gibson 36791bf3c8SDavid Gibson /* 37791bf3c8SDavid Gibson * Aliases for each of the address space windows that the bridge 38791bf3c8SDavid Gibson * can forward. Mapped into the bridge's parent's address space, 39791bf3c8SDavid Gibson * as subregions. 40791bf3c8SDavid Gibson */ 41791bf3c8SDavid Gibson struct PCIBridgeWindows { 42791bf3c8SDavid Gibson MemoryRegion alias_pref_mem; 43791bf3c8SDavid Gibson MemoryRegion alias_mem; 44791bf3c8SDavid Gibson MemoryRegion alias_io; 45791bf3c8SDavid Gibson /* 46791bf3c8SDavid Gibson * When bridge control VGA forwarding is enabled, bridges will 47791bf3c8SDavid Gibson * provide positive decode on the PCI VGA defined I/O port and 48791bf3c8SDavid Gibson * MMIO ranges. When enabled forwarding is only qualified on the 49791bf3c8SDavid Gibson * I/O and memory enable bits in the bridge command register. 50791bf3c8SDavid Gibson */ 51791bf3c8SDavid Gibson MemoryRegion alias_vga[QEMU_PCI_VGA_NUM_REGIONS]; 52791bf3c8SDavid Gibson }; 53791bf3c8SDavid Gibson 54791bf3c8SDavid Gibson #define TYPE_PCI_BRIDGE "base-pci-bridge" 558063396bSEduardo Habkost OBJECT_DECLARE_SIMPLE_TYPE(PCIBridge, PCI_BRIDGE) 56ad494274SIgor Mammedov #define IS_PCI_BRIDGE(dev) object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE) 57791bf3c8SDavid Gibson 58791bf3c8SDavid Gibson struct PCIBridge { 59791bf3c8SDavid Gibson /*< private >*/ 60791bf3c8SDavid Gibson PCIDevice parent_obj; 61791bf3c8SDavid Gibson /*< public >*/ 62791bf3c8SDavid Gibson 63791bf3c8SDavid Gibson /* private member */ 64791bf3c8SDavid Gibson PCIBus sec_bus; 65791bf3c8SDavid Gibson /* 66791bf3c8SDavid Gibson * Memory regions for the bridge's address spaces. These regions are not 67791bf3c8SDavid Gibson * directly added to system_memory/system_io or its descendants. 68791bf3c8SDavid Gibson * Bridge's secondary bus points to these, so that devices 69791bf3c8SDavid Gibson * under the bridge see these regions as its address spaces. 70791bf3c8SDavid Gibson * The regions are as large as the entire address space - 71791bf3c8SDavid Gibson * they don't take into account any windows. 72791bf3c8SDavid Gibson */ 73791bf3c8SDavid Gibson MemoryRegion address_space_mem; 74791bf3c8SDavid Gibson MemoryRegion address_space_io; 75791bf3c8SDavid Gibson 76b2999ed8SJonathan Cameron PCIBridgeWindows windows; 77791bf3c8SDavid Gibson 78791bf3c8SDavid Gibson pci_map_irq_fn map_irq; 79791bf3c8SDavid Gibson const char *bus_name; 80*4565917bSMichael S. Tsirkin 81*4565917bSMichael S. Tsirkin /* SLT is RO for PCIE to PCIE bridges, but old QEMU versions had it RW */ 82*4565917bSMichael S. Tsirkin bool pcie_writeable_slt_bug; 83791bf3c8SDavid Gibson }; 840d09e41aSPaolo Bonzini 853cf0ecb3SLaszlo Ersek #define PCI_BRIDGE_DEV_PROP_CHASSIS_NR "chassis_nr" 867a7c6a41SLaszlo Ersek #define PCI_BRIDGE_DEV_PROP_MSI "msi" 874e5c9bfeSLaszlo Ersek #define PCI_BRIDGE_DEV_PROP_SHPC "shpc" 883d6a69b6SBen Widawsky typedef struct CXLHost CXLHost; 893d6a69b6SBen Widawsky 90c28db9e0SJonathan Cameron typedef struct PXBDev { 913d6a69b6SBen Widawsky /*< private >*/ 923d6a69b6SBen Widawsky PCIDevice parent_obj; 933d6a69b6SBen Widawsky /*< public >*/ 943d6a69b6SBen Widawsky 953d6a69b6SBen Widawsky uint8_t bus_nr; 963d6a69b6SBen Widawsky uint16_t numa_node; 973d6a69b6SBen Widawsky bool bypass_iommu; 98c28db9e0SJonathan Cameron } PXBDev; 993d6a69b6SBen Widawsky 100c28db9e0SJonathan Cameron typedef struct PXBPCIEDev { 101c28db9e0SJonathan Cameron /*< private >*/ 102c28db9e0SJonathan Cameron PXBDev parent_obj; 103c28db9e0SJonathan Cameron } PXBPCIEDev; 104c28db9e0SJonathan Cameron 105c28db9e0SJonathan Cameron #define TYPE_PXB_DEV "pxb" 106c28db9e0SJonathan Cameron OBJECT_DECLARE_SIMPLE_TYPE(PXBDev, PXB_DEV) 107c28db9e0SJonathan Cameron 108c28db9e0SJonathan Cameron typedef struct PXBCXLDev { 109c28db9e0SJonathan Cameron /*< private >*/ 110c28db9e0SJonathan Cameron PXBPCIEDev parent_obj; 111c28db9e0SJonathan Cameron /*< public >*/ 112c28db9e0SJonathan Cameron 113c28db9e0SJonathan Cameron bool hdm_for_passthrough; 114c28db9e0SJonathan Cameron CXLHost *cxl_host_bridge; /* Pointer to a CXLHost */ 115c28db9e0SJonathan Cameron } PXBCXLDev; 116c28db9e0SJonathan Cameron 117c28db9e0SJonathan Cameron #define TYPE_PXB_CXL_DEV "pxb-cxl" 118c28db9e0SJonathan Cameron OBJECT_DECLARE_SIMPLE_TYPE(PXBCXLDev, PXB_CXL_DEV) 1193cf0ecb3SLaszlo Ersek 1200d09e41aSPaolo Bonzini int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset, 121f8cd1b02SMao Zhongyi uint16_t svid, uint16_t ssid, 122f8cd1b02SMao Zhongyi Error **errp); 1230d09e41aSPaolo Bonzini 1240d09e41aSPaolo Bonzini PCIDevice *pci_bridge_get_device(PCIBus *bus); 1250d09e41aSPaolo Bonzini PCIBus *pci_bridge_get_sec_bus(PCIBridge *br); 1260d09e41aSPaolo Bonzini 1270d09e41aSPaolo Bonzini pcibus_t pci_bridge_get_base(const PCIDevice *bridge, uint8_t type); 1280d09e41aSPaolo Bonzini pcibus_t pci_bridge_get_limit(const PCIDevice *bridge, uint8_t type); 1290d09e41aSPaolo Bonzini 130e78e9ae4SDon Koch void pci_bridge_update_mappings(PCIBridge *br); 1310d09e41aSPaolo Bonzini void pci_bridge_write_config(PCIDevice *d, 1320d09e41aSPaolo Bonzini uint32_t address, uint32_t val, int len); 1330d09e41aSPaolo Bonzini void pci_bridge_disable_base_limit(PCIDevice *dev); 1340d09e41aSPaolo Bonzini void pci_bridge_reset(DeviceState *qdev); 1350d09e41aSPaolo Bonzini 1369cfaa007SCao jin void pci_bridge_initfn(PCIDevice *pci_dev, const char *typename); 1370d09e41aSPaolo Bonzini void pci_bridge_exitfn(PCIDevice *pci_dev); 1380d09e41aSPaolo Bonzini 13962b76563SDavid Hildenbrand void pci_bridge_dev_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, 14062b76563SDavid Hildenbrand Error **errp); 1418f560cdcSDavid Hildenbrand void pci_bridge_dev_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, 1428f560cdcSDavid Hildenbrand Error **errp); 14362b76563SDavid Hildenbrand void pci_bridge_dev_unplug_request_cb(HotplugHandler *hotplug_dev, 14462b76563SDavid Hildenbrand DeviceState *dev, Error **errp); 1450d09e41aSPaolo Bonzini 1460d09e41aSPaolo Bonzini /* 1470d09e41aSPaolo Bonzini * before qdev initialization(qdev_init()), this function sets bus_name and 148b7709d0eSJulia Suvorova * map_irq callback which are necessary for pci_bridge_initfn() to 1490d09e41aSPaolo Bonzini * initialize bus. 1500d09e41aSPaolo Bonzini */ 1510d09e41aSPaolo Bonzini void pci_bridge_map_irq(PCIBridge *br, const char* bus_name, 1520d09e41aSPaolo Bonzini pci_map_irq_fn map_irq); 1530d09e41aSPaolo Bonzini 1540d09e41aSPaolo Bonzini /* TODO: add this define to pci_regs.h in linux and then in qemu. */ 1550d09e41aSPaolo Bonzini #define PCI_BRIDGE_CTL_VGA_16BIT 0x10 /* VGA 16-bit decode */ 1560d09e41aSPaolo Bonzini #define PCI_BRIDGE_CTL_DISCARD 0x100 /* Primary discard timer */ 1570d09e41aSPaolo Bonzini #define PCI_BRIDGE_CTL_SEC_DISCARD 0x200 /* Secondary discard timer */ 1580d09e41aSPaolo Bonzini #define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400 /* Discard timer status */ 1590d09e41aSPaolo Bonzini #define PCI_BRIDGE_CTL_DISCARD_SERR 0x800 /* Discard timer SERR# enable */ 1600d09e41aSPaolo Bonzini 16170e1ee59SAleksandr Bezzubikov typedef struct PCIBridgeQemuCap { 16270e1ee59SAleksandr Bezzubikov uint8_t id; /* Standard PCI capability header field */ 16370e1ee59SAleksandr Bezzubikov uint8_t next; /* Standard PCI capability header field */ 16470e1ee59SAleksandr Bezzubikov uint8_t len; /* Standard PCI vendor-specific capability header field */ 16570e1ee59SAleksandr Bezzubikov uint8_t type; /* Red Hat vendor-specific capability type. 16670e1ee59SAleksandr Bezzubikov Types are defined with REDHAT_PCI_CAP_ prefix */ 16770e1ee59SAleksandr Bezzubikov 16870e1ee59SAleksandr Bezzubikov uint32_t bus_res; /* Minimum number of buses to reserve */ 16970e1ee59SAleksandr Bezzubikov uint64_t io; /* IO space to reserve */ 17070e1ee59SAleksandr Bezzubikov uint32_t mem; /* Non-prefetchable memory to reserve */ 17170e1ee59SAleksandr Bezzubikov /* At most one of the following two fields may be set to a value 17270e1ee59SAleksandr Bezzubikov * different from -1 */ 17370e1ee59SAleksandr Bezzubikov uint32_t mem_pref_32; /* Prefetchable memory to reserve (32-bit MMIO) */ 17470e1ee59SAleksandr Bezzubikov uint64_t mem_pref_64; /* Prefetchable memory to reserve (64-bit MMIO) */ 17570e1ee59SAleksandr Bezzubikov } PCIBridgeQemuCap; 17670e1ee59SAleksandr Bezzubikov 177efe84f03SLaurent Vivier #define REDHAT_PCI_CAP_TYPE_OFFSET 3 17870e1ee59SAleksandr Bezzubikov #define REDHAT_PCI_CAP_RESOURCE_RESERVE 1 17970e1ee59SAleksandr Bezzubikov 1809e899399SJing Liu /* 1819e899399SJing Liu * PCI BUS/IO/MEM/PREFMEM additional resources recorded as a 1829e899399SJing Liu * capability in PCI configuration space to reserve on firmware init. 1839e899399SJing Liu */ 1849e899399SJing Liu typedef struct PCIResReserve { 1859e899399SJing Liu uint32_t bus; 1869e899399SJing Liu uint64_t io; 1879e899399SJing Liu uint64_t mem_non_pref; 1889e899399SJing Liu uint64_t mem_pref_32; 1899e899399SJing Liu uint64_t mem_pref_64; 1909e899399SJing Liu } PCIResReserve; 1919e899399SJing Liu 192efe84f03SLaurent Vivier #define REDHAT_PCI_CAP_RES_RESERVE_BUS_RES 4 193efe84f03SLaurent Vivier #define REDHAT_PCI_CAP_RES_RESERVE_IO 8 194efe84f03SLaurent Vivier #define REDHAT_PCI_CAP_RES_RESERVE_MEM 16 195efe84f03SLaurent Vivier #define REDHAT_PCI_CAP_RES_RESERVE_PREF_MEM_32 20 196efe84f03SLaurent Vivier #define REDHAT_PCI_CAP_RES_RESERVE_PREF_MEM_64 24 197efe84f03SLaurent Vivier #define REDHAT_PCI_CAP_RES_RESERVE_CAP_SIZE 32 198efe84f03SLaurent Vivier 19970e1ee59SAleksandr Bezzubikov int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset, 2009e899399SJing Liu PCIResReserve res_reserve, Error **errp); 20170e1ee59SAleksandr Bezzubikov 2020d09e41aSPaolo Bonzini #endif /* QEMU_PCI_BRIDGE_H */ 203