1e4dffb67SVidya Sagar# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2e4dffb67SVidya Sagar%YAML 1.2 3e4dffb67SVidya Sagar--- 4e4dffb67SVidya Sagar$id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml# 5e4dffb67SVidya Sagar$schema: http://devicetree.org/meta-schemas/core.yaml# 6e4dffb67SVidya Sagar 7e4dffb67SVidya Sagartitle: NVIDIA Tegra194 (and later) PCIe controller (Synopsys DesignWare Core based) 8e4dffb67SVidya Sagar 9e4dffb67SVidya Sagarmaintainers: 10e4dffb67SVidya Sagar - Thierry Reding <thierry.reding@gmail.com> 11e4dffb67SVidya Sagar - Jon Hunter <jonathanh@nvidia.com> 12e4dffb67SVidya Sagar - Vidya Sagar <vidyas@nvidia.com> 13e4dffb67SVidya Sagar 14e4dffb67SVidya Sagardescription: | 15e4dffb67SVidya Sagar This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus 16e4dffb67SVidya Sagar inherits all the common properties defined in snps,dw-pcie.yaml. Some of 17e4dffb67SVidya Sagar the controller instances are dual mode where in they can work either in 18e4dffb67SVidya Sagar Root Port mode or Endpoint mode but one at a time. 19e4dffb67SVidya Sagar 20e4dffb67SVidya Sagar See nvidia,tegra194-pcie-ep.yaml for details on the Endpoint mode device 21e4dffb67SVidya Sagar tree bindings. 22e4dffb67SVidya Sagar 23e4dffb67SVidya Sagarproperties: 24e4dffb67SVidya Sagar compatible: 25e4dffb67SVidya Sagar enum: 26e4dffb67SVidya Sagar - nvidia,tegra194-pcie 273e4ff9a6SVidya Sagar - nvidia,tegra234-pcie 28e4dffb67SVidya Sagar 29e4dffb67SVidya Sagar reg: 30*5c374149SVidya Sagar minItems: 4 31e4dffb67SVidya Sagar items: 32e4dffb67SVidya Sagar - description: controller's application logic registers 33e4dffb67SVidya Sagar - description: configuration registers 34e4dffb67SVidya Sagar - description: iATU and DMA registers. This is where the iATU (internal 35e4dffb67SVidya Sagar Address Translation Unit) registers of the PCIe core are made 36e4dffb67SVidya Sagar available for software access. 37e4dffb67SVidya Sagar - description: aperture where the Root Port's own configuration 38e4dffb67SVidya Sagar registers are available. 39*5c374149SVidya Sagar - description: aperture to access the configuration space through ECAM. 40e4dffb67SVidya Sagar 41e4dffb67SVidya Sagar reg-names: 42*5c374149SVidya Sagar minItems: 4 43e4dffb67SVidya Sagar items: 44e4dffb67SVidya Sagar - const: appl 45e4dffb67SVidya Sagar - const: config 46e4dffb67SVidya Sagar - const: atu_dma 47e4dffb67SVidya Sagar - const: dbi 48*5c374149SVidya Sagar - const: ecam 49e4dffb67SVidya Sagar 50e4dffb67SVidya Sagar interrupts: 51e4dffb67SVidya Sagar items: 52e4dffb67SVidya Sagar - description: controller interrupt 53e4dffb67SVidya Sagar - description: MSI interrupt 54e4dffb67SVidya Sagar 55e4dffb67SVidya Sagar interrupt-names: 56e4dffb67SVidya Sagar items: 57e4dffb67SVidya Sagar - const: intr 58e4dffb67SVidya Sagar - const: msi 59e4dffb67SVidya Sagar 60e4dffb67SVidya Sagar clocks: 61e4dffb67SVidya Sagar items: 62e4dffb67SVidya Sagar - description: module clock 63e4dffb67SVidya Sagar 64e4dffb67SVidya Sagar clock-names: 65e4dffb67SVidya Sagar items: 66e4dffb67SVidya Sagar - const: core 67e4dffb67SVidya Sagar 68e4dffb67SVidya Sagar resets: 69e4dffb67SVidya Sagar items: 70e4dffb67SVidya Sagar - description: APB bus interface reset 71e4dffb67SVidya Sagar - description: module reset 72e4dffb67SVidya Sagar 73e4dffb67SVidya Sagar reset-names: 74e4dffb67SVidya Sagar items: 75e4dffb67SVidya Sagar - const: apb 76e4dffb67SVidya Sagar - const: core 77e4dffb67SVidya Sagar 78e4dffb67SVidya Sagar phys: 79e4dffb67SVidya Sagar minItems: 1 80e4dffb67SVidya Sagar maxItems: 8 81e4dffb67SVidya Sagar 82e4dffb67SVidya Sagar phy-names: 83e4dffb67SVidya Sagar minItems: 1 84e4dffb67SVidya Sagar items: 85e4dffb67SVidya Sagar - const: p2u-0 86e4dffb67SVidya Sagar - const: p2u-1 87e4dffb67SVidya Sagar - const: p2u-2 88e4dffb67SVidya Sagar - const: p2u-3 89e4dffb67SVidya Sagar - const: p2u-4 90e4dffb67SVidya Sagar - const: p2u-5 91e4dffb67SVidya Sagar - const: p2u-6 92e4dffb67SVidya Sagar - const: p2u-7 93e4dffb67SVidya Sagar 94e4dffb67SVidya Sagar power-domains: 95e4dffb67SVidya Sagar maxItems: 1 96e4dffb67SVidya Sagar description: | 97e4dffb67SVidya Sagar A phandle to the node that controls power to the respective PCIe 98e4dffb67SVidya Sagar controller and a specifier name for the PCIe controller. 99e4dffb67SVidya Sagar 1003e4ff9a6SVidya Sagar Tegra194 specifiers defined in "include/dt-bindings/power/tegra194-powergate.h" 1013e4ff9a6SVidya Sagar Tegra234 specifiers defined in "include/dt-bindings/power/tegra234-powergate.h" 102e4dffb67SVidya Sagar 103e4dffb67SVidya Sagar interconnects: 104e4dffb67SVidya Sagar items: 105e4dffb67SVidya Sagar - description: memory read client 106e4dffb67SVidya Sagar - description: memory write client 107e4dffb67SVidya Sagar 108e4dffb67SVidya Sagar interconnect-names: 109e4dffb67SVidya Sagar items: 110e4dffb67SVidya Sagar - const: dma-mem # read 111e4dffb67SVidya Sagar - const: write 112e4dffb67SVidya Sagar 113e4dffb67SVidya Sagar dma-coherent: true 114e4dffb67SVidya Sagar 115e4dffb67SVidya Sagar nvidia,bpmp: 116e4dffb67SVidya Sagar $ref: /schemas/types.yaml#/definitions/phandle-array 117e4dffb67SVidya Sagar description: | 118e4dffb67SVidya Sagar Must contain a pair of phandles to BPMP controller node followed by 119e4dffb67SVidya Sagar controller ID. Following are the controller IDs for each controller: 120e4dffb67SVidya Sagar 1213e4ff9a6SVidya Sagar Tegra194 1223e4ff9a6SVidya Sagar 123e4dffb67SVidya Sagar 0: C0 124e4dffb67SVidya Sagar 1: C1 125e4dffb67SVidya Sagar 2: C2 126e4dffb67SVidya Sagar 3: C3 127e4dffb67SVidya Sagar 4: C4 128e4dffb67SVidya Sagar 5: C5 1293e4ff9a6SVidya Sagar 1303e4ff9a6SVidya Sagar Tegra234 1313e4ff9a6SVidya Sagar 1323e4ff9a6SVidya Sagar 0 : C0 1333e4ff9a6SVidya Sagar 1 : C1 1343e4ff9a6SVidya Sagar 2 : C2 1353e4ff9a6SVidya Sagar 3 : C3 1363e4ff9a6SVidya Sagar 4 : C4 1373e4ff9a6SVidya Sagar 5 : C5 1383e4ff9a6SVidya Sagar 6 : C6 1393e4ff9a6SVidya Sagar 7 : C7 1403e4ff9a6SVidya Sagar 8 : C8 1413e4ff9a6SVidya Sagar 9 : C9 1423e4ff9a6SVidya Sagar 10: C10 1433e4ff9a6SVidya Sagar 144e4dffb67SVidya Sagar items: 145e4dffb67SVidya Sagar - items: 146e4dffb67SVidya Sagar - description: phandle to BPMP controller node 147e4dffb67SVidya Sagar - description: PCIe controller ID 1483e4ff9a6SVidya Sagar maximum: 10 149e4dffb67SVidya Sagar 150e4dffb67SVidya Sagar nvidia,update-fc-fixup: 151e4dffb67SVidya Sagar description: | 152e4dffb67SVidya Sagar This is a boolean property and needs to be present to improve performance 153e4dffb67SVidya Sagar when a platform is designed in such a way that it satisfies at least one 154e4dffb67SVidya Sagar of the following conditions thereby enabling Root Port to exchange 155e4dffb67SVidya Sagar optimum number of FC (Flow Control) credits with downstream devices: 156e4dffb67SVidya Sagar 1573e4ff9a6SVidya Sagar NOTE: This is applicable only for Tegra194. 1583e4ff9a6SVidya Sagar 159e4dffb67SVidya Sagar 1. If C0/C4/C5 run at x1/x2 link widths (irrespective of speed and MPS) 160e4dffb67SVidya Sagar 2. If C0/C1/C2/C3/C4/C5 operate at their respective max link widths and 161e4dffb67SVidya Sagar a) speed is Gen-2 and MPS is 256B 162e4dffb67SVidya Sagar b) speed is >= Gen-3 with any MPS 163e4dffb67SVidya Sagar 164e4dffb67SVidya Sagar $ref: /schemas/types.yaml#/definitions/flag 165e4dffb67SVidya Sagar 166e4dffb67SVidya Sagar nvidia,aspm-cmrt-us: 167e4dffb67SVidya Sagar description: Common Mode Restore Time for proper operation of ASPM to be 168e4dffb67SVidya Sagar specified in microseconds 169e4dffb67SVidya Sagar 170e4dffb67SVidya Sagar nvidia,aspm-pwr-on-t-us: 171e4dffb67SVidya Sagar description: Power On time for proper operation of ASPM to be specified in 172e4dffb67SVidya Sagar microseconds 173e4dffb67SVidya Sagar 174e4dffb67SVidya Sagar nvidia,aspm-l0s-entrance-latency-us: 175e4dffb67SVidya Sagar description: ASPM L0s entrance latency to be specified in microseconds 176e4dffb67SVidya Sagar 177e4dffb67SVidya Sagar vddio-pex-ctl-supply: 178e4dffb67SVidya Sagar description: A phandle to the regulator supply for PCIe side band signals. 179e4dffb67SVidya Sagar 180e4dffb67SVidya Sagar vpcie3v3-supply: 181e4dffb67SVidya Sagar description: A phandle to the regulator node that supplies 3.3V to the slot 182e4dffb67SVidya Sagar if the platform has one such slot, e.g., x16 slot owned by C5 controller 183e4dffb67SVidya Sagar in p2972-0000 platform. 184e4dffb67SVidya Sagar 185e4dffb67SVidya Sagar vpcie12v-supply: 186e4dffb67SVidya Sagar description: A phandle to the regulator node that supplies 12V to the slot 187e4dffb67SVidya Sagar if the platform has one such slot, e.g., x16 slot owned by C5 controller 188e4dffb67SVidya Sagar in p2972-0000 platform. 189e4dffb67SVidya Sagar 1903e4ff9a6SVidya Sagar nvidia,enable-srns: 1913e4ff9a6SVidya Sagar description: | 1923e4ff9a6SVidya Sagar This boolean property needs to be present if the controller is 1933e4ff9a6SVidya Sagar configured to operate in SRNS (Separate Reference Clocks with No 1943e4ff9a6SVidya Sagar Spread-Spectrum Clocking). NOTE: This is applicable only for 1953e4ff9a6SVidya Sagar Tegra234. 1963e4ff9a6SVidya Sagar 1973e4ff9a6SVidya Sagar $ref: /schemas/types.yaml#/definitions/flag 1983e4ff9a6SVidya Sagar 1993e4ff9a6SVidya Sagar nvidia,enable-ext-refclk: 2003e4ff9a6SVidya Sagar description: | 2013e4ff9a6SVidya Sagar This boolean property needs to be present if the controller is 2023e4ff9a6SVidya Sagar configured to use the reference clocking coming in from an external 2033e4ff9a6SVidya Sagar clock source instead of using the internal clock source. 2043e4ff9a6SVidya Sagar 2053e4ff9a6SVidya Sagar $ref: /schemas/types.yaml#/definitions/flag 2063e4ff9a6SVidya Sagar 207e4dffb67SVidya SagarallOf: 208e4dffb67SVidya Sagar - $ref: /schemas/pci/snps,dw-pcie.yaml# 209*5c374149SVidya Sagar - if: 210*5c374149SVidya Sagar properties: 211*5c374149SVidya Sagar compatible: 212*5c374149SVidya Sagar contains: 213*5c374149SVidya Sagar enum: 214*5c374149SVidya Sagar - nvidia,tegra194-pcie 215*5c374149SVidya Sagar then: 216*5c374149SVidya Sagar properties: 217*5c374149SVidya Sagar reg: 218*5c374149SVidya Sagar maxItems: 4 219*5c374149SVidya Sagar reg-names: 220*5c374149SVidya Sagar maxItems: 4 221*5c374149SVidya Sagar 222*5c374149SVidya Sagar - if: 223*5c374149SVidya Sagar properties: 224*5c374149SVidya Sagar compatible: 225*5c374149SVidya Sagar contains: 226*5c374149SVidya Sagar enum: 227*5c374149SVidya Sagar - nvidia,tegra234-pcie 228*5c374149SVidya Sagar then: 229*5c374149SVidya Sagar properties: 230*5c374149SVidya Sagar reg: 231*5c374149SVidya Sagar minItems: 5 232*5c374149SVidya Sagar reg-names: 233*5c374149SVidya Sagar minItems: 5 234e4dffb67SVidya Sagar 235e4dffb67SVidya SagarunevaluatedProperties: false 236e4dffb67SVidya Sagar 237e4dffb67SVidya Sagarrequired: 238e4dffb67SVidya Sagar - interrupts 239e4dffb67SVidya Sagar - interrupt-names 240e4dffb67SVidya Sagar - interrupt-map 241e4dffb67SVidya Sagar - interrupt-map-mask 242e4dffb67SVidya Sagar - clocks 243e4dffb67SVidya Sagar - clock-names 244e4dffb67SVidya Sagar - resets 245e4dffb67SVidya Sagar - reset-names 246e4dffb67SVidya Sagar - power-domains 247e4dffb67SVidya Sagar - vddio-pex-ctl-supply 248e4dffb67SVidya Sagar - num-lanes 249e4dffb67SVidya Sagar - phys 250e4dffb67SVidya Sagar - phy-names 251e4dffb67SVidya Sagar - nvidia,bpmp 252e4dffb67SVidya Sagar 253e4dffb67SVidya Sagarexamples: 254e4dffb67SVidya Sagar - | 255e4dffb67SVidya Sagar #include <dt-bindings/clock/tegra194-clock.h> 256e4dffb67SVidya Sagar #include <dt-bindings/interrupt-controller/arm-gic.h> 257e4dffb67SVidya Sagar #include <dt-bindings/power/tegra194-powergate.h> 258e4dffb67SVidya Sagar #include <dt-bindings/reset/tegra194-reset.h> 259e4dffb67SVidya Sagar 260e4dffb67SVidya Sagar bus@0 { 261e4dffb67SVidya Sagar #address-cells = <2>; 262e4dffb67SVidya Sagar #size-cells = <2>; 263e4dffb67SVidya Sagar ranges = <0x0 0x0 0x0 0x8 0x0>; 264e4dffb67SVidya Sagar 265e4dffb67SVidya Sagar pcie@14180000 { 266e4dffb67SVidya Sagar compatible = "nvidia,tegra194-pcie"; 267e4dffb67SVidya Sagar power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 268e4dffb67SVidya Sagar reg = <0x0 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 269e4dffb67SVidya Sagar <0x0 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 270e4dffb67SVidya Sagar <0x0 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 271e4dffb67SVidya Sagar <0x0 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 272e4dffb67SVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi"; 273e4dffb67SVidya Sagar 274e4dffb67SVidya Sagar #address-cells = <3>; 275e4dffb67SVidya Sagar #size-cells = <2>; 276e4dffb67SVidya Sagar device_type = "pci"; 277e4dffb67SVidya Sagar num-lanes = <8>; 278e4dffb67SVidya Sagar linux,pci-domain = <0>; 279e4dffb67SVidya Sagar 280e4dffb67SVidya Sagar pinctrl-names = "default"; 281e4dffb67SVidya Sagar pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 282e4dffb67SVidya Sagar 283e4dffb67SVidya Sagar clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 284e4dffb67SVidya Sagar clock-names = "core"; 285e4dffb67SVidya Sagar 286e4dffb67SVidya Sagar resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 287e4dffb67SVidya Sagar <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 288e4dffb67SVidya Sagar reset-names = "apb", "core"; 289e4dffb67SVidya Sagar 290e4dffb67SVidya Sagar interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 291e4dffb67SVidya Sagar <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 292e4dffb67SVidya Sagar interrupt-names = "intr", "msi"; 293e4dffb67SVidya Sagar 294e4dffb67SVidya Sagar #interrupt-cells = <1>; 295e4dffb67SVidya Sagar interrupt-map-mask = <0 0 0 0>; 296e4dffb67SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 297e4dffb67SVidya Sagar 298e4dffb67SVidya Sagar nvidia,bpmp = <&bpmp 0>; 299e4dffb67SVidya Sagar 300e4dffb67SVidya Sagar supports-clkreq; 301e4dffb67SVidya Sagar nvidia,aspm-cmrt-us = <60>; 302e4dffb67SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 303e4dffb67SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 304e4dffb67SVidya Sagar 305e4dffb67SVidya Sagar bus-range = <0x0 0xff>; 306e4dffb67SVidya Sagar ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000>, /* downstream I/O */ 307e4dffb67SVidya Sagar <0x82000000 0x0 0x38200000 0x0 0x38200000 0x0 0x01e00000>, /* non-prefetch memory */ 308e4dffb67SVidya Sagar <0xc2000000 0x18 0x00000000 0x18 0x00000000 0x4 0x00000000>; /* prefetchable memory */ 309e4dffb67SVidya Sagar 310e4dffb67SVidya Sagar vddio-pex-ctl-supply = <&vdd_1v8ao>; 311e4dffb67SVidya Sagar vpcie3v3-supply = <&vdd_3v3_pcie>; 312e4dffb67SVidya Sagar vpcie12v-supply = <&vdd_12v_pcie>; 313e4dffb67SVidya Sagar 314e4dffb67SVidya Sagar phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>, 315e4dffb67SVidya Sagar <&p2u_hsio_5>; 316e4dffb67SVidya Sagar phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3"; 317e4dffb67SVidya Sagar }; 318e4dffb67SVidya Sagar }; 3193e4ff9a6SVidya Sagar 3203e4ff9a6SVidya Sagar - | 3213e4ff9a6SVidya Sagar #include <dt-bindings/clock/tegra234-clock.h> 3223e4ff9a6SVidya Sagar #include <dt-bindings/interrupt-controller/arm-gic.h> 3233e4ff9a6SVidya Sagar #include <dt-bindings/power/tegra234-powergate.h> 3243e4ff9a6SVidya Sagar #include <dt-bindings/reset/tegra234-reset.h> 3253e4ff9a6SVidya Sagar 3263e4ff9a6SVidya Sagar bus@0 { 3273e4ff9a6SVidya Sagar #address-cells = <2>; 3283e4ff9a6SVidya Sagar #size-cells = <2>; 3293e4ff9a6SVidya Sagar ranges = <0x0 0x0 0x0 0x8 0x0>; 3303e4ff9a6SVidya Sagar 3313e4ff9a6SVidya Sagar pcie@14160000 { 3323e4ff9a6SVidya Sagar compatible = "nvidia,tegra234-pcie"; 3333e4ff9a6SVidya Sagar power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>; 3343e4ff9a6SVidya Sagar reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 3353e4ff9a6SVidya Sagar <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 3363e4ff9a6SVidya Sagar <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 337*5c374149SVidya Sagar <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 338*5c374149SVidya Sagar <0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 339*5c374149SVidya Sagar reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 3403e4ff9a6SVidya Sagar 3413e4ff9a6SVidya Sagar #address-cells = <3>; 3423e4ff9a6SVidya Sagar #size-cells = <2>; 3433e4ff9a6SVidya Sagar device_type = "pci"; 3443e4ff9a6SVidya Sagar num-lanes = <4>; 3453e4ff9a6SVidya Sagar num-viewport = <8>; 3463e4ff9a6SVidya Sagar linux,pci-domain = <4>; 3473e4ff9a6SVidya Sagar 3483e4ff9a6SVidya Sagar clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>; 3493e4ff9a6SVidya Sagar clock-names = "core"; 3503e4ff9a6SVidya Sagar 3513e4ff9a6SVidya Sagar resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>, 3523e4ff9a6SVidya Sagar <&bpmp TEGRA234_RESET_PEX0_CORE_4>; 3533e4ff9a6SVidya Sagar reset-names = "apb", "core"; 3543e4ff9a6SVidya Sagar 3553e4ff9a6SVidya Sagar interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 3563e4ff9a6SVidya Sagar <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 3573e4ff9a6SVidya Sagar interrupt-names = "intr", "msi"; 3583e4ff9a6SVidya Sagar 3593e4ff9a6SVidya Sagar #interrupt-cells = <1>; 3603e4ff9a6SVidya Sagar interrupt-map-mask = <0 0 0 0>; 3613e4ff9a6SVidya Sagar interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 3623e4ff9a6SVidya Sagar 3633e4ff9a6SVidya Sagar nvidia,bpmp = <&bpmp 4>; 3643e4ff9a6SVidya Sagar 3653e4ff9a6SVidya Sagar nvidia,aspm-cmrt-us = <60>; 3663e4ff9a6SVidya Sagar nvidia,aspm-pwr-on-t-us = <20>; 3673e4ff9a6SVidya Sagar nvidia,aspm-l0s-entrance-latency-us = <3>; 3683e4ff9a6SVidya Sagar 3693e4ff9a6SVidya Sagar bus-range = <0x0 0xff>; 3703e4ff9a6SVidya Sagar ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable */ 3713e4ff9a6SVidya Sagar <0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable */ 3723e4ff9a6SVidya Sagar <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O */ 3733e4ff9a6SVidya Sagar 3743e4ff9a6SVidya Sagar vddio-pex-ctl-supply = <&p3701_vdd_AO_1v8>; 3753e4ff9a6SVidya Sagar 3763e4ff9a6SVidya Sagar phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>, 3773e4ff9a6SVidya Sagar <&p2u_hsio_7>; 3783e4ff9a6SVidya Sagar phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3"; 3793e4ff9a6SVidya Sagar }; 3803e4ff9a6SVidya Sagar }; 381