12720b991SCorentin Labbe# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 22720b991SCorentin Labbe%YAML 1.2 32720b991SCorentin Labbe--- 42720b991SCorentin Labbe$id: http://devicetree.org/schemas/pci/faraday,ftpci100.yaml# 52720b991SCorentin Labbe$schema: http://devicetree.org/meta-schemas/core.yaml# 62720b991SCorentin Labbe 72720b991SCorentin Labbetitle: Faraday Technology FTPCI100 PCI Host Bridge 82720b991SCorentin Labbe 92720b991SCorentin Labbemaintainers: 102720b991SCorentin Labbe - Linus Walleij <linus.walleij@linaro.org> 112720b991SCorentin Labbe 122720b991SCorentin Labbedescription: | 132720b991SCorentin Labbe This PCI bridge is found inside that Cortina Systems Gemini SoC platform and 142720b991SCorentin Labbe is a generic IP block from Faraday Technology. It exists in two variants: 152720b991SCorentin Labbe plain and dual PCI. The plain version embeds a cascading interrupt controller 162720b991SCorentin Labbe into the host bridge. The dual version routes the interrupts to the host 172720b991SCorentin Labbe chips interrupt controller. 182720b991SCorentin Labbe The host controller appear on the PCI bus with vendor ID 0x159b (Faraday 192720b991SCorentin Labbe Technology) and product ID 0x4321. 202720b991SCorentin Labbe I/O space considerations: 212720b991SCorentin Labbe The plain variant has 128MiB of non-prefetchable memory space, whereas the 222720b991SCorentin Labbe "dual" variant has 64MiB. Take this into account when describing the ranges. 232720b991SCorentin Labbe 242720b991SCorentin Labbe Interrupt map considerations: 252720b991SCorentin Labbe 262720b991SCorentin Labbe The "dual" variant will get INT A, B, C, D from the system interrupt controller 272720b991SCorentin Labbe and should point to respective interrupt in that controller in its interrupt-map. 282720b991SCorentin Labbe 292720b991SCorentin Labbe The code which is the only documentation of how the Faraday PCI (the non-dual 302720b991SCorentin Labbe variant) interrupts assigns the default interrupt mapping/swizzling has 312720b991SCorentin Labbe typically been like this, doing the swizzling on the interrupt controller side 322720b991SCorentin Labbe rather than in the interconnect: 332720b991SCorentin Labbe 342720b991SCorentin Labbe interrupt-map-mask = <0xf800 0 0 7>; 352720b991SCorentin Labbe interrupt-map = 362720b991SCorentin Labbe <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */ 372720b991SCorentin Labbe <0x4800 0 0 2 &pci_intc 1>, 382720b991SCorentin Labbe <0x4800 0 0 3 &pci_intc 2>, 392720b991SCorentin Labbe <0x4800 0 0 4 &pci_intc 3>, 402720b991SCorentin Labbe <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */ 412720b991SCorentin Labbe <0x5000 0 0 2 &pci_intc 2>, 422720b991SCorentin Labbe <0x5000 0 0 3 &pci_intc 3>, 432720b991SCorentin Labbe <0x5000 0 0 4 &pci_intc 0>, 442720b991SCorentin Labbe <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */ 452720b991SCorentin Labbe <0x5800 0 0 2 &pci_intc 3>, 462720b991SCorentin Labbe <0x5800 0 0 3 &pci_intc 0>, 472720b991SCorentin Labbe <0x5800 0 0 4 &pci_intc 1>, 482720b991SCorentin Labbe <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */ 492720b991SCorentin Labbe <0x6000 0 0 2 &pci_intc 0>, 502720b991SCorentin Labbe <0x6000 0 0 3 &pci_intc 1>, 512720b991SCorentin Labbe <0x6000 0 0 4 &pci_intc 2>; 522720b991SCorentin Labbe 532720b991SCorentin LabbeallOf: 542720b991SCorentin Labbe - $ref: /schemas/pci/pci-bus.yaml# 552720b991SCorentin Labbe 562720b991SCorentin Labbeproperties: 572720b991SCorentin Labbe compatible: 582720b991SCorentin Labbe oneOf: 592720b991SCorentin Labbe - items: 602720b991SCorentin Labbe - const: cortina,gemini-pci 612720b991SCorentin Labbe - const: faraday,ftpci100 622720b991SCorentin Labbe - items: 632720b991SCorentin Labbe - const: cortina,gemini-pci-dual 642720b991SCorentin Labbe - const: faraday,ftpci100-dual 652720b991SCorentin Labbe - const: faraday,ftpci100 662720b991SCorentin Labbe - const: faraday,ftpci100-dual 672720b991SCorentin Labbe 682720b991SCorentin Labbe reg: 692720b991SCorentin Labbe maxItems: 1 702720b991SCorentin Labbe 712720b991SCorentin Labbe "#address-cells": 722720b991SCorentin Labbe const: 3 732720b991SCorentin Labbe 742720b991SCorentin Labbe "#interrupt-cells": 752720b991SCorentin Labbe const: 1 762720b991SCorentin Labbe 772720b991SCorentin Labbe ranges: 782720b991SCorentin Labbe minItems: 2 792720b991SCorentin Labbe 802720b991SCorentin Labbe dma-ranges: 812720b991SCorentin Labbe minItems: 3 822720b991SCorentin Labbe description: | 832720b991SCorentin Labbe three ranges for the inbound memory region. The ranges must 842720b991SCorentin Labbe be aligned to a 1MB boundary, and may be 1MB, 2MB, 4MB, 8MB, 16MB, 32MB, 64MB, 852720b991SCorentin Labbe 128MB, 256MB, 512MB, 1GB or 2GB in size. The memory should be marked as 862720b991SCorentin Labbe pre-fetchable. 872720b991SCorentin Labbe 882720b991SCorentin Labbe clocks: 892720b991SCorentin Labbe items: 902720b991SCorentin Labbe - description: peripheral clock (PCLK) 912720b991SCorentin Labbe - description: PCI clock (PCICLK). 922720b991SCorentin Labbe description: | 932720b991SCorentin Labbe If these are not present, they are assumed to be 942720b991SCorentin Labbe hard-wired enabled and always on. The PCI clock will be 33 or 66 MHz. 952720b991SCorentin Labbe 962720b991SCorentin Labbe clock-names: 972720b991SCorentin Labbe items: 982720b991SCorentin Labbe - const: PCLK 992720b991SCorentin Labbe - const: PCICLK 1002720b991SCorentin Labbe 1012720b991SCorentin Labbe interrupt-controller: 1022720b991SCorentin Labbe type: object 1032720b991SCorentin Labbe 1042720b991SCorentin Labberequired: 1052720b991SCorentin Labbe - reg 1062720b991SCorentin Labbe - compatible 1072720b991SCorentin Labbe - "#interrupt-cells" 1082720b991SCorentin Labbe - interrupt-map-mask 1092720b991SCorentin Labbe - interrupt-map 1102720b991SCorentin Labbe - dma-ranges 1112720b991SCorentin Labbe 1122720b991SCorentin Labbeif: 1132720b991SCorentin Labbe properties: 1142720b991SCorentin Labbe compatible: 1152720b991SCorentin Labbe contains: 116*a083fadfSRob Herring const: faraday,ftpci100 1172720b991SCorentin Labbethen: 1182720b991SCorentin Labbe required: 1192720b991SCorentin Labbe - interrupt-controller 1202720b991SCorentin Labbe 1212720b991SCorentin LabbeunevaluatedProperties: false 1222720b991SCorentin Labbe 1232720b991SCorentin Labbeexamples: 1242720b991SCorentin Labbe - | 1252720b991SCorentin Labbe #include <dt-bindings/interrupt-controller/irq.h> 1262720b991SCorentin Labbe pci@50000000 { 1272720b991SCorentin Labbe compatible = "cortina,gemini-pci", "faraday,ftpci100"; 1282720b991SCorentin Labbe reg = <0x50000000 0x100>; 1292720b991SCorentin Labbe device_type = "pci"; 1302720b991SCorentin Labbe #address-cells = <3>; 1312720b991SCorentin Labbe #size-cells = <2>; 1322720b991SCorentin Labbe #interrupt-cells = <1>; 1332720b991SCorentin Labbe 1342720b991SCorentin Labbe bus-range = <0x00 0xff>; 1352720b991SCorentin Labbe ranges = /* 1MiB I/O space 0x50000000-0x500fffff */ 1362720b991SCorentin Labbe <0x01000000 0 0 0x50000000 0 0x00100000>, 1372720b991SCorentin Labbe /* 128MiB non-prefetchable memory 0x58000000-0x5fffffff */ 1382720b991SCorentin Labbe <0x02000000 0 0x58000000 0x58000000 0 0x08000000>; 1392720b991SCorentin Labbe 1402720b991SCorentin Labbe /* DMA ranges */ 1412720b991SCorentin Labbe dma-ranges = 1422720b991SCorentin Labbe /* 128MiB at 0x00000000-0x07ffffff */ 1432720b991SCorentin Labbe <0x02000000 0 0x00000000 0x00000000 0 0x08000000>, 1442720b991SCorentin Labbe /* 64MiB at 0x00000000-0x03ffffff */ 1452720b991SCorentin Labbe <0x02000000 0 0x00000000 0x00000000 0 0x04000000>, 1462720b991SCorentin Labbe /* 64MiB at 0x00000000-0x03ffffff */ 1472720b991SCorentin Labbe <0x02000000 0 0x00000000 0x00000000 0 0x04000000>; 1482720b991SCorentin Labbe 1492720b991SCorentin Labbe interrupt-map-mask = <0xf800 0 0 7>; 1502720b991SCorentin Labbe interrupt-map = 1512720b991SCorentin Labbe <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */ 1522720b991SCorentin Labbe <0x4800 0 0 2 &pci_intc 1>, 1532720b991SCorentin Labbe <0x4800 0 0 3 &pci_intc 2>, 1542720b991SCorentin Labbe <0x4800 0 0 4 &pci_intc 3>, 1552720b991SCorentin Labbe <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */ 1562720b991SCorentin Labbe <0x5000 0 0 2 &pci_intc 2>, 1572720b991SCorentin Labbe <0x5000 0 0 3 &pci_intc 3>, 1582720b991SCorentin Labbe <0x5000 0 0 4 &pci_intc 0>, 1592720b991SCorentin Labbe <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */ 1602720b991SCorentin Labbe <0x5800 0 0 2 &pci_intc 3>, 1612720b991SCorentin Labbe <0x5800 0 0 3 &pci_intc 0>, 1622720b991SCorentin Labbe <0x5800 0 0 4 &pci_intc 1>, 1632720b991SCorentin Labbe <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */ 1642720b991SCorentin Labbe <0x6000 0 0 2 &pci_intc 0>, 1652720b991SCorentin Labbe <0x6000 0 0 3 &pci_intc 0>, 1662720b991SCorentin Labbe <0x6000 0 0 4 &pci_intc 0>; 1672720b991SCorentin Labbe pci_intc: interrupt-controller { 1682720b991SCorentin Labbe interrupt-parent = <&intcon>; 1692720b991SCorentin Labbe interrupt-controller; 1702720b991SCorentin Labbe interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 1712720b991SCorentin Labbe #address-cells = <0>; 1722720b991SCorentin Labbe #interrupt-cells = <1>; 1732720b991SCorentin Labbe }; 1742720b991SCorentin Labbe }; 175