16e0832faSShawn Lin // SPDX-License-Identifier: GPL-2.0
26e0832faSShawn Lin /*
36e0832faSShawn Lin * Support for V3 Semiconductor PCI Local Bus to PCI Bridge
46e0832faSShawn Lin * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
56e0832faSShawn Lin *
66e0832faSShawn Lin * Based on the code from arch/arm/mach-integrator/pci_v3.c
76e0832faSShawn Lin * Copyright (C) 1999 ARM Limited
86e0832faSShawn Lin * Copyright (C) 2000-2001 Deep Blue Solutions Ltd
96e0832faSShawn Lin *
106e0832faSShawn Lin * Contributors to the old driver include:
116e0832faSShawn Lin * Russell King <linux@armlinux.org.uk>
126e0832faSShawn Lin * David A. Rusling <david.rusling@linaro.org> (uHAL, ARM Firmware suite)
136e0832faSShawn Lin * Rob Herring <robh@kernel.org>
146e0832faSShawn Lin * Liviu Dudau <Liviu.Dudau@arm.com>
156e0832faSShawn Lin * Grant Likely <grant.likely@secretlab.ca>
166e0832faSShawn Lin * Arnd Bergmann <arnd@arndb.de>
176e0832faSShawn Lin * Bjorn Helgaas <bhelgaas@google.com>
186e0832faSShawn Lin */
196e0832faSShawn Lin #include <linux/init.h>
206e0832faSShawn Lin #include <linux/interrupt.h>
216e0832faSShawn Lin #include <linux/io.h>
226e0832faSShawn Lin #include <linux/kernel.h>
23*c925cfafSRob Herring #include <linux/of.h>
246e0832faSShawn Lin #include <linux/of_pci.h>
256e0832faSShawn Lin #include <linux/pci.h>
266e0832faSShawn Lin #include <linux/platform_device.h>
276e0832faSShawn Lin #include <linux/slab.h>
286e0832faSShawn Lin #include <linux/bitops.h>
296e0832faSShawn Lin #include <linux/irq.h>
306e0832faSShawn Lin #include <linux/mfd/syscon.h>
316e0832faSShawn Lin #include <linux/regmap.h>
326e0832faSShawn Lin #include <linux/clk.h>
336e0832faSShawn Lin
346e0832faSShawn Lin #include "../pci.h"
356e0832faSShawn Lin
366e0832faSShawn Lin #define V3_PCI_VENDOR 0x00000000
376e0832faSShawn Lin #define V3_PCI_DEVICE 0x00000002
386e0832faSShawn Lin #define V3_PCI_CMD 0x00000004
396e0832faSShawn Lin #define V3_PCI_STAT 0x00000006
406e0832faSShawn Lin #define V3_PCI_CC_REV 0x00000008
416e0832faSShawn Lin #define V3_PCI_HDR_CFG 0x0000000C
426e0832faSShawn Lin #define V3_PCI_IO_BASE 0x00000010
436e0832faSShawn Lin #define V3_PCI_BASE0 0x00000014
446e0832faSShawn Lin #define V3_PCI_BASE1 0x00000018
456e0832faSShawn Lin #define V3_PCI_SUB_VENDOR 0x0000002C
466e0832faSShawn Lin #define V3_PCI_SUB_ID 0x0000002E
476e0832faSShawn Lin #define V3_PCI_ROM 0x00000030
486e0832faSShawn Lin #define V3_PCI_BPARAM 0x0000003C
496e0832faSShawn Lin #define V3_PCI_MAP0 0x00000040
506e0832faSShawn Lin #define V3_PCI_MAP1 0x00000044
516e0832faSShawn Lin #define V3_PCI_INT_STAT 0x00000048
526e0832faSShawn Lin #define V3_PCI_INT_CFG 0x0000004C
536e0832faSShawn Lin #define V3_LB_BASE0 0x00000054
546e0832faSShawn Lin #define V3_LB_BASE1 0x00000058
556e0832faSShawn Lin #define V3_LB_MAP0 0x0000005E
566e0832faSShawn Lin #define V3_LB_MAP1 0x00000062
576e0832faSShawn Lin #define V3_LB_BASE2 0x00000064
586e0832faSShawn Lin #define V3_LB_MAP2 0x00000066
596e0832faSShawn Lin #define V3_LB_SIZE 0x00000068
606e0832faSShawn Lin #define V3_LB_IO_BASE 0x0000006E
616e0832faSShawn Lin #define V3_FIFO_CFG 0x00000070
626e0832faSShawn Lin #define V3_FIFO_PRIORITY 0x00000072
636e0832faSShawn Lin #define V3_FIFO_STAT 0x00000074
646e0832faSShawn Lin #define V3_LB_ISTAT 0x00000076
656e0832faSShawn Lin #define V3_LB_IMASK 0x00000077
666e0832faSShawn Lin #define V3_SYSTEM 0x00000078
676e0832faSShawn Lin #define V3_LB_CFG 0x0000007A
686e0832faSShawn Lin #define V3_PCI_CFG 0x0000007C
696e0832faSShawn Lin #define V3_DMA_PCI_ADR0 0x00000080
706e0832faSShawn Lin #define V3_DMA_PCI_ADR1 0x00000090
716e0832faSShawn Lin #define V3_DMA_LOCAL_ADR0 0x00000084
726e0832faSShawn Lin #define V3_DMA_LOCAL_ADR1 0x00000094
736e0832faSShawn Lin #define V3_DMA_LENGTH0 0x00000088
746e0832faSShawn Lin #define V3_DMA_LENGTH1 0x00000098
756e0832faSShawn Lin #define V3_DMA_CSR0 0x0000008B
766e0832faSShawn Lin #define V3_DMA_CSR1 0x0000009B
776e0832faSShawn Lin #define V3_DMA_CTLB_ADR0 0x0000008C
786e0832faSShawn Lin #define V3_DMA_CTLB_ADR1 0x0000009C
796e0832faSShawn Lin #define V3_DMA_DELAY 0x000000E0
806e0832faSShawn Lin #define V3_MAIL_DATA 0x000000C0
816e0832faSShawn Lin #define V3_PCI_MAIL_IEWR 0x000000D0
826e0832faSShawn Lin #define V3_PCI_MAIL_IERD 0x000000D2
836e0832faSShawn Lin #define V3_LB_MAIL_IEWR 0x000000D4
846e0832faSShawn Lin #define V3_LB_MAIL_IERD 0x000000D6
856e0832faSShawn Lin #define V3_MAIL_WR_STAT 0x000000D8
866e0832faSShawn Lin #define V3_MAIL_RD_STAT 0x000000DA
876e0832faSShawn Lin #define V3_QBA_MAP 0x000000DC
886e0832faSShawn Lin
896e0832faSShawn Lin /* PCI STATUS bits */
906e0832faSShawn Lin #define V3_PCI_STAT_PAR_ERR BIT(15)
916e0832faSShawn Lin #define V3_PCI_STAT_SYS_ERR BIT(14)
926e0832faSShawn Lin #define V3_PCI_STAT_M_ABORT_ERR BIT(13)
936e0832faSShawn Lin #define V3_PCI_STAT_T_ABORT_ERR BIT(12)
946e0832faSShawn Lin
956e0832faSShawn Lin /* LB ISTAT bits */
966e0832faSShawn Lin #define V3_LB_ISTAT_MAILBOX BIT(7)
976e0832faSShawn Lin #define V3_LB_ISTAT_PCI_RD BIT(6)
986e0832faSShawn Lin #define V3_LB_ISTAT_PCI_WR BIT(5)
996e0832faSShawn Lin #define V3_LB_ISTAT_PCI_INT BIT(4)
1006e0832faSShawn Lin #define V3_LB_ISTAT_PCI_PERR BIT(3)
1016e0832faSShawn Lin #define V3_LB_ISTAT_I2O_QWR BIT(2)
1026e0832faSShawn Lin #define V3_LB_ISTAT_DMA1 BIT(1)
1036e0832faSShawn Lin #define V3_LB_ISTAT_DMA0 BIT(0)
1046e0832faSShawn Lin
1056e0832faSShawn Lin /* PCI COMMAND bits */
1066e0832faSShawn Lin #define V3_COMMAND_M_FBB_EN BIT(9)
1076e0832faSShawn Lin #define V3_COMMAND_M_SERR_EN BIT(8)
1086e0832faSShawn Lin #define V3_COMMAND_M_PAR_EN BIT(6)
1096e0832faSShawn Lin #define V3_COMMAND_M_MASTER_EN BIT(2)
1106e0832faSShawn Lin #define V3_COMMAND_M_MEM_EN BIT(1)
1116e0832faSShawn Lin #define V3_COMMAND_M_IO_EN BIT(0)
1126e0832faSShawn Lin
1136e0832faSShawn Lin /* SYSTEM bits */
1146e0832faSShawn Lin #define V3_SYSTEM_M_RST_OUT BIT(15)
1156e0832faSShawn Lin #define V3_SYSTEM_M_LOCK BIT(14)
1166e0832faSShawn Lin #define V3_SYSTEM_UNLOCK 0xa05f
1176e0832faSShawn Lin
1186e0832faSShawn Lin /* PCI CFG bits */
1196e0832faSShawn Lin #define V3_PCI_CFG_M_I2O_EN BIT(15)
1206e0832faSShawn Lin #define V3_PCI_CFG_M_IO_REG_DIS BIT(14)
1216e0832faSShawn Lin #define V3_PCI_CFG_M_IO_DIS BIT(13)
1226e0832faSShawn Lin #define V3_PCI_CFG_M_EN3V BIT(12)
1236e0832faSShawn Lin #define V3_PCI_CFG_M_RETRY_EN BIT(10)
1246e0832faSShawn Lin #define V3_PCI_CFG_M_AD_LOW1 BIT(9)
1256e0832faSShawn Lin #define V3_PCI_CFG_M_AD_LOW0 BIT(8)
1266e0832faSShawn Lin /*
1276e0832faSShawn Lin * This is the value applied to C/BE[3:1], with bit 0 always held 0
1286e0832faSShawn Lin * during DMA access.
1296e0832faSShawn Lin */
1306e0832faSShawn Lin #define V3_PCI_CFG_M_RTYPE_SHIFT 5
1316e0832faSShawn Lin #define V3_PCI_CFG_M_WTYPE_SHIFT 1
1326e0832faSShawn Lin #define V3_PCI_CFG_TYPE_DEFAULT 0x3
1336e0832faSShawn Lin
1346e0832faSShawn Lin /* PCI BASE bits (PCI -> Local Bus) */
1356e0832faSShawn Lin #define V3_PCI_BASE_M_ADR_BASE 0xFFF00000U
1366e0832faSShawn Lin #define V3_PCI_BASE_M_ADR_BASEL 0x000FFF00U
1376e0832faSShawn Lin #define V3_PCI_BASE_M_PREFETCH BIT(3)
1386e0832faSShawn Lin #define V3_PCI_BASE_M_TYPE (3 << 1)
1396e0832faSShawn Lin #define V3_PCI_BASE_M_IO BIT(0)
1406e0832faSShawn Lin
1416e0832faSShawn Lin /* PCI MAP bits (PCI -> Local bus) */
1426e0832faSShawn Lin #define V3_PCI_MAP_M_MAP_ADR 0xFFF00000U
1436e0832faSShawn Lin #define V3_PCI_MAP_M_RD_POST_INH BIT(15)
1446e0832faSShawn Lin #define V3_PCI_MAP_M_ROM_SIZE (3 << 10)
1456e0832faSShawn Lin #define V3_PCI_MAP_M_SWAP (3 << 8)
1466e0832faSShawn Lin #define V3_PCI_MAP_M_ADR_SIZE 0x000000F0U
1476e0832faSShawn Lin #define V3_PCI_MAP_M_REG_EN BIT(1)
1486e0832faSShawn Lin #define V3_PCI_MAP_M_ENABLE BIT(0)
1496e0832faSShawn Lin
1506e0832faSShawn Lin /* LB_BASE0,1 bits (Local bus -> PCI) */
1516e0832faSShawn Lin #define V3_LB_BASE_ADR_BASE 0xfff00000U
1526e0832faSShawn Lin #define V3_LB_BASE_SWAP (3 << 8)
1536e0832faSShawn Lin #define V3_LB_BASE_ADR_SIZE (15 << 4)
1546e0832faSShawn Lin #define V3_LB_BASE_PREFETCH BIT(3)
1556e0832faSShawn Lin #define V3_LB_BASE_ENABLE BIT(0)
1566e0832faSShawn Lin
1576e0832faSShawn Lin #define V3_LB_BASE_ADR_SIZE_1MB (0 << 4)
1586e0832faSShawn Lin #define V3_LB_BASE_ADR_SIZE_2MB (1 << 4)
1596e0832faSShawn Lin #define V3_LB_BASE_ADR_SIZE_4MB (2 << 4)
1606e0832faSShawn Lin #define V3_LB_BASE_ADR_SIZE_8MB (3 << 4)
1616e0832faSShawn Lin #define V3_LB_BASE_ADR_SIZE_16MB (4 << 4)
1626e0832faSShawn Lin #define V3_LB_BASE_ADR_SIZE_32MB (5 << 4)
1636e0832faSShawn Lin #define V3_LB_BASE_ADR_SIZE_64MB (6 << 4)
1646e0832faSShawn Lin #define V3_LB_BASE_ADR_SIZE_128MB (7 << 4)
1656e0832faSShawn Lin #define V3_LB_BASE_ADR_SIZE_256MB (8 << 4)
1666e0832faSShawn Lin #define V3_LB_BASE_ADR_SIZE_512MB (9 << 4)
1676e0832faSShawn Lin #define V3_LB_BASE_ADR_SIZE_1GB (10 << 4)
1686e0832faSShawn Lin #define V3_LB_BASE_ADR_SIZE_2GB (11 << 4)
1696e0832faSShawn Lin
1706e0832faSShawn Lin #define v3_addr_to_lb_base(a) ((a) & V3_LB_BASE_ADR_BASE)
1716e0832faSShawn Lin
1726e0832faSShawn Lin /* LB_MAP0,1 bits (Local bus -> PCI) */
1736e0832faSShawn Lin #define V3_LB_MAP_MAP_ADR 0xfff0U
1746e0832faSShawn Lin #define V3_LB_MAP_TYPE (7 << 1)
1756e0832faSShawn Lin #define V3_LB_MAP_AD_LOW_EN BIT(0)
1766e0832faSShawn Lin
1776e0832faSShawn Lin #define V3_LB_MAP_TYPE_IACK (0 << 1)
1786e0832faSShawn Lin #define V3_LB_MAP_TYPE_IO (1 << 1)
1796e0832faSShawn Lin #define V3_LB_MAP_TYPE_MEM (3 << 1)
1806e0832faSShawn Lin #define V3_LB_MAP_TYPE_CONFIG (5 << 1)
1816e0832faSShawn Lin #define V3_LB_MAP_TYPE_MEM_MULTIPLE (6 << 1)
1826e0832faSShawn Lin
1836e0832faSShawn Lin #define v3_addr_to_lb_map(a) (((a) >> 16) & V3_LB_MAP_MAP_ADR)
1846e0832faSShawn Lin
1856e0832faSShawn Lin /* LB_BASE2 bits (Local bus -> PCI IO) */
1866e0832faSShawn Lin #define V3_LB_BASE2_ADR_BASE 0xff00U
1876e0832faSShawn Lin #define V3_LB_BASE2_SWAP_AUTO (3 << 6)
1886e0832faSShawn Lin #define V3_LB_BASE2_ENABLE BIT(0)
1896e0832faSShawn Lin
1906e0832faSShawn Lin #define v3_addr_to_lb_base2(a) (((a) >> 16) & V3_LB_BASE2_ADR_BASE)
1916e0832faSShawn Lin
1926e0832faSShawn Lin /* LB_MAP2 bits (Local bus -> PCI IO) */
1936e0832faSShawn Lin #define V3_LB_MAP2_MAP_ADR 0xff00U
1946e0832faSShawn Lin
1956e0832faSShawn Lin #define v3_addr_to_lb_map2(a) (((a) >> 16) & V3_LB_MAP2_MAP_ADR)
1966e0832faSShawn Lin
1976e0832faSShawn Lin /* FIFO priority bits */
1986e0832faSShawn Lin #define V3_FIFO_PRIO_LOCAL BIT(12)
1996e0832faSShawn Lin #define V3_FIFO_PRIO_LB_RD1_FLUSH_EOB BIT(10)
2006e0832faSShawn Lin #define V3_FIFO_PRIO_LB_RD1_FLUSH_AP1 BIT(11)
2016e0832faSShawn Lin #define V3_FIFO_PRIO_LB_RD1_FLUSH_ANY (BIT(10)|BIT(11))
2026e0832faSShawn Lin #define V3_FIFO_PRIO_LB_RD0_FLUSH_EOB BIT(8)
2036e0832faSShawn Lin #define V3_FIFO_PRIO_LB_RD0_FLUSH_AP1 BIT(9)
2046e0832faSShawn Lin #define V3_FIFO_PRIO_LB_RD0_FLUSH_ANY (BIT(8)|BIT(9))
2056e0832faSShawn Lin #define V3_FIFO_PRIO_PCI BIT(4)
2066e0832faSShawn Lin #define V3_FIFO_PRIO_PCI_RD1_FLUSH_EOB BIT(2)
2076e0832faSShawn Lin #define V3_FIFO_PRIO_PCI_RD1_FLUSH_AP1 BIT(3)
2086e0832faSShawn Lin #define V3_FIFO_PRIO_PCI_RD1_FLUSH_ANY (BIT(2)|BIT(3))
2096e0832faSShawn Lin #define V3_FIFO_PRIO_PCI_RD0_FLUSH_EOB BIT(0)
2106e0832faSShawn Lin #define V3_FIFO_PRIO_PCI_RD0_FLUSH_AP1 BIT(1)
2116e0832faSShawn Lin #define V3_FIFO_PRIO_PCI_RD0_FLUSH_ANY (BIT(0)|BIT(1))
2126e0832faSShawn Lin
2136e0832faSShawn Lin /* Local bus configuration bits */
2146e0832faSShawn Lin #define V3_LB_CFG_LB_TO_64_CYCLES 0x0000
2156e0832faSShawn Lin #define V3_LB_CFG_LB_TO_256_CYCLES BIT(13)
2166e0832faSShawn Lin #define V3_LB_CFG_LB_TO_512_CYCLES BIT(14)
2176e0832faSShawn Lin #define V3_LB_CFG_LB_TO_1024_CYCLES (BIT(13)|BIT(14))
2186e0832faSShawn Lin #define V3_LB_CFG_LB_RST BIT(12)
2196e0832faSShawn Lin #define V3_LB_CFG_LB_PPC_RDY BIT(11)
2206e0832faSShawn Lin #define V3_LB_CFG_LB_LB_INT BIT(10)
2216e0832faSShawn Lin #define V3_LB_CFG_LB_ERR_EN BIT(9)
2226e0832faSShawn Lin #define V3_LB_CFG_LB_RDY_EN BIT(8)
2236e0832faSShawn Lin #define V3_LB_CFG_LB_BE_IMODE BIT(7)
2246e0832faSShawn Lin #define V3_LB_CFG_LB_BE_OMODE BIT(6)
2256e0832faSShawn Lin #define V3_LB_CFG_LB_ENDIAN BIT(5)
2266e0832faSShawn Lin #define V3_LB_CFG_LB_PARK_EN BIT(4)
2276e0832faSShawn Lin #define V3_LB_CFG_LB_FBB_DIS BIT(2)
2286e0832faSShawn Lin
2296e0832faSShawn Lin /* ARM Integrator-specific extended control registers */
2306e0832faSShawn Lin #define INTEGRATOR_SC_PCI_OFFSET 0x18
2316e0832faSShawn Lin #define INTEGRATOR_SC_PCI_ENABLE BIT(0)
2326e0832faSShawn Lin #define INTEGRATOR_SC_PCI_INTCLR BIT(1)
2336e0832faSShawn Lin #define INTEGRATOR_SC_LBFADDR_OFFSET 0x20
2346e0832faSShawn Lin #define INTEGRATOR_SC_LBFCODE_OFFSET 0x24
2356e0832faSShawn Lin
2366e0832faSShawn Lin struct v3_pci {
2376e0832faSShawn Lin struct device *dev;
2386e0832faSShawn Lin void __iomem *base;
2396e0832faSShawn Lin void __iomem *config_base;
2406e0832faSShawn Lin u32 config_mem;
2416e0832faSShawn Lin u32 non_pre_mem;
2426e0832faSShawn Lin u32 pre_mem;
2436e0832faSShawn Lin phys_addr_t non_pre_bus_addr;
2446e0832faSShawn Lin phys_addr_t pre_bus_addr;
2456e0832faSShawn Lin struct regmap *map;
2466e0832faSShawn Lin };
2476e0832faSShawn Lin
2486e0832faSShawn Lin /*
2496e0832faSShawn Lin * The V3 PCI interface chip in Integrator provides several windows from
2506e0832faSShawn Lin * local bus memory into the PCI memory areas. Unfortunately, there
2516e0832faSShawn Lin * are not really enough windows for our usage, therefore we reuse
2526e0832faSShawn Lin * one of the windows for access to PCI configuration space. On the
2536e0832faSShawn Lin * Integrator/AP, the memory map is as follows:
2546e0832faSShawn Lin *
2556e0832faSShawn Lin * Local Bus Memory Usage
2566e0832faSShawn Lin *
2576e0832faSShawn Lin * 40000000 - 4FFFFFFF PCI memory. 256M non-prefetchable
2586e0832faSShawn Lin * 50000000 - 5FFFFFFF PCI memory. 256M prefetchable
2596e0832faSShawn Lin * 60000000 - 60FFFFFF PCI IO. 16M
2606e0832faSShawn Lin * 61000000 - 61FFFFFF PCI Configuration. 16M
2616e0832faSShawn Lin *
2626e0832faSShawn Lin * There are three V3 windows, each described by a pair of V3 registers.
2636e0832faSShawn Lin * These are LB_BASE0/LB_MAP0, LB_BASE1/LB_MAP1 and LB_BASE2/LB_MAP2.
2646e0832faSShawn Lin * Base0 and Base1 can be used for any type of PCI memory access. Base2
2656e0832faSShawn Lin * can be used either for PCI I/O or for I20 accesses. By default, uHAL
2666e0832faSShawn Lin * uses this only for PCI IO space.
2676e0832faSShawn Lin *
2686e0832faSShawn Lin * Normally these spaces are mapped using the following base registers:
2696e0832faSShawn Lin *
2706e0832faSShawn Lin * Usage Local Bus Memory Base/Map registers used
2716e0832faSShawn Lin *
2726e0832faSShawn Lin * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0
2736e0832faSShawn Lin * Mem 50000000 - 5FFFFFFF LB_BASE1/LB_MAP1
2746e0832faSShawn Lin * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2
2756e0832faSShawn Lin * Cfg 61000000 - 61FFFFFF
2766e0832faSShawn Lin *
2776e0832faSShawn Lin * This means that I20 and PCI configuration space accesses will fail.
2786e0832faSShawn Lin * When PCI configuration accesses are needed (via the uHAL PCI
2796e0832faSShawn Lin * configuration space primitives) we must remap the spaces as follows:
2806e0832faSShawn Lin *
2816e0832faSShawn Lin * Usage Local Bus Memory Base/Map registers used
2826e0832faSShawn Lin *
2836e0832faSShawn Lin * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0
2846e0832faSShawn Lin * Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0
2856e0832faSShawn Lin * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2
2866e0832faSShawn Lin * Cfg 61000000 - 61FFFFFF LB_BASE1/LB_MAP1
2876e0832faSShawn Lin *
2886e0832faSShawn Lin * To make this work, the code depends on overlapping windows working.
2896e0832faSShawn Lin * The V3 chip translates an address by checking its range within
2906e0832faSShawn Lin * each of the BASE/MAP pairs in turn (in ascending register number
2916e0832faSShawn Lin * order). It will use the first matching pair. So, for example,
2926e0832faSShawn Lin * if the same address is mapped by both LB_BASE0/LB_MAP0 and
2936e0832faSShawn Lin * LB_BASE1/LB_MAP1, the V3 will use the translation from
2946e0832faSShawn Lin * LB_BASE0/LB_MAP0.
2956e0832faSShawn Lin *
2966e0832faSShawn Lin * To allow PCI Configuration space access, the code enlarges the
2976e0832faSShawn Lin * window mapped by LB_BASE0/LB_MAP0 from 256M to 512M. This occludes
2986e0832faSShawn Lin * the windows currently mapped by LB_BASE1/LB_MAP1 so that it can
2996e0832faSShawn Lin * be remapped for use by configuration cycles.
3006e0832faSShawn Lin *
3016e0832faSShawn Lin * At the end of the PCI Configuration space accesses,
3026e0832faSShawn Lin * LB_BASE1/LB_MAP1 is reset to map PCI Memory. Finally the window
3036e0832faSShawn Lin * mapped by LB_BASE0/LB_MAP0 is reduced in size from 512M to 256M to
3046e0832faSShawn Lin * reveal the now restored LB_BASE1/LB_MAP1 window.
3056e0832faSShawn Lin *
3066e0832faSShawn Lin * NOTE: We do not set up I2O mapping. I suspect that this is only
3076e0832faSShawn Lin * for an intelligent (target) device. Using I2O disables most of
3086e0832faSShawn Lin * the mappings into PCI memory.
3096e0832faSShawn Lin */
v3_map_bus(struct pci_bus * bus,unsigned int devfn,int offset)3106e0832faSShawn Lin static void __iomem *v3_map_bus(struct pci_bus *bus,
3116e0832faSShawn Lin unsigned int devfn, int offset)
3126e0832faSShawn Lin {
3136e0832faSShawn Lin struct v3_pci *v3 = bus->sysdata;
3146e0832faSShawn Lin unsigned int address, mapaddress, busnr;
3156e0832faSShawn Lin
3166e0832faSShawn Lin busnr = bus->number;
3176e0832faSShawn Lin if (busnr == 0) {
3186e0832faSShawn Lin int slot = PCI_SLOT(devfn);
3196e0832faSShawn Lin
3206e0832faSShawn Lin /*
3216e0832faSShawn Lin * local bus segment so need a type 0 config cycle
3226e0832faSShawn Lin *
3236e0832faSShawn Lin * build the PCI configuration "address" with one-hot in
3246e0832faSShawn Lin * A31-A11
3256e0832faSShawn Lin *
3266e0832faSShawn Lin * mapaddress:
3276e0832faSShawn Lin * 3:1 = config cycle (101)
3286e0832faSShawn Lin * 0 = PCI A1 & A0 are 0 (0)
3296e0832faSShawn Lin */
3306e0832faSShawn Lin address = PCI_FUNC(devfn) << 8;
3316e0832faSShawn Lin mapaddress = V3_LB_MAP_TYPE_CONFIG;
3326e0832faSShawn Lin
3336e0832faSShawn Lin if (slot > 12)
3346e0832faSShawn Lin /*
3356e0832faSShawn Lin * high order bits are handled by the MAP register
3366e0832faSShawn Lin */
3376e0832faSShawn Lin mapaddress |= BIT(slot - 5);
3386e0832faSShawn Lin else
3396e0832faSShawn Lin /*
3406e0832faSShawn Lin * low order bits handled directly in the address
3416e0832faSShawn Lin */
3426e0832faSShawn Lin address |= BIT(slot + 11);
3436e0832faSShawn Lin } else {
3446e0832faSShawn Lin /*
3456e0832faSShawn Lin * not the local bus segment so need a type 1 config cycle
3466e0832faSShawn Lin *
3476e0832faSShawn Lin * address:
3486e0832faSShawn Lin * 23:16 = bus number
3496e0832faSShawn Lin * 15:11 = slot number (7:3 of devfn)
3506e0832faSShawn Lin * 10:8 = func number (2:0 of devfn)
3516e0832faSShawn Lin *
3526e0832faSShawn Lin * mapaddress:
3536e0832faSShawn Lin * 3:1 = config cycle (101)
3546e0832faSShawn Lin * 0 = PCI A1 & A0 from host bus (1)
3556e0832faSShawn Lin */
3566e0832faSShawn Lin mapaddress = V3_LB_MAP_TYPE_CONFIG | V3_LB_MAP_AD_LOW_EN;
3576e0832faSShawn Lin address = (busnr << 16) | (devfn << 8);
3586e0832faSShawn Lin }
3596e0832faSShawn Lin
3606e0832faSShawn Lin /*
3616e0832faSShawn Lin * Set up base0 to see all 512Mbytes of memory space (not
3626e0832faSShawn Lin * prefetchable), this frees up base1 for re-use by
3636e0832faSShawn Lin * configuration memory
3646e0832faSShawn Lin */
3656e0832faSShawn Lin writel(v3_addr_to_lb_base(v3->non_pre_mem) |
3666e0832faSShawn Lin V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE,
3676e0832faSShawn Lin v3->base + V3_LB_BASE0);
3686e0832faSShawn Lin
3696e0832faSShawn Lin /*
3706e0832faSShawn Lin * Set up base1/map1 to point into configuration space.
3716e0832faSShawn Lin * The config mem is always 16MB.
3726e0832faSShawn Lin */
3736e0832faSShawn Lin writel(v3_addr_to_lb_base(v3->config_mem) |
3746e0832faSShawn Lin V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE,
3756e0832faSShawn Lin v3->base + V3_LB_BASE1);
3766e0832faSShawn Lin writew(mapaddress, v3->base + V3_LB_MAP1);
3776e0832faSShawn Lin
3786e0832faSShawn Lin return v3->config_base + address + offset;
3796e0832faSShawn Lin }
3806e0832faSShawn Lin
v3_unmap_bus(struct v3_pci * v3)3816e0832faSShawn Lin static void v3_unmap_bus(struct v3_pci *v3)
3826e0832faSShawn Lin {
3836e0832faSShawn Lin /*
3846e0832faSShawn Lin * Reassign base1 for use by prefetchable PCI memory
3856e0832faSShawn Lin */
3866e0832faSShawn Lin writel(v3_addr_to_lb_base(v3->pre_mem) |
3876e0832faSShawn Lin V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
3886e0832faSShawn Lin V3_LB_BASE_ENABLE,
3896e0832faSShawn Lin v3->base + V3_LB_BASE1);
3906e0832faSShawn Lin writew(v3_addr_to_lb_map(v3->pre_bus_addr) |
3916e0832faSShawn Lin V3_LB_MAP_TYPE_MEM, /* was V3_LB_MAP_TYPE_MEM_MULTIPLE */
3926e0832faSShawn Lin v3->base + V3_LB_MAP1);
3936e0832faSShawn Lin
3946e0832faSShawn Lin /*
3956e0832faSShawn Lin * And shrink base0 back to a 256M window (NOTE: MAP0 already correct)
3966e0832faSShawn Lin */
3976e0832faSShawn Lin writel(v3_addr_to_lb_base(v3->non_pre_mem) |
3986e0832faSShawn Lin V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE,
3996e0832faSShawn Lin v3->base + V3_LB_BASE0);
4006e0832faSShawn Lin }
4016e0832faSShawn Lin
v3_pci_read_config(struct pci_bus * bus,unsigned int fn,int config,int size,u32 * value)4026e0832faSShawn Lin static int v3_pci_read_config(struct pci_bus *bus, unsigned int fn,
4036e0832faSShawn Lin int config, int size, u32 *value)
4046e0832faSShawn Lin {
4056e0832faSShawn Lin struct v3_pci *v3 = bus->sysdata;
4066e0832faSShawn Lin int ret;
4076e0832faSShawn Lin
4086e0832faSShawn Lin dev_dbg(&bus->dev,
4096e0832faSShawn Lin "[read] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",
4106e0832faSShawn Lin PCI_SLOT(fn), PCI_FUNC(fn), config, size, *value);
4116e0832faSShawn Lin ret = pci_generic_config_read(bus, fn, config, size, value);
4126e0832faSShawn Lin v3_unmap_bus(v3);
4136e0832faSShawn Lin return ret;
4146e0832faSShawn Lin }
4156e0832faSShawn Lin
v3_pci_write_config(struct pci_bus * bus,unsigned int fn,int config,int size,u32 value)4166e0832faSShawn Lin static int v3_pci_write_config(struct pci_bus *bus, unsigned int fn,
4176e0832faSShawn Lin int config, int size, u32 value)
4186e0832faSShawn Lin {
4196e0832faSShawn Lin struct v3_pci *v3 = bus->sysdata;
4206e0832faSShawn Lin int ret;
4216e0832faSShawn Lin
4226e0832faSShawn Lin dev_dbg(&bus->dev,
4236e0832faSShawn Lin "[write] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",
4246e0832faSShawn Lin PCI_SLOT(fn), PCI_FUNC(fn), config, size, value);
4256e0832faSShawn Lin ret = pci_generic_config_write(bus, fn, config, size, value);
4266e0832faSShawn Lin v3_unmap_bus(v3);
4276e0832faSShawn Lin return ret;
4286e0832faSShawn Lin }
4296e0832faSShawn Lin
4306e0832faSShawn Lin static struct pci_ops v3_pci_ops = {
4316e0832faSShawn Lin .map_bus = v3_map_bus,
4326e0832faSShawn Lin .read = v3_pci_read_config,
4336e0832faSShawn Lin .write = v3_pci_write_config,
4346e0832faSShawn Lin };
4356e0832faSShawn Lin
v3_irq(int irq,void * data)4366e0832faSShawn Lin static irqreturn_t v3_irq(int irq, void *data)
4376e0832faSShawn Lin {
4386e0832faSShawn Lin struct v3_pci *v3 = data;
4396e0832faSShawn Lin struct device *dev = v3->dev;
4406e0832faSShawn Lin u32 status;
4416e0832faSShawn Lin
4426e0832faSShawn Lin status = readw(v3->base + V3_PCI_STAT);
4436e0832faSShawn Lin if (status & V3_PCI_STAT_PAR_ERR)
4446e0832faSShawn Lin dev_err(dev, "parity error interrupt\n");
4456e0832faSShawn Lin if (status & V3_PCI_STAT_SYS_ERR)
4466e0832faSShawn Lin dev_err(dev, "system error interrupt\n");
4476e0832faSShawn Lin if (status & V3_PCI_STAT_M_ABORT_ERR)
4486e0832faSShawn Lin dev_err(dev, "master abort error interrupt\n");
4496e0832faSShawn Lin if (status & V3_PCI_STAT_T_ABORT_ERR)
4506e0832faSShawn Lin dev_err(dev, "target abort error interrupt\n");
4516e0832faSShawn Lin writew(status, v3->base + V3_PCI_STAT);
4526e0832faSShawn Lin
4536e0832faSShawn Lin status = readb(v3->base + V3_LB_ISTAT);
4546e0832faSShawn Lin if (status & V3_LB_ISTAT_MAILBOX)
4556e0832faSShawn Lin dev_info(dev, "PCI mailbox interrupt\n");
4566e0832faSShawn Lin if (status & V3_LB_ISTAT_PCI_RD)
4576e0832faSShawn Lin dev_err(dev, "PCI target LB->PCI READ abort interrupt\n");
4586e0832faSShawn Lin if (status & V3_LB_ISTAT_PCI_WR)
4596e0832faSShawn Lin dev_err(dev, "PCI target LB->PCI WRITE abort interrupt\n");
4606e0832faSShawn Lin if (status & V3_LB_ISTAT_PCI_INT)
4616e0832faSShawn Lin dev_info(dev, "PCI pin interrupt\n");
4626e0832faSShawn Lin if (status & V3_LB_ISTAT_PCI_PERR)
4636e0832faSShawn Lin dev_err(dev, "PCI parity error interrupt\n");
4646e0832faSShawn Lin if (status & V3_LB_ISTAT_I2O_QWR)
4656e0832faSShawn Lin dev_info(dev, "I2O inbound post queue interrupt\n");
4666e0832faSShawn Lin if (status & V3_LB_ISTAT_DMA1)
4676e0832faSShawn Lin dev_info(dev, "DMA channel 1 interrupt\n");
4686e0832faSShawn Lin if (status & V3_LB_ISTAT_DMA0)
4696e0832faSShawn Lin dev_info(dev, "DMA channel 0 interrupt\n");
4706e0832faSShawn Lin /* Clear all possible interrupts on the local bus */
4716e0832faSShawn Lin writeb(0, v3->base + V3_LB_ISTAT);
4726e0832faSShawn Lin if (v3->map)
4736e0832faSShawn Lin regmap_write(v3->map, INTEGRATOR_SC_PCI_OFFSET,
4746e0832faSShawn Lin INTEGRATOR_SC_PCI_ENABLE |
4756e0832faSShawn Lin INTEGRATOR_SC_PCI_INTCLR);
4766e0832faSShawn Lin
4776e0832faSShawn Lin return IRQ_HANDLED;
4786e0832faSShawn Lin }
4796e0832faSShawn Lin
v3_integrator_init(struct v3_pci * v3)4806e0832faSShawn Lin static int v3_integrator_init(struct v3_pci *v3)
4816e0832faSShawn Lin {
4826e0832faSShawn Lin unsigned int val;
4836e0832faSShawn Lin
4846e0832faSShawn Lin v3->map =
4856e0832faSShawn Lin syscon_regmap_lookup_by_compatible("arm,integrator-ap-syscon");
4866e0832faSShawn Lin if (IS_ERR(v3->map)) {
4876e0832faSShawn Lin dev_err(v3->dev, "no syscon\n");
4886e0832faSShawn Lin return -ENODEV;
4896e0832faSShawn Lin }
4906e0832faSShawn Lin
4916e0832faSShawn Lin regmap_read(v3->map, INTEGRATOR_SC_PCI_OFFSET, &val);
4926e0832faSShawn Lin /* Take the PCI bridge out of reset, clear IRQs */
4936e0832faSShawn Lin regmap_write(v3->map, INTEGRATOR_SC_PCI_OFFSET,
4946e0832faSShawn Lin INTEGRATOR_SC_PCI_ENABLE |
4956e0832faSShawn Lin INTEGRATOR_SC_PCI_INTCLR);
4966e0832faSShawn Lin
4976e0832faSShawn Lin if (!(val & INTEGRATOR_SC_PCI_ENABLE)) {
4986e0832faSShawn Lin /* If we were in reset we need to sleep a bit */
4996e0832faSShawn Lin msleep(230);
5006e0832faSShawn Lin
5016e0832faSShawn Lin /* Set the physical base for the controller itself */
5026e0832faSShawn Lin writel(0x6200, v3->base + V3_LB_IO_BASE);
5036e0832faSShawn Lin
5046e0832faSShawn Lin /* Wait for the mailbox to settle after reset */
5056e0832faSShawn Lin do {
5066e0832faSShawn Lin writeb(0xaa, v3->base + V3_MAIL_DATA);
5076e0832faSShawn Lin writeb(0x55, v3->base + V3_MAIL_DATA + 4);
5086e0832faSShawn Lin } while (readb(v3->base + V3_MAIL_DATA) != 0xaa &&
5096e0832faSShawn Lin readb(v3->base + V3_MAIL_DATA) != 0x55);
5106e0832faSShawn Lin }
5116e0832faSShawn Lin
5126e0832faSShawn Lin dev_info(v3->dev, "initialized PCI V3 Integrator/AP integration\n");
5136e0832faSShawn Lin
5146e0832faSShawn Lin return 0;
5156e0832faSShawn Lin }
5166e0832faSShawn Lin
v3_pci_setup_resource(struct v3_pci * v3,struct pci_host_bridge * host,struct resource_entry * win)5176e0832faSShawn Lin static int v3_pci_setup_resource(struct v3_pci *v3,
5186e0832faSShawn Lin struct pci_host_bridge *host,
5196e0832faSShawn Lin struct resource_entry *win)
5206e0832faSShawn Lin {
5216e0832faSShawn Lin struct device *dev = v3->dev;
5226e0832faSShawn Lin struct resource *mem;
5236e0832faSShawn Lin struct resource *io;
5246e0832faSShawn Lin
5256e0832faSShawn Lin switch (resource_type(win->res)) {
5266e0832faSShawn Lin case IORESOURCE_IO:
5276e0832faSShawn Lin io = win->res;
528e0aebfe8SRob Herring
5296e0832faSShawn Lin /* Setup window 2 - PCI I/O */
530e0aebfe8SRob Herring writel(v3_addr_to_lb_base2(pci_pio_to_address(io->start)) |
5316e0832faSShawn Lin V3_LB_BASE2_ENABLE,
5326e0832faSShawn Lin v3->base + V3_LB_BASE2);
533e0aebfe8SRob Herring writew(v3_addr_to_lb_map2(io->start - win->offset),
5346e0832faSShawn Lin v3->base + V3_LB_MAP2);
5356e0832faSShawn Lin break;
5366e0832faSShawn Lin case IORESOURCE_MEM:
5376e0832faSShawn Lin mem = win->res;
5386e0832faSShawn Lin if (mem->flags & IORESOURCE_PREFETCH) {
5396e0832faSShawn Lin mem->name = "V3 PCI PRE-MEM";
5406e0832faSShawn Lin v3->pre_mem = mem->start;
5416e0832faSShawn Lin v3->pre_bus_addr = mem->start - win->offset;
5426e0832faSShawn Lin dev_dbg(dev, "PREFETCHABLE MEM window %pR, bus addr %pap\n",
5436e0832faSShawn Lin mem, &v3->pre_bus_addr);
5446e0832faSShawn Lin if (resource_size(mem) != SZ_256M) {
5456e0832faSShawn Lin dev_err(dev, "prefetchable memory range is not 256MB\n");
5466e0832faSShawn Lin return -EINVAL;
5476e0832faSShawn Lin }
5486e0832faSShawn Lin if (v3->non_pre_mem &&
5496e0832faSShawn Lin (mem->start != v3->non_pre_mem + SZ_256M)) {
5506e0832faSShawn Lin dev_err(dev,
5516e0832faSShawn Lin "prefetchable memory is not adjacent to non-prefetchable memory\n");
5526e0832faSShawn Lin return -EINVAL;
5536e0832faSShawn Lin }
5546e0832faSShawn Lin /* Setup window 1 - PCI prefetchable memory */
5556e0832faSShawn Lin writel(v3_addr_to_lb_base(v3->pre_mem) |
5566e0832faSShawn Lin V3_LB_BASE_ADR_SIZE_256MB |
5576e0832faSShawn Lin V3_LB_BASE_PREFETCH |
5586e0832faSShawn Lin V3_LB_BASE_ENABLE,
5596e0832faSShawn Lin v3->base + V3_LB_BASE1);
5606e0832faSShawn Lin writew(v3_addr_to_lb_map(v3->pre_bus_addr) |
5616e0832faSShawn Lin V3_LB_MAP_TYPE_MEM, /* Was V3_LB_MAP_TYPE_MEM_MULTIPLE */
5626e0832faSShawn Lin v3->base + V3_LB_MAP1);
5636e0832faSShawn Lin } else {
5646e0832faSShawn Lin mem->name = "V3 PCI NON-PRE-MEM";
5656e0832faSShawn Lin v3->non_pre_mem = mem->start;
5666e0832faSShawn Lin v3->non_pre_bus_addr = mem->start - win->offset;
5676e0832faSShawn Lin dev_dbg(dev, "NON-PREFETCHABLE MEM window %pR, bus addr %pap\n",
5686e0832faSShawn Lin mem, &v3->non_pre_bus_addr);
5696e0832faSShawn Lin if (resource_size(mem) != SZ_256M) {
5706e0832faSShawn Lin dev_err(dev,
5716e0832faSShawn Lin "non-prefetchable memory range is not 256MB\n");
5726e0832faSShawn Lin return -EINVAL;
5736e0832faSShawn Lin }
5746e0832faSShawn Lin /* Setup window 0 - PCI non-prefetchable memory */
5756e0832faSShawn Lin writel(v3_addr_to_lb_base(v3->non_pre_mem) |
5766e0832faSShawn Lin V3_LB_BASE_ADR_SIZE_256MB |
5776e0832faSShawn Lin V3_LB_BASE_ENABLE,
5786e0832faSShawn Lin v3->base + V3_LB_BASE0);
5796e0832faSShawn Lin writew(v3_addr_to_lb_map(v3->non_pre_bus_addr) |
5806e0832faSShawn Lin V3_LB_MAP_TYPE_MEM,
5816e0832faSShawn Lin v3->base + V3_LB_MAP0);
5826e0832faSShawn Lin }
5836e0832faSShawn Lin break;
5846e0832faSShawn Lin case IORESOURCE_BUS:
5856e0832faSShawn Lin break;
5866e0832faSShawn Lin default:
5876e0832faSShawn Lin dev_info(dev, "Unknown resource type %lu\n",
5886e0832faSShawn Lin resource_type(win->res));
5896e0832faSShawn Lin break;
5906e0832faSShawn Lin }
5916e0832faSShawn Lin
5926e0832faSShawn Lin return 0;
5936e0832faSShawn Lin }
5946e0832faSShawn Lin
v3_get_dma_range_config(struct v3_pci * v3,struct resource_entry * entry,u32 * pci_base,u32 * pci_map)5956e0832faSShawn Lin static int v3_get_dma_range_config(struct v3_pci *v3,
596070d7d70SRob Herring struct resource_entry *entry,
5976e0832faSShawn Lin u32 *pci_base, u32 *pci_map)
5986e0832faSShawn Lin {
5996e0832faSShawn Lin struct device *dev = v3->dev;
600070d7d70SRob Herring u64 cpu_addr = entry->res->start;
601070d7d70SRob Herring u64 cpu_end = entry->res->end;
602070d7d70SRob Herring u64 pci_end = cpu_end - entry->offset;
603070d7d70SRob Herring u64 pci_addr = entry->res->start - entry->offset;
6046e0832faSShawn Lin u32 val;
6056e0832faSShawn Lin
606070d7d70SRob Herring if (pci_addr & ~V3_PCI_BASE_M_ADR_BASE) {
6076e0832faSShawn Lin dev_err(dev, "illegal range, only PCI bits 31..20 allowed\n");
6086e0832faSShawn Lin return -EINVAL;
6096e0832faSShawn Lin }
610070d7d70SRob Herring val = ((u32)pci_addr) & V3_PCI_BASE_M_ADR_BASE;
6116e0832faSShawn Lin *pci_base = val;
6126e0832faSShawn Lin
613070d7d70SRob Herring if (cpu_addr & ~V3_PCI_MAP_M_MAP_ADR) {
6146e0832faSShawn Lin dev_err(dev, "illegal range, only CPU bits 31..20 allowed\n");
6156e0832faSShawn Lin return -EINVAL;
6166e0832faSShawn Lin }
617070d7d70SRob Herring val = ((u32)cpu_addr) & V3_PCI_MAP_M_MAP_ADR;
6186e0832faSShawn Lin
619070d7d70SRob Herring switch (resource_size(entry->res)) {
6206e0832faSShawn Lin case SZ_1M:
6216e0832faSShawn Lin val |= V3_LB_BASE_ADR_SIZE_1MB;
6226e0832faSShawn Lin break;
6236e0832faSShawn Lin case SZ_2M:
6246e0832faSShawn Lin val |= V3_LB_BASE_ADR_SIZE_2MB;
6256e0832faSShawn Lin break;
6266e0832faSShawn Lin case SZ_4M:
6276e0832faSShawn Lin val |= V3_LB_BASE_ADR_SIZE_4MB;
6286e0832faSShawn Lin break;
6296e0832faSShawn Lin case SZ_8M:
6306e0832faSShawn Lin val |= V3_LB_BASE_ADR_SIZE_8MB;
6316e0832faSShawn Lin break;
6326e0832faSShawn Lin case SZ_16M:
6336e0832faSShawn Lin val |= V3_LB_BASE_ADR_SIZE_16MB;
6346e0832faSShawn Lin break;
6356e0832faSShawn Lin case SZ_32M:
6366e0832faSShawn Lin val |= V3_LB_BASE_ADR_SIZE_32MB;
6376e0832faSShawn Lin break;
6386e0832faSShawn Lin case SZ_64M:
6396e0832faSShawn Lin val |= V3_LB_BASE_ADR_SIZE_64MB;
6406e0832faSShawn Lin break;
6416e0832faSShawn Lin case SZ_128M:
6426e0832faSShawn Lin val |= V3_LB_BASE_ADR_SIZE_128MB;
6436e0832faSShawn Lin break;
6446e0832faSShawn Lin case SZ_256M:
6456e0832faSShawn Lin val |= V3_LB_BASE_ADR_SIZE_256MB;
6466e0832faSShawn Lin break;
6476e0832faSShawn Lin case SZ_512M:
6486e0832faSShawn Lin val |= V3_LB_BASE_ADR_SIZE_512MB;
6496e0832faSShawn Lin break;
6506e0832faSShawn Lin case SZ_1G:
6516e0832faSShawn Lin val |= V3_LB_BASE_ADR_SIZE_1GB;
6526e0832faSShawn Lin break;
6536e0832faSShawn Lin case SZ_2G:
6546e0832faSShawn Lin val |= V3_LB_BASE_ADR_SIZE_2GB;
6556e0832faSShawn Lin break;
6566e0832faSShawn Lin default:
6576e0832faSShawn Lin dev_err(v3->dev, "illegal dma memory chunk size\n");
6586e0832faSShawn Lin return -EINVAL;
6596e0832faSShawn Lin }
6606e0832faSShawn Lin val |= V3_PCI_MAP_M_REG_EN | V3_PCI_MAP_M_ENABLE;
6616e0832faSShawn Lin *pci_map = val;
6626e0832faSShawn Lin
6636e0832faSShawn Lin dev_dbg(dev,
6646e0832faSShawn Lin "DMA MEM CPU: 0x%016llx -> 0x%016llx => "
6656e0832faSShawn Lin "PCI: 0x%016llx -> 0x%016llx base %08x map %08x\n",
666070d7d70SRob Herring cpu_addr, cpu_end,
667070d7d70SRob Herring pci_addr, pci_end,
6686e0832faSShawn Lin *pci_base, *pci_map);
6696e0832faSShawn Lin
6706e0832faSShawn Lin return 0;
6716e0832faSShawn Lin }
6726e0832faSShawn Lin
v3_pci_parse_map_dma_ranges(struct v3_pci * v3,struct device_node * np)6736e0832faSShawn Lin static int v3_pci_parse_map_dma_ranges(struct v3_pci *v3,
6746e0832faSShawn Lin struct device_node *np)
6756e0832faSShawn Lin {
676070d7d70SRob Herring struct pci_host_bridge *bridge = pci_host_bridge_from_priv(v3);
6776e0832faSShawn Lin struct device *dev = v3->dev;
678070d7d70SRob Herring struct resource_entry *entry;
6796e0832faSShawn Lin int i = 0;
6806e0832faSShawn Lin
681070d7d70SRob Herring resource_list_for_each_entry(entry, &bridge->dma_ranges) {
6826e0832faSShawn Lin int ret;
6836e0832faSShawn Lin u32 pci_base, pci_map;
6846e0832faSShawn Lin
685070d7d70SRob Herring ret = v3_get_dma_range_config(v3, entry, &pci_base, &pci_map);
6866e0832faSShawn Lin if (ret)
6876e0832faSShawn Lin return ret;
6886e0832faSShawn Lin
6896e0832faSShawn Lin if (i == 0) {
6906e0832faSShawn Lin writel(pci_base, v3->base + V3_PCI_BASE0);
6916e0832faSShawn Lin writel(pci_map, v3->base + V3_PCI_MAP0);
6926e0832faSShawn Lin } else if (i == 1) {
6936e0832faSShawn Lin writel(pci_base, v3->base + V3_PCI_BASE1);
6946e0832faSShawn Lin writel(pci_map, v3->base + V3_PCI_MAP1);
6956e0832faSShawn Lin } else {
6966e0832faSShawn Lin dev_err(dev, "too many ranges, only two supported\n");
6976e0832faSShawn Lin dev_err(dev, "range %d ignored\n", i);
6986e0832faSShawn Lin }
6996e0832faSShawn Lin i++;
7006e0832faSShawn Lin }
7016e0832faSShawn Lin return 0;
7026e0832faSShawn Lin }
7036e0832faSShawn Lin
v3_pci_probe(struct platform_device * pdev)7046e0832faSShawn Lin static int v3_pci_probe(struct platform_device *pdev)
7056e0832faSShawn Lin {
7066e0832faSShawn Lin struct device *dev = &pdev->dev;
7076e0832faSShawn Lin struct device_node *np = dev->of_node;
7086e0832faSShawn Lin struct resource *regs;
7096e0832faSShawn Lin struct resource_entry *win;
7106e0832faSShawn Lin struct v3_pci *v3;
7116e0832faSShawn Lin struct pci_host_bridge *host;
7126e0832faSShawn Lin struct clk *clk;
7136e0832faSShawn Lin u16 val;
7146e0832faSShawn Lin int irq;
7156e0832faSShawn Lin int ret;
7166e0832faSShawn Lin
717bca71898SChristophe JAILLET host = devm_pci_alloc_host_bridge(dev, sizeof(*v3));
7186e0832faSShawn Lin if (!host)
7196e0832faSShawn Lin return -ENOMEM;
7206e0832faSShawn Lin
7216e0832faSShawn Lin host->ops = &v3_pci_ops;
7226e0832faSShawn Lin v3 = pci_host_bridge_priv(host);
7236e0832faSShawn Lin host->sysdata = v3;
7246e0832faSShawn Lin v3->dev = dev;
7256e0832faSShawn Lin
7266e0832faSShawn Lin /* Get and enable host clock */
7276e0832faSShawn Lin clk = devm_clk_get(dev, NULL);
7286e0832faSShawn Lin if (IS_ERR(clk)) {
7296e0832faSShawn Lin dev_err(dev, "clock not found\n");
7306e0832faSShawn Lin return PTR_ERR(clk);
7316e0832faSShawn Lin }
7326e0832faSShawn Lin ret = clk_prepare_enable(clk);
7336e0832faSShawn Lin if (ret) {
7346e0832faSShawn Lin dev_err(dev, "unable to enable clock\n");
7356e0832faSShawn Lin return ret;
7366e0832faSShawn Lin }
7376e0832faSShawn Lin
7386e0832faSShawn Lin v3->base = devm_platform_get_and_ioremap_resource(pdev, 0, ®s);
7396e0832faSShawn Lin if (IS_ERR(v3->base))
7406e0832faSShawn Lin return PTR_ERR(v3->base);
7416e0832faSShawn Lin /*
7426e0832faSShawn Lin * The hardware has a register with the physical base address
7436e0832faSShawn Lin * of the V3 controller itself, verify that this is the same
7446e0832faSShawn Lin * as the physical memory we've remapped it from.
7456e0832faSShawn Lin */
7466e0832faSShawn Lin if (readl(v3->base + V3_LB_IO_BASE) != (regs->start >> 16))
7476e0832faSShawn Lin dev_err(dev, "V3_LB_IO_BASE = %08x but device is @%pR\n",
7486e0832faSShawn Lin readl(v3->base + V3_LB_IO_BASE), regs);
7496e0832faSShawn Lin
7506e0832faSShawn Lin /* Configuration space is 16MB directly mapped */
7516e0832faSShawn Lin regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
7526e0832faSShawn Lin if (resource_size(regs) != SZ_16M) {
7536e0832faSShawn Lin dev_err(dev, "config mem is not 16MB!\n");
7546e0832faSShawn Lin return -EINVAL;
7556e0832faSShawn Lin }
7566e0832faSShawn Lin v3->config_mem = regs->start;
7576e0832faSShawn Lin v3->config_base = devm_ioremap_resource(dev, regs);
7586e0832faSShawn Lin if (IS_ERR(v3->config_base))
7596e0832faSShawn Lin return PTR_ERR(v3->config_base);
7606e0832faSShawn Lin
7616e0832faSShawn Lin /* Get and request error IRQ resource */
7626e0832faSShawn Lin irq = platform_get_irq(pdev, 0);
7636e0832faSShawn Lin if (irq < 0)
764caecb05cSKrzysztof Wilczyński return irq;
7650584bff0SAman Sharma
766caecb05cSKrzysztof Wilczyński ret = devm_request_irq(dev, irq, v3_irq, 0,
7676e0832faSShawn Lin "PCIv3 error", v3);
7686e0832faSShawn Lin if (ret < 0) {
7696e0832faSShawn Lin dev_err(dev,
7706e0832faSShawn Lin "unable to request PCIv3 error IRQ %d (%d)\n",
7716e0832faSShawn Lin irq, ret);
7726e0832faSShawn Lin return ret;
7736e0832faSShawn Lin }
7746e0832faSShawn Lin
7756e0832faSShawn Lin /*
7766e0832faSShawn Lin * Unlock V3 registers, but only if they were previously locked.
7776e0832faSShawn Lin */
7786e0832faSShawn Lin if (readw(v3->base + V3_SYSTEM) & V3_SYSTEM_M_LOCK)
7796e0832faSShawn Lin writew(V3_SYSTEM_UNLOCK, v3->base + V3_SYSTEM);
7806e0832faSShawn Lin
7816e0832faSShawn Lin /* Disable all slave access while we set up the windows */
7826e0832faSShawn Lin val = readw(v3->base + V3_PCI_CMD);
7836e0832faSShawn Lin val &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
7846e0832faSShawn Lin writew(val, v3->base + V3_PCI_CMD);
7856e0832faSShawn Lin
7866e0832faSShawn Lin /* Put the PCI bus into reset */
7876e0832faSShawn Lin val = readw(v3->base + V3_SYSTEM);
7886e0832faSShawn Lin val &= ~V3_SYSTEM_M_RST_OUT;
7896e0832faSShawn Lin writew(val, v3->base + V3_SYSTEM);
7906e0832faSShawn Lin
7916e0832faSShawn Lin /* Retry until we're ready */
7926e0832faSShawn Lin val = readw(v3->base + V3_PCI_CFG);
7936e0832faSShawn Lin val |= V3_PCI_CFG_M_RETRY_EN;
7946e0832faSShawn Lin writew(val, v3->base + V3_PCI_CFG);
7956e0832faSShawn Lin
7966e0832faSShawn Lin /* Set up the local bus protocol */
7976e0832faSShawn Lin val = readw(v3->base + V3_LB_CFG);
7986e0832faSShawn Lin val |= V3_LB_CFG_LB_BE_IMODE; /* Byte enable input */
7996e0832faSShawn Lin val |= V3_LB_CFG_LB_BE_OMODE; /* Byte enable output */
8006e0832faSShawn Lin val &= ~V3_LB_CFG_LB_ENDIAN; /* Little endian */
8016e0832faSShawn Lin val &= ~V3_LB_CFG_LB_PPC_RDY; /* TODO: when using on PPC403Gx, set to 1 */
8026e0832faSShawn Lin writew(val, v3->base + V3_LB_CFG);
8036e0832faSShawn Lin
8046e0832faSShawn Lin /* Enable the PCI bus master */
8056e0832faSShawn Lin val = readw(v3->base + V3_PCI_CMD);
8066e0832faSShawn Lin val |= PCI_COMMAND_MASTER;
8076e0832faSShawn Lin writew(val, v3->base + V3_PCI_CMD);
8086e0832faSShawn Lin
8096e0832faSShawn Lin /* Get the I/O and memory ranges from DT */
8106e0832faSShawn Lin resource_list_for_each_entry(win, &host->windows) {
811e0aebfe8SRob Herring ret = v3_pci_setup_resource(v3, host, win);
812e0aebfe8SRob Herring if (ret) {
8136e0832faSShawn Lin dev_err(dev, "error setting up resources\n");
8146e0832faSShawn Lin return ret;
8156e0832faSShawn Lin }
8166e0832faSShawn Lin }
8176e0832faSShawn Lin ret = v3_pci_parse_map_dma_ranges(v3, np);
8186e0832faSShawn Lin if (ret)
8196e0832faSShawn Lin return ret;
8206e0832faSShawn Lin
8216e0832faSShawn Lin /*
8226e0832faSShawn Lin * Disable PCI to host IO cycles, enable I/O buffers @3.3V,
8236e0832faSShawn Lin * set AD_LOW0 to 1 if one of the LB_MAP registers choose
8246e0832faSShawn Lin * to use this (should be unused).
8256e0832faSShawn Lin */
8266e0832faSShawn Lin writel(0x00000000, v3->base + V3_PCI_IO_BASE);
8276e0832faSShawn Lin val = V3_PCI_CFG_M_IO_REG_DIS | V3_PCI_CFG_M_IO_DIS |
8286e0832faSShawn Lin V3_PCI_CFG_M_EN3V | V3_PCI_CFG_M_AD_LOW0;
8296e0832faSShawn Lin /*
8306e0832faSShawn Lin * DMA read and write from PCI bus commands types
8316e0832faSShawn Lin */
8326e0832faSShawn Lin val |= V3_PCI_CFG_TYPE_DEFAULT << V3_PCI_CFG_M_RTYPE_SHIFT;
8336e0832faSShawn Lin val |= V3_PCI_CFG_TYPE_DEFAULT << V3_PCI_CFG_M_WTYPE_SHIFT;
8346e0832faSShawn Lin writew(val, v3->base + V3_PCI_CFG);
8356e0832faSShawn Lin
8366e0832faSShawn Lin /*
8376e0832faSShawn Lin * Set the V3 FIFO such that writes have higher priority than
8386e0832faSShawn Lin * reads, and local bus write causes local bus read fifo flush
8396e0832faSShawn Lin * on aperture 1. Same for PCI.
8406e0832faSShawn Lin */
8416e0832faSShawn Lin writew(V3_FIFO_PRIO_LB_RD1_FLUSH_AP1 |
8426e0832faSShawn Lin V3_FIFO_PRIO_LB_RD0_FLUSH_AP1 |
8436e0832faSShawn Lin V3_FIFO_PRIO_PCI_RD1_FLUSH_AP1 |
8446e0832faSShawn Lin V3_FIFO_PRIO_PCI_RD0_FLUSH_AP1,
8456e0832faSShawn Lin v3->base + V3_FIFO_PRIORITY);
8466e0832faSShawn Lin
8476e0832faSShawn Lin
8486e0832faSShawn Lin /*
8496e0832faSShawn Lin * Clear any error interrupts, and enable parity and write error
8506e0832faSShawn Lin * interrupts
8516e0832faSShawn Lin */
8526e0832faSShawn Lin writeb(0, v3->base + V3_LB_ISTAT);
8536e0832faSShawn Lin val = readw(v3->base + V3_LB_CFG);
8546e0832faSShawn Lin val |= V3_LB_CFG_LB_LB_INT;
8556e0832faSShawn Lin writew(val, v3->base + V3_LB_CFG);
8566e0832faSShawn Lin writeb(V3_LB_ISTAT_PCI_WR | V3_LB_ISTAT_PCI_PERR,
8576e0832faSShawn Lin v3->base + V3_LB_IMASK);
8586e0832faSShawn Lin
8596e0832faSShawn Lin /* Special Integrator initialization */
8606e0832faSShawn Lin if (of_device_is_compatible(np, "arm,integrator-ap-pci")) {
8616e0832faSShawn Lin ret = v3_integrator_init(v3);
8626e0832faSShawn Lin if (ret)
8636e0832faSShawn Lin return ret;
8646e0832faSShawn Lin }
8656e0832faSShawn Lin
8666e0832faSShawn Lin /* Post-init: enable PCI memory and invalidate (master already on) */
8676e0832faSShawn Lin val = readw(v3->base + V3_PCI_CMD);
8686e0832faSShawn Lin val |= PCI_COMMAND_MEMORY | PCI_COMMAND_INVALIDATE;
8696e0832faSShawn Lin writew(val, v3->base + V3_PCI_CMD);
8706e0832faSShawn Lin
8716e0832faSShawn Lin /* Clear pending interrupts */
8726e0832faSShawn Lin writeb(0, v3->base + V3_LB_ISTAT);
8736e0832faSShawn Lin /* Read or write errors and parity errors cause interrupts */
8746e0832faSShawn Lin writeb(V3_LB_ISTAT_PCI_RD | V3_LB_ISTAT_PCI_WR | V3_LB_ISTAT_PCI_PERR,
8756e0832faSShawn Lin v3->base + V3_LB_IMASK);
8766e0832faSShawn Lin
8776e0832faSShawn Lin /* Take the PCI bus out of reset so devices can initialize */
8786e0832faSShawn Lin val = readw(v3->base + V3_SYSTEM);
8796e0832faSShawn Lin val |= V3_SYSTEM_M_RST_OUT;
8806e0832faSShawn Lin writew(val, v3->base + V3_SYSTEM);
8816e0832faSShawn Lin
8826e0832faSShawn Lin /*
8836e0832faSShawn Lin * Re-lock the system register.
8846e0832faSShawn Lin */
8856e0832faSShawn Lin val = readw(v3->base + V3_SYSTEM);
8866e0832faSShawn Lin val |= V3_SYSTEM_M_LOCK;
8876e0832faSShawn Lin writew(val, v3->base + V3_SYSTEM);
8886e0832faSShawn Lin
8896e0832faSShawn Lin return pci_host_probe(host);
890d7169a94SRob Herring }
8916e0832faSShawn Lin
8926e0832faSShawn Lin static const struct of_device_id v3_pci_of_match[] = {
8936e0832faSShawn Lin {
8946e0832faSShawn Lin .compatible = "v3,v360epc-pci",
8956e0832faSShawn Lin },
8966e0832faSShawn Lin {},
8976e0832faSShawn Lin };
8986e0832faSShawn Lin
8996e0832faSShawn Lin static struct platform_driver v3_pci_driver = {
9006e0832faSShawn Lin .driver = {
9016e0832faSShawn Lin .name = "pci-v3-semi",
9026e0832faSShawn Lin .of_match_table = v3_pci_of_match,
9038610e98fSBjorn Helgaas .suppress_bind_attrs = true,
9046e0832faSShawn Lin },
9056e0832faSShawn Lin .probe = v3_pci_probe,
9066e0832faSShawn Lin };
9076e0832faSShawn Lin builtin_platform_driver(v3_pci_driver);
9086e0832faSShawn Lin