14549e789STom Rini// SPDX-License-Identifier: GPL-2.0+ OR X11 244937214SPrabhakar Kushwaha/* 344937214SPrabhakar Kushwaha * Freescale ls2080a SOC common device tree source 444937214SPrabhakar Kushwaha * 544937214SPrabhakar Kushwaha * Copyright 2013-2015 Freescale Semiconductor, Inc. 644937214SPrabhakar Kushwaha */ 744937214SPrabhakar Kushwaha 844937214SPrabhakar Kushwaha/ { 944937214SPrabhakar Kushwaha compatible = "fsl,ls2080a"; 1044937214SPrabhakar Kushwaha interrupt-parent = <&gic>; 1144937214SPrabhakar Kushwaha #address-cells = <2>; 1244937214SPrabhakar Kushwaha #size-cells = <2>; 1344937214SPrabhakar Kushwaha 1444937214SPrabhakar Kushwaha memory@80000000 { 1544937214SPrabhakar Kushwaha device_type = "memory"; 1644937214SPrabhakar Kushwaha reg = <0x00000000 0x80000000 0 0x80000000>; 1744937214SPrabhakar Kushwaha /* DRAM space - 1, size : 2 GB DRAM */ 1844937214SPrabhakar Kushwaha }; 1944937214SPrabhakar Kushwaha 2044937214SPrabhakar Kushwaha gic: interrupt-controller@6000000 { 2144937214SPrabhakar Kushwaha compatible = "arm,gic-v3"; 2244937214SPrabhakar Kushwaha reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 2344937214SPrabhakar Kushwaha <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */ 2444937214SPrabhakar Kushwaha #interrupt-cells = <3>; 2544937214SPrabhakar Kushwaha interrupt-controller; 2644937214SPrabhakar Kushwaha interrupts = <1 9 0x4>; 2744937214SPrabhakar Kushwaha }; 2844937214SPrabhakar Kushwaha 2944937214SPrabhakar Kushwaha timer { 3044937214SPrabhakar Kushwaha compatible = "arm,armv8-timer"; 3144937214SPrabhakar Kushwaha interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ 3244937214SPrabhakar Kushwaha <1 14 0x8>, /* Physical Non-Secure PPI, active-low */ 3344937214SPrabhakar Kushwaha <1 11 0x8>, /* Virtual PPI, active-low */ 3444937214SPrabhakar Kushwaha <1 10 0x8>; /* Hypervisor PPI, active-low */ 3544937214SPrabhakar Kushwaha }; 3644937214SPrabhakar Kushwaha 3744937214SPrabhakar Kushwaha serial0: serial@21c0500 { 3844937214SPrabhakar Kushwaha device_type = "serial"; 3944937214SPrabhakar Kushwaha compatible = "fsl,ns16550", "ns16550a"; 4044937214SPrabhakar Kushwaha reg = <0x0 0x21c0500 0x0 0x100>; 4144937214SPrabhakar Kushwaha clock-frequency = <0>; /* Updated by bootloader */ 4244937214SPrabhakar Kushwaha interrupts = <0 32 0x1>; /* edge triggered */ 4344937214SPrabhakar Kushwaha }; 4444937214SPrabhakar Kushwaha 4544937214SPrabhakar Kushwaha serial1: serial@21c0600 { 4644937214SPrabhakar Kushwaha device_type = "serial"; 4744937214SPrabhakar Kushwaha compatible = "fsl,ns16550", "ns16550a"; 4844937214SPrabhakar Kushwaha reg = <0x0 0x21c0600 0x0 0x100>; 4944937214SPrabhakar Kushwaha clock-frequency = <0>; /* Updated by bootloader */ 5044937214SPrabhakar Kushwaha interrupts = <0 32 0x1>; /* edge triggered */ 5144937214SPrabhakar Kushwaha }; 5244937214SPrabhakar Kushwaha 5344937214SPrabhakar Kushwaha fsl_mc: fsl-mc@80c000000 { 5444937214SPrabhakar Kushwaha compatible = "fsl,qoriq-mc"; 5544937214SPrabhakar Kushwaha reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ 5644937214SPrabhakar Kushwaha <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ 5744937214SPrabhakar Kushwaha }; 5844937214SPrabhakar Kushwaha 5944937214SPrabhakar Kushwaha dspi: dspi@2100000 { 6044937214SPrabhakar Kushwaha compatible = "fsl,vf610-dspi"; 6144937214SPrabhakar Kushwaha #address-cells = <1>; 6244937214SPrabhakar Kushwaha #size-cells = <0>; 6344937214SPrabhakar Kushwaha reg = <0x0 0x2100000 0x0 0x10000>; 6444937214SPrabhakar Kushwaha interrupts = <0 26 0x4>; /* Level high type */ 6544937214SPrabhakar Kushwaha num-cs = <6>; 6644937214SPrabhakar Kushwaha }; 6795ab851dSYuan Yao 6895ab851dSYuan Yao qspi: quadspi@1550000 { 6995ab851dSYuan Yao compatible = "fsl,vf610-qspi"; 7095ab851dSYuan Yao #address-cells = <1>; 7195ab851dSYuan Yao #size-cells = <0>; 7295ab851dSYuan Yao reg = <0x0 0x20c0000 0x0 0x10000>, 7395ab851dSYuan Yao <0x0 0x20000000 0x0 0x10000000>; 7495ab851dSYuan Yao reg-names = "QuadSPI", "QuadSPI-memory"; 7595ab851dSYuan Yao num-cs = <4>; 7695ab851dSYuan Yao }; 7768ec3888SSriram Dash 7899e0071dSYinbo Zhu esdhc: esdhc@0 { 7999e0071dSYinbo Zhu compatible = "fsl,esdhc"; 8099e0071dSYinbo Zhu reg = <0x0 0x2140000 0x0 0x10000>; 8199e0071dSYinbo Zhu interrupts = <0 28 0x4>; /* Level high type */ 8299e0071dSYinbo Zhu little-endian; 8399e0071dSYinbo Zhu bus-width = <4>; 8499e0071dSYinbo Zhu }; 8599e0071dSYinbo Zhu 8668ec3888SSriram Dash usb0: usb3@3100000 { 8768ec3888SSriram Dash compatible = "fsl,layerscape-dwc3"; 8868ec3888SSriram Dash reg = <0x0 0x3100000 0x0 0x10000>; 8968ec3888SSriram Dash interrupts = <0 80 0x4>; /* Level high type */ 9068ec3888SSriram Dash dr_mode = "host"; 9168ec3888SSriram Dash }; 9268ec3888SSriram Dash 9368ec3888SSriram Dash usb1: usb3@3110000 { 9468ec3888SSriram Dash compatible = "fsl,layerscape-dwc3"; 9568ec3888SSriram Dash reg = <0x0 0x3110000 0x0 0x10000>; 9668ec3888SSriram Dash interrupts = <0 81 0x4>; /* Level high type */ 9768ec3888SSriram Dash dr_mode = "host"; 9868ec3888SSriram Dash }; 9933f61e07SMinghuan Lian 10033f61e07SMinghuan Lian pcie@3400000 { 10133f61e07SMinghuan Lian compatible = "fsl,ls-pcie", "snps,dw-pcie"; 10233f61e07SMinghuan Lian reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */ 10333f61e07SMinghuan Lian 0x00 0x03480000 0x0 0x80000 /* lut registers */ 10433f61e07SMinghuan Lian 0x10 0x00000000 0x0 0x20000>; /* configuration space */ 10533f61e07SMinghuan Lian reg-names = "dbi", "lut", "config"; 10633f61e07SMinghuan Lian #address-cells = <3>; 10733f61e07SMinghuan Lian #size-cells = <2>; 10833f61e07SMinghuan Lian device_type = "pci"; 10933f61e07SMinghuan Lian num-lanes = <4>; 11033f61e07SMinghuan Lian bus-range = <0x0 0xff>; 11133f61e07SMinghuan Lian ranges = <0x81000000 0x0 0x00000000 0x10 0x00020000 0x0 0x00010000 /* downstream I/O */ 11233f61e07SMinghuan Lian 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 11333f61e07SMinghuan Lian }; 11433f61e07SMinghuan Lian 11533f61e07SMinghuan Lian pcie@3500000 { 11633f61e07SMinghuan Lian compatible = "fsl,ls-pcie", "snps,dw-pcie"; 11733f61e07SMinghuan Lian reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */ 11833f61e07SMinghuan Lian 0x00 0x03580000 0x0 0x80000 /* lut registers */ 11933f61e07SMinghuan Lian 0x12 0x00000000 0x0 0x20000>; /* configuration space */ 12033f61e07SMinghuan Lian reg-names = "dbi", "lut", "config"; 12133f61e07SMinghuan Lian #address-cells = <3>; 12233f61e07SMinghuan Lian #size-cells = <2>; 12333f61e07SMinghuan Lian device_type = "pci"; 12433f61e07SMinghuan Lian num-lanes = <4>; 12533f61e07SMinghuan Lian bus-range = <0x0 0xff>; 12633f61e07SMinghuan Lian ranges = <0x81000000 0x0 0x00000000 0x12 0x00020000 0x0 0x00010000 /* downstream I/O */ 12733f61e07SMinghuan Lian 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 12833f61e07SMinghuan Lian }; 12933f61e07SMinghuan Lian 13033f61e07SMinghuan Lian pcie@3600000 { 13133f61e07SMinghuan Lian compatible = "fsl,ls-pcie", "snps,dw-pcie"; 13233f61e07SMinghuan Lian reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */ 13333f61e07SMinghuan Lian 0x00 0x03680000 0x0 0x80000 /* lut registers */ 13433f61e07SMinghuan Lian 0x14 0x00000000 0x0 0x20000>; /* configuration space */ 13533f61e07SMinghuan Lian reg-names = "dbi", "lut", "config"; 13633f61e07SMinghuan Lian #address-cells = <3>; 13733f61e07SMinghuan Lian #size-cells = <2>; 13833f61e07SMinghuan Lian device_type = "pci"; 13933f61e07SMinghuan Lian num-lanes = <8>; 14033f61e07SMinghuan Lian bus-range = <0x0 0xff>; 14133f61e07SMinghuan Lian ranges = <0x81000000 0x0 0x00000000 0x14 0x00020000 0x0 0x00010000 /* downstream I/O */ 14233f61e07SMinghuan Lian 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 14333f61e07SMinghuan Lian }; 14433f61e07SMinghuan Lian 14533f61e07SMinghuan Lian pcie@3700000 { 14633f61e07SMinghuan Lian compatible = "fsl,ls-pcie", "snps,dw-pcie"; 14733f61e07SMinghuan Lian reg = <0x00 0x03700000 0x0 0x80000 /* dbi registers */ 14833f61e07SMinghuan Lian 0x00 0x03780000 0x0 0x80000 /* lut registers */ 14933f61e07SMinghuan Lian 0x16 0x00000000 0x0 0x20000>; /* configuration space */ 15033f61e07SMinghuan Lian reg-names = "dbi", "lut", "config"; 15133f61e07SMinghuan Lian #address-cells = <3>; 15233f61e07SMinghuan Lian #size-cells = <2>; 15333f61e07SMinghuan Lian device_type = "pci"; 15433f61e07SMinghuan Lian num-lanes = <4>; 15533f61e07SMinghuan Lian bus-range = <0x0 0xff>; 15633f61e07SMinghuan Lian ranges = <0x81000000 0x0 0x00000000 0x16 0x00020000 0x0 0x00010000 /* downstream I/O */ 15733f61e07SMinghuan Lian 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 15833f61e07SMinghuan Lian }; 159*8ec42856SPeng Ma 160*8ec42856SPeng Ma sata: sata@3200000 { 161*8ec42856SPeng Ma compatible = "fsl,ls2080a-ahci"; 162*8ec42856SPeng Ma reg = <0x0 0x3200000 0x0 0x10000>; 163*8ec42856SPeng Ma interrupts = <0 133 0x4>; /* Level high type */ 164*8ec42856SPeng Ma status = "disabled"; 165*8ec42856SPeng Ma }; 166*8ec42856SPeng Ma 16744937214SPrabhakar Kushwaha}; 168