|
Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43 |
|
| #
fcf7ff67 |
| 31-Jul-2023 |
Hui Wang <hui.wang@canonical.com> |
arm64: dts: ls1028a: add l1 and l2 cache info
When we ran the stress-ng cache related stressors, we got the log as
below:
ubuntu@ubuntu:~$ stress-ng --l1cache 4
stress-ng: info: [656] defaulting to
arm64: dts: ls1028a: add l1 and l2 cache info
When we ran the stress-ng cache related stressors, we got the log as
below:
ubuntu@ubuntu:~$ stress-ng --l1cache 4
stress-ng: info: [656] defaulting to a 86400 second (1 day, 0.00 secs) run per stressor
stress-ng: info: [656] dispatching hogs: 4 l1cache
stress-ng: info: [657] stress-ng-l1cache: skipping stressor, cannot determine cache level 1 information from kernel
This is because the l1 and l2 cache info is missing in the devicetree,
ls1028a has dual cortex-a72 cores and has 48KB icache, 32KB dcache and
1MB l2 ucache:
- icache is 3-way set associative
- dcache is 2-way set associative
- l2cache is 16-way set associative
- line size are 64bytes
Signed-off-by: Hui Wang <hui.wang@canonical.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
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|
Revision tags: v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3 |
|
| #
c290d09a |
| 21-Apr-2023 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
arm64: dts: freescale: add missing cache properties
As all level 2 and level 3 caches are unified, add required
cache-unified properties to fix warnings like:
fsl-ls2080a-simu.dtb: l2-cache3: 'ca
arm64: dts: freescale: add missing cache properties
As all level 2 and level 3 caches are unified, add required
cache-unified properties to fix warnings like:
fsl-ls2080a-simu.dtb: l2-cache3: 'cache-unified' is a required property
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
|
|
Revision tags: v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11 |
|
| #
04b09f6e |
| 08-Feb-2023 |
Rob Herring <robh@kernel.org> |
arm64: dts: layerscape: Fix GICv3 ITS node names
The GICv3 ITS is an MSI controller, therefore its node name should be
'msi-controller'.
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by:
arm64: dts: layerscape: Fix GICv3 ITS node names
The GICv3 ITS is an MSI controller, therefore its node name should be
'msi-controller'.
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
|
|
Revision tags: v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14 |
|
| #
8720913f |
| 15-Dec-2022 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
arm64: dts: ls1028a: declare cache-coherent page table walk feature for IOMMU
The SMMUv2 driver for MMU-500 reads the ARM_SMMU_GR0_ID0 register at
probe time and tries to determine based on the CTTW
arm64: dts: ls1028a: declare cache-coherent page table walk feature for IOMMU
The SMMUv2 driver for MMU-500 reads the ARM_SMMU_GR0_ID0 register at
probe time and tries to determine based on the CTTW (Coherent
Translation Table Walk) bit whether this feature is supported.
Unfortunately, it looks like the SMMU integration in the NXP LS1028A has
wrongly tied the cfg_cttw signal to 0, even though the SoC documentation
specifies that "The SMMU supports cache coherency for page table walks
and DVM transactions for page table cache maintenance operations."
Device tree provides the option of overriding the ID register via the
dma-coherent property since commit bae2c2d421cd ("iommu/arm-smmu: Sort
out coherency"), and that's what we do here.
Telling struct io_pgtable_cfg that the SMMU page table walks are
coherent with the CPU caches brings performance benefits, because it
avoids certain operations such as __arm_lpae_sync_pte() for PTE updates.
Link: https://lore.kernel.org/linux-iommu/3f3112e4-65ff-105d-8cd7-60495ec9054a@arm.com/
Suggested-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
|
|
Revision tags: v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79, v6.0.8, v5.15.78 |
|
| #
3b450831 |
| 07-Nov-2022 |
Pierre Gondois <pierre.gondois@arm.com> |
arm64: dts: Update cache properties for freescale
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and S
arm64: dts: Update cache properties for freescale
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Chester Lin <clin@suse.com>
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
|
|
Revision tags: v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4, v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71, v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65 |
|
| #
d72e3b4e |
| 31-Aug-2022 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
arm64: dts: ls1028a: mark enetc port 3 as a DSA master too
The LS1028A switch has 2 internal links to the ENETC controller.
With DSA's ability to support multiple CPU ports, we should mark both
ENE
arm64: dts: ls1028a: mark enetc port 3 as a DSA master too
The LS1028A switch has 2 internal links to the ENETC controller.
With DSA's ability to support multiple CPU ports, we should mark both
ENETC ports as DSA masters.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Michael Walle <michael@walle.cc>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
|
| #
b340ee02 |
| 31-Aug-2022 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
arm64: dts: ls1028a: move DSA CPU port property to the common SoC dtsi
Since the CPU port 4 of the switch is hardwired inside the SoC to go to
the enetc port 2, this shouldn't be something that the
arm64: dts: ls1028a: move DSA CPU port property to the common SoC dtsi
Since the CPU port 4 of the switch is hardwired inside the SoC to go to
the enetc port 2, this shouldn't be something that the board files need
to set (but whether that CPU port is used or not is another discussion).
So move the DSA "ethernet" property to the common dtsi.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Michael Walle <michael@walle.cc>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
|
|
Revision tags: v5.15.64, v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58, v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48, v5.15.47, v5.15.46, v5.15.45, v5.15.44, v5.15.43, v5.15.42, v5.18, v5.15.41, v5.15.40, v5.15.39, v5.15.38, v5.15.37 |
|
| #
3c12e9da |
| 28-Apr-2022 |
Sean Anderson <sean.anderson@seco.com> |
arm64: dts: ls1028a: Update SFP node to include clock
The clocks property is now mandatory. Add it to avoid warning message.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Micha
arm64: dts: ls1028a: Update SFP node to include clock
The clocks property is now mandatory. Add it to avoid warning message.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Michael Walle <michael@walle.cc>
Fixes: eba5bea8f37f ("arm64: dts: ls1028a: add efuse node")
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
|
| #
33597c62 |
| 26-May-2022 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
arm64: dts: fsl: adjust whitespace around '='
Fix whitespace coding style: use single space instead of tabs or
multiple spaces around '=' sign in property assignment. No functional
changes (same DT
arm64: dts: fsl: adjust whitespace around '='
Fix whitespace coding style: use single space instead of tabs or
multiple spaces around '=' sign in property assignment. No functional
changes (same DTB).
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
|
|
Revision tags: v5.15.36, v5.15.35, v5.15.34, v5.15.33 |
|
| #
73d901d6 |
| 30-Mar-2022 |
Michael Walle <michael@walle.cc> |
arm64: dts: ls1028a: default to OTG mode for USB
At the moment, the dtsi will force the dr_mode to host. This is
problematic because it will always turn on the Vbus voltage regardless
if the port is
arm64: dts: ls1028a: default to OTG mode for USB
At the moment, the dtsi will force the dr_mode to host. This is
problematic because it will always turn on the Vbus voltage regardless
if the port is host or device. This might lead to a "shortcut" between
the two USB endpoints because both might have their Vbus supplies
enabled. Therefore, the default should be "otg" for any ports which
aren't host only (from a SoC point of view) and have a user of the dtsi
file overwrite that explicitly.
Move the 'dr_mode = "host";' into the board dts. Now that the dtsi
doesn't set the dr_mode anymore, we can also drop the 'dr_mode = "otg";'
in the board dts because that is the default value if dr_mode is not
set.
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
|
|
Revision tags: v5.15.32, v5.15.31, v5.17, v5.15.30, v5.15.29, v5.15.28, v5.15.27, v5.15.26, v5.15.25, v5.15.24 |
|
| #
eba5bea8 |
| 14-Feb-2022 |
Michael Walle <michael@walle.cc> |
arm64: dts: ls1028a: add efuse node
Layerscape SoCs contain a Security Fuse Processor which is basically a
efuse controller. Add the node, so userspace can read the efuses.
Signed-off-by: Michael W
arm64: dts: ls1028a: add efuse node
Layerscape SoCs contain a Security Fuse Processor which is basically a
efuse controller. Add the node, so userspace can read the efuses.
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
|
|
Revision tags: v5.15.23, v5.15.22, v5.15.21, v5.15.20, v5.15.19, v5.15.18, v5.15.17, v5.4.173, v5.15.16, v5.15.15, v5.16, v5.15.10, v5.15.9, v5.15.8 |
|
| #
e426d63e |
| 14-Dec-2021 |
Alex Marginean <alexandru.marginean@nxp.com> |
arm64: dts: ls1028a-qds: add overlays for various serdes protocols
Add overlays for various serdes protocols on LS1028A QDS board using
different PHY cards. These should be applied at boot, based o
arm64: dts: ls1028a-qds: add overlays for various serdes protocols
Add overlays for various serdes protocols on LS1028A QDS board using
different PHY cards. These should be applied at boot, based on serdes
configuration. If no overlay is applied, only the RGMII interface on
the QDS is available in Linux.
Building device tree fragments requires passing the "-@" argument to
dtc, which increases the base dtb size and might cause some platforms to
fail to store the new binary. To avoid that, it would be nice to only
pass "-@" for the platforms where fragments will be used, aka
LS1028A-QDS. One approach suggested by Rob Herring is used here:
https://lore.kernel.org/patchwork/patch/821645/
Also moved the enet* override nodes in dts file to be in alphabetic order.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Jason Liu <jason.hui.liu@nxp.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
|
| #
71799672 |
| 14-Dec-2021 |
Biwen Li <biwen.li@nxp.com> |
arm64: dts: ls1028a: add flextimer based pwm nodes
Add pwm nodes using flextimer controller.
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Sh
arm64: dts: ls1028a: add flextimer based pwm nodes
Add pwm nodes using flextimer controller.
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
|
| #
dd3d936a |
| 14-Dec-2021 |
Biwen Li <biwen.li@nxp.com> |
arm64: dts: ls1028a: add ftm_alarm1 node to be used as wakeup source
Add flextimer2 based ftm_alarm1 node and enable it to be the default rtc
wakeup source for rdb and qds boards instead of the orig
arm64: dts: ls1028a: add ftm_alarm1 node to be used as wakeup source
Add flextimer2 based ftm_alarm1 node and enable it to be the default rtc
wakeup source for rdb and qds boards instead of the original flextimer1
which is used by PWM. The ftm_alarm0 node hence is disabled by default.
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
|
| #
e84e22c0 |
| 14-Dec-2021 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
arm64: dts: ls1028a: Add PCIe EP nodes
Add PCIe EP nodes for ls1028a to support EP mode.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by:
arm64: dts: ls1028a: Add PCIe EP nodes
Add PCIe EP nodes for ls1028a to support EP mode.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
|
|
Revision tags: v5.15.7, v5.15.6, v5.15.5, v5.15.4, v5.15.3, v5.15.2, v5.15.1, v5.15, v5.14.14, v5.14.13, v5.14.12, v5.14.11, v5.14.10, v5.14.9 |
|
| #
8fcea7be |
| 29-Sep-2021 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
arm64: dts: ls1028a: mark internal links between Felix and ENETC as capable of flow control
The internal Ethernet switch suffers from erratum A-050484 ("Ethernet
flow control not functional on L2 sw
arm64: dts: ls1028a: mark internal links between Felix and ENETC as capable of flow control
The internal Ethernet switch suffers from erratum A-050484 ("Ethernet
flow control not functional on L2 switch NPI port when XFH is used").
XFH stands for "Extraction Frame Header" - which basically means the
default "ocelot" DSA tagging protocol.
However, the switch supports one other tagging protocol - "ocelot-8021q",
and this is not subject to the erratum above. So describe the hardware
ability to pass PAUSE frames in the device tree, and let the driver
figure out whether it should use flow control on the CPU port or not,
depending on whether the "ocelot" or "ocelot-8021q" tagging protocol is
being used.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
|
|
Revision tags: v5.14.8, v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5, v5.14.4, v5.10.65, v5.14.3, v5.10.64, v5.14.2, v5.10.63, v5.14.1, v5.10.62 |
|
| #
70293bea |
| 31-Aug-2021 |
Michael Walle <michael@walle.cc> |
arm64: dts: ls1028a: disable usb controller by default
One of the last devices which are enabled by default are the USB
controllers. Although the pins are not multi-function pins, some boards
might
arm64: dts: ls1028a: disable usb controller by default
One of the last devices which are enabled by default are the USB
controllers. Although the pins are not multi-function pins, some boards
might not use USB at all. Apply the "disabled-by-default" style also for
the USB controllers and enable the controllers in the actual device tree
of the boards.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
|
| #
55ca18c0 |
| 31-Aug-2021 |
Michael Walle <michael@walle.cc> |
arm64: dts: ls1028a: add Vivante GPU node
Recently, support for this particular Vivante GC7000 GPU was added to the
linux kernel. Add the corresponding device tree node.
Signed-off-by: Michael Wall
arm64: dts: ls1028a: add Vivante GPU node
Recently, support for this particular Vivante GC7000 GPU was added to the
linux kernel. Add the corresponding device tree node.
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
|
| #
7de87eae |
| 31-Aug-2021 |
Michael Walle <michael@walle.cc> |
arm64: dts: ls1028a: move Mali DP500 node into /soc
Move it inside the /soc subnode because it is part of the CCSR space.
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Shawn Guo <s
arm64: dts: ls1028a: move Mali DP500 node into /soc
Move it inside the /soc subnode because it is part of the CCSR space.
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
|
| #
b4751afb |
| 31-Aug-2021 |
Michael Walle <michael@walle.cc> |
arm64: dts: ls1028a: move pixel clock pll into /soc
Move it inside the /soc subnode because it is part of the CCSR space.
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Shawn Guo <s
arm64: dts: ls1028a: move pixel clock pll into /soc
Move it inside the /soc subnode because it is part of the CCSR space.
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
|
| #
8b94aa31 |
| 15-Sep-2021 |
Michael Walle <michael@walle.cc> |
arm64: dts: ls1028a: fix eSDHC2 node
On the LS1028A this instance of the eSDHC controller is intended for
either an eMMC or eSDIO card. It doesn't provide a card detect pin and
its IO voltage is fix
arm64: dts: ls1028a: fix eSDHC2 node
On the LS1028A this instance of the eSDHC controller is intended for
either an eMMC or eSDIO card. It doesn't provide a card detect pin and
its IO voltage is fixed at 1.8V.
Remove the bogus broken-cd property, instead add the non-removable
property. Fix the voltage-ranges property and set it to 1.8V only.
Fixes: 491d3a3fc113 ("arm64: dts: ls1028a: Add esdhc node in dts")
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
|
|
Revision tags: v5.14, v5.10.61, v5.10.60, v5.10.53, v5.10.52, v5.10.51, v5.10.50, v5.10.49, v5.13, v5.10.46, v5.10.43 |
|
| #
7e71b854 |
| 08-Jun-2021 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
arm64: dts: ls1028a: fix node name for the sysclk
U-Boot attempts to fix up the "clock-frequency" property of the "/sysclk" node:
https://elixir.bootlin.com/u-boot/v2021.04/source/arch/arm/cpu/armv8
arm64: dts: ls1028a: fix node name for the sysclk
U-Boot attempts to fix up the "clock-frequency" property of the "/sysclk" node:
https://elixir.bootlin.com/u-boot/v2021.04/source/arch/arm/cpu/armv8/fsl-layerscape/fdt.c#L512
but fails to do so:
## Booting kernel from Legacy Image at a1000000 ...
Image Name:
Created: 2021-06-08 10:31:38 UTC
Image Type: AArch64 Linux Kernel Image (gzip compressed)
Data Size: 15431370 Bytes = 14.7 MiB
Load Address: 80080000
Entry Point: 80080000
Verifying Checksum ... OK
## Flattened Device Tree blob at a0000000
Booting using the fdt blob at 0xa0000000
Uncompressing Kernel Image
Loading Device Tree to 00000000fbb19000, end 00000000fbb22717 ... OK
Unable to update property /sysclk:clock-frequency, err=FDT_ERR_NOTFOUND
Starting kernel ...
All Layerscape SoCs except LS1028A use "sysclk" as the node name, and
not "clock-sysclk". So change the node name of LS1028A accordingly.
Fixes: 8897f3255c9c ("arm64: dts: Add support for NXP LS1028A SoC")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Revision tags: v5.10.42, v5.10.41, v5.10.40, v5.10.39 |
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ce87d936 |
| 21-May-2021 |
Zhen Lei <thunder.leizhen@huawei.com> |
arm64: dts: freescale: Separate each group of data in the property 'reg'
Do not write the 'reg' of multiple groups of data into a uint32 array,
use <> to separate them. Otherwise, the errors similar
arm64: dts: freescale: Separate each group of data in the property 'reg'
Do not write the 'reg' of multiple groups of data into a uint32 array,
use <> to separate them. Otherwise, the errors similar to the following
will be reported by reg.yaml.
arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dt.yaml:
soc: pcie@3400000:reg:0: \
[0, 54525952, 0, 1048576, 64, 0, 0, 8192] is too long
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Revision tags: v5.4.119, v5.10.36, v5.10.35, v5.10.34, v5.4.116, v5.10.33, v5.12, v5.10.32, v5.10.31, v5.10.30 |
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6bee93d9 |
| 07-Apr-2021 |
Kornel Duleba <mindal@semihalf.com> |
arm64: dts: fsl-ls1028a: Correct ECAM PCIE window ranges
Currently all PCIE windows point to bus address 0x0, which does not match
the values obtained from hardware during EA.
Replace those values w
arm64: dts: fsl-ls1028a: Correct ECAM PCIE window ranges
Currently all PCIE windows point to bus address 0x0, which does not match
the values obtained from hardware during EA.
Replace those values with CPU addresses, since in reality we
have a 1:1 mapping between the two.
Signed-off-by: Kornel Duleba <mindal@semihalf.com>
Acked-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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dabea675 |
| 08-Apr-2021 |
Michael Walle <michael@walle.cc> |
arm64: dts: ls1028a: fix memory node
While enabling EDAC support for the LS1028A it was discovered that the
memory node has a wrong endianness setting as well as a wrong interrupt
assignment. Fix bo
arm64: dts: ls1028a: fix memory node
While enabling EDAC support for the LS1028A it was discovered that the
memory node has a wrong endianness setting as well as a wrong interrupt
assignment. Fix both.
This was tested on a sl28 board. To force ECC errors, you can use the
error injection supported by the controller in hardware (with
CONFIG_EDAC_DEBUG enabled):
# enable error injection
$ echo 0x100 > /sys/devices/system/edac/mc/mc0/inject_ctrl
# flip lowest bit of the data
$ echo 0x1 > /sys/devices/system/edac/mc/mc0/inject_data_lo
Fixes: 8897f3255c9c ("arm64: dts: Add support for NXP LS1028A SoC")
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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