18897f325SBhaskar Upadhaya// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 28897f325SBhaskar Upadhaya/* 38897f325SBhaskar Upadhaya * Device Tree Include file for NXP Layerscape-1028A family SoC. 48897f325SBhaskar Upadhaya * 5f7d48ffcSWasim Khan * Copyright 2018-2020 NXP 68897f325SBhaskar Upadhaya * 78897f325SBhaskar Upadhaya * Harninder Rai <harninder.rai@nxp.com> 88897f325SBhaskar Upadhaya * 98897f325SBhaskar Upadhaya */ 108897f325SBhaskar Upadhaya 1199314eb1SMichael Walle#include <dt-bindings/clock/fsl,qoriq-clockgen.h> 128897f325SBhaskar Upadhaya#include <dt-bindings/interrupt-controller/arm-gic.h> 138897f325SBhaskar Upadhaya#include <dt-bindings/thermal/thermal.h> 148897f325SBhaskar Upadhaya 158897f325SBhaskar Upadhaya/ { 168897f325SBhaskar Upadhaya compatible = "fsl,ls1028a"; 178897f325SBhaskar Upadhaya interrupt-parent = <&gic>; 188897f325SBhaskar Upadhaya #address-cells = <2>; 198897f325SBhaskar Upadhaya #size-cells = <2>; 208897f325SBhaskar Upadhaya 218897f325SBhaskar Upadhaya cpus { 228897f325SBhaskar Upadhaya #address-cells = <1>; 238897f325SBhaskar Upadhaya #size-cells = <0>; 248897f325SBhaskar Upadhaya 258897f325SBhaskar Upadhaya cpu0: cpu@0 { 268897f325SBhaskar Upadhaya device_type = "cpu"; 278897f325SBhaskar Upadhaya compatible = "arm,cortex-a72"; 288897f325SBhaskar Upadhaya reg = <0x0>; 298897f325SBhaskar Upadhaya enable-method = "psci"; 3099314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 0>; 31*fcf7ff67SHui Wang i-cache-size = <0xc000>; 32*fcf7ff67SHui Wang i-cache-line-size = <64>; 33*fcf7ff67SHui Wang i-cache-sets = <256>; 34*fcf7ff67SHui Wang d-cache-size = <0x8000>; 35*fcf7ff67SHui Wang d-cache-line-size = <64>; 36*fcf7ff67SHui Wang d-cache-sets = <256>; 378897f325SBhaskar Upadhaya next-level-cache = <&l2>; 3853f2ac9dSRan Wang cpu-idle-states = <&CPU_PW20>; 39571cebfeSYuantian Tang #cooling-cells = <2>; 408897f325SBhaskar Upadhaya }; 418897f325SBhaskar Upadhaya 428897f325SBhaskar Upadhaya cpu1: cpu@1 { 438897f325SBhaskar Upadhaya device_type = "cpu"; 448897f325SBhaskar Upadhaya compatible = "arm,cortex-a72"; 458897f325SBhaskar Upadhaya reg = <0x1>; 468897f325SBhaskar Upadhaya enable-method = "psci"; 4799314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 0>; 48*fcf7ff67SHui Wang i-cache-size = <0xc000>; 49*fcf7ff67SHui Wang i-cache-line-size = <64>; 50*fcf7ff67SHui Wang i-cache-sets = <256>; 51*fcf7ff67SHui Wang d-cache-size = <0x8000>; 52*fcf7ff67SHui Wang d-cache-line-size = <64>; 53*fcf7ff67SHui Wang d-cache-sets = <256>; 548897f325SBhaskar Upadhaya next-level-cache = <&l2>; 5553f2ac9dSRan Wang cpu-idle-states = <&CPU_PW20>; 56571cebfeSYuantian Tang #cooling-cells = <2>; 578897f325SBhaskar Upadhaya }; 588897f325SBhaskar Upadhaya 598897f325SBhaskar Upadhaya l2: l2-cache { 608897f325SBhaskar Upadhaya compatible = "cache"; 613b450831SPierre Gondois cache-level = <2>; 62c290d09aSKrzysztof Kozlowski cache-unified; 63*fcf7ff67SHui Wang cache-size = <0x100000>; 64*fcf7ff67SHui Wang cache-line-size = <64>; 65*fcf7ff67SHui Wang cache-sets = <1024>; 668897f325SBhaskar Upadhaya }; 678897f325SBhaskar Upadhaya }; 688897f325SBhaskar Upadhaya 698897f325SBhaskar Upadhaya idle-states { 708897f325SBhaskar Upadhaya /* 718897f325SBhaskar Upadhaya * PSCI node is not added default, U-boot will add missing 728897f325SBhaskar Upadhaya * parts if it determines to use PSCI. 738897f325SBhaskar Upadhaya */ 749b631649SLinus Walleij entry-method = "psci"; 758897f325SBhaskar Upadhaya 7653f2ac9dSRan Wang CPU_PW20: cpu-pw20 { 778897f325SBhaskar Upadhaya compatible = "arm,idle-state"; 7853f2ac9dSRan Wang idle-state-name = "PW20"; 7953f2ac9dSRan Wang arm,psci-suspend-param = <0x0>; 8053f2ac9dSRan Wang entry-latency-us = <2000>; 8153f2ac9dSRan Wang exit-latency-us = <2000>; 8253f2ac9dSRan Wang min-residency-us = <6000>; 838897f325SBhaskar Upadhaya }; 848897f325SBhaskar Upadhaya }; 858897f325SBhaskar Upadhaya 8671799672SBiwen Li rtc_clk: rtc-clk { 8771799672SBiwen Li compatible = "fixed-clock"; 8871799672SBiwen Li #clock-cells = <0>; 8971799672SBiwen Li clock-frequency = <32768>; 9071799672SBiwen Li clock-output-names = "rtc_clk"; 9171799672SBiwen Li }; 9271799672SBiwen Li 937e71b854SVladimir Oltean sysclk: sysclk { 948897f325SBhaskar Upadhaya compatible = "fixed-clock"; 958897f325SBhaskar Upadhaya #clock-cells = <0>; 968897f325SBhaskar Upadhaya clock-frequency = <100000000>; 978897f325SBhaskar Upadhaya clock-output-names = "sysclk"; 988897f325SBhaskar Upadhaya }; 998897f325SBhaskar Upadhaya 10081f36887SWen He osc_27m: clock-osc-27m { 1017f538f19SWen He compatible = "fixed-clock"; 1027f538f19SWen He #clock-cells = <0>; 1037f538f19SWen He clock-frequency = <27000000>; 10481f36887SWen He clock-output-names = "phy_27m"; 10581f36887SWen He }; 10681f36887SWen He 107f90931aeSMichael Walle firmware { 108c67b761aSSahil Malhotra optee: optee { 109f90931aeSMichael Walle compatible = "linaro,optee-tz"; 110f90931aeSMichael Walle method = "smc"; 111f90931aeSMichael Walle status = "disabled"; 112f90931aeSMichael Walle }; 113f90931aeSMichael Walle }; 114f90931aeSMichael Walle 1158897f325SBhaskar Upadhaya reboot { 1168897f325SBhaskar Upadhaya compatible = "syscon-reboot"; 1173f0fb37bSMichael Walle regmap = <&rst>; 1181653e3d4SMichael Walle offset = <0>; 1198897f325SBhaskar Upadhaya mask = <0x02>; 1208897f325SBhaskar Upadhaya }; 1218897f325SBhaskar Upadhaya 1228897f325SBhaskar Upadhaya timer { 1238897f325SBhaskar Upadhaya compatible = "arm,armv8-timer"; 1248897f325SBhaskar Upadhaya interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | 1258897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>, 1268897f325SBhaskar Upadhaya <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | 1278897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>, 1288897f325SBhaskar Upadhaya <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | 1298897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>, 1308897f325SBhaskar Upadhaya <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | 1318897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>; 1328897f325SBhaskar Upadhaya }; 1338897f325SBhaskar Upadhaya 134b9eb314aSAlison Wang pmu { 135b9eb314aSAlison Wang compatible = "arm,cortex-a72-pmu"; 136b9eb314aSAlison Wang interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 137b9eb314aSAlison Wang }; 138b9eb314aSAlison Wang 1398897f325SBhaskar Upadhaya gic: interrupt-controller@6000000 { 1408897f325SBhaskar Upadhaya compatible = "arm,gic-v3"; 1418897f325SBhaskar Upadhaya #address-cells = <2>; 1428897f325SBhaskar Upadhaya #size-cells = <2>; 1438897f325SBhaskar Upadhaya ranges; 1448897f325SBhaskar Upadhaya reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 1458897f325SBhaskar Upadhaya <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */ 1468897f325SBhaskar Upadhaya #interrupt-cells = <3>; 1478897f325SBhaskar Upadhaya interrupt-controller; 1488897f325SBhaskar Upadhaya interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | 1498897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>; 15004b09f6eSRob Herring its: msi-controller@6020000 { 1518897f325SBhaskar Upadhaya compatible = "arm,gic-v3-its"; 1528897f325SBhaskar Upadhaya msi-controller; 1538897f325SBhaskar Upadhaya reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */ 1548897f325SBhaskar Upadhaya }; 1558897f325SBhaskar Upadhaya }; 1568897f325SBhaskar Upadhaya 15768e36a42SFabio Estevam thermal-zones { 1583269c178SYuantian Tang ddr-controller { 15968e36a42SFabio Estevam polling-delay-passive = <1000>; 16068e36a42SFabio Estevam polling-delay = <5000>; 16168e36a42SFabio Estevam thermal-sensors = <&tmu 0>; 16268e36a42SFabio Estevam 16368e36a42SFabio Estevam trips { 1643269c178SYuantian Tang ddr-ctrler-alert { 1653269c178SYuantian Tang temperature = <85000>; 1663269c178SYuantian Tang hysteresis = <2000>; 1673269c178SYuantian Tang type = "passive"; 1683269c178SYuantian Tang }; 1693269c178SYuantian Tang 1703269c178SYuantian Tang ddr-ctrler-crit { 1713269c178SYuantian Tang temperature = <95000>; 1723269c178SYuantian Tang hysteresis = <2000>; 1733269c178SYuantian Tang type = "critical"; 1743269c178SYuantian Tang }; 1753269c178SYuantian Tang }; 1763269c178SYuantian Tang }; 1773269c178SYuantian Tang 1783269c178SYuantian Tang core-cluster { 1793269c178SYuantian Tang polling-delay-passive = <1000>; 1803269c178SYuantian Tang polling-delay = <5000>; 1813269c178SYuantian Tang thermal-sensors = <&tmu 1>; 1823269c178SYuantian Tang 1833269c178SYuantian Tang trips { 18468e36a42SFabio Estevam core_cluster_alert: core-cluster-alert { 18568e36a42SFabio Estevam temperature = <85000>; 18668e36a42SFabio Estevam hysteresis = <2000>; 18768e36a42SFabio Estevam type = "passive"; 18868e36a42SFabio Estevam }; 18968e36a42SFabio Estevam 19068e36a42SFabio Estevam core_cluster_crit: core-cluster-crit { 19168e36a42SFabio Estevam temperature = <95000>; 19268e36a42SFabio Estevam hysteresis = <2000>; 19368e36a42SFabio Estevam type = "critical"; 19468e36a42SFabio Estevam }; 19568e36a42SFabio Estevam }; 19668e36a42SFabio Estevam 19768e36a42SFabio Estevam cooling-maps { 19868e36a42SFabio Estevam map0 { 19968e36a42SFabio Estevam trip = <&core_cluster_alert>; 20068e36a42SFabio Estevam cooling-device = 20168e36a42SFabio Estevam <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 20268e36a42SFabio Estevam <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 20368e36a42SFabio Estevam }; 20468e36a42SFabio Estevam }; 20568e36a42SFabio Estevam }; 20668e36a42SFabio Estevam }; 20768e36a42SFabio Estevam 2088897f325SBhaskar Upadhaya soc: soc { 2098897f325SBhaskar Upadhaya compatible = "simple-bus"; 2108897f325SBhaskar Upadhaya #address-cells = <2>; 2118897f325SBhaskar Upadhaya #size-cells = <2>; 2128897f325SBhaskar Upadhaya ranges; 2138897f325SBhaskar Upadhaya 2148897f325SBhaskar Upadhaya ddr: memory-controller@1080000 { 2158897f325SBhaskar Upadhaya compatible = "fsl,qoriq-memory-controller"; 2168897f325SBhaskar Upadhaya reg = <0x0 0x1080000 0x0 0x1000>; 217dabea675SMichael Walle interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 218dabea675SMichael Walle little-endian; 2198897f325SBhaskar Upadhaya }; 2208897f325SBhaskar Upadhaya 2218897f325SBhaskar Upadhaya dcfg: syscon@1e00000 { 22269c910d3SMichael Walle #address-cells = <1>; 22369c910d3SMichael Walle #size-cells = <1>; 22469c910d3SMichael Walle compatible = "fsl,ls1028a-dcfg", "syscon", "simple-mfd"; 2258897f325SBhaskar Upadhaya reg = <0x0 0x1e00000 0x0 0x10000>; 22669c910d3SMichael Walle ranges = <0x0 0x0 0x1e00000 0x10000>; 22733eae7fbSYinbo Zhu little-endian; 22869c910d3SMichael Walle 22969c910d3SMichael Walle fspi_clk: clock-controller@900 { 23069c910d3SMichael Walle compatible = "fsl,ls1028a-flexspi-clk"; 23169c910d3SMichael Walle reg = <0x900 0x4>; 23269c910d3SMichael Walle #clock-cells = <0>; 23369c910d3SMichael Walle clocks = <&clockgen QORIQ_CLK_HWACCEL 0>; 23469c910d3SMichael Walle clock-output-names = "fspi_clk"; 23569c910d3SMichael Walle }; 2368897f325SBhaskar Upadhaya }; 2378897f325SBhaskar Upadhaya 2383f0fb37bSMichael Walle rst: syscon@1e60000 { 2393f0fb37bSMichael Walle compatible = "syscon"; 2403f0fb37bSMichael Walle reg = <0x0 0x1e60000 0x0 0x10000>; 2413f0fb37bSMichael Walle little-endian; 2423f0fb37bSMichael Walle }; 2433f0fb37bSMichael Walle 2443c12e9daSSean Anderson sfp: efuse@1e80000 { 245eba5bea8SMichael Walle compatible = "fsl,ls1028a-sfp"; 246eba5bea8SMichael Walle reg = <0x0 0x1e80000 0x0 0x10000>; 2473c12e9daSSean Anderson clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 2483c12e9daSSean Anderson QORIQ_CLK_PLL_DIV(4)>; 2493c12e9daSSean Anderson clock-names = "sfp"; 250eba5bea8SMichael Walle #address-cells = <1>; 251eba5bea8SMichael Walle #size-cells = <1>; 252eba5bea8SMichael Walle 253eba5bea8SMichael Walle ls1028a_uid: unique-id@1c { 254eba5bea8SMichael Walle reg = <0x1c 0x8>; 255eba5bea8SMichael Walle }; 256eba5bea8SMichael Walle }; 257eba5bea8SMichael Walle 2588897f325SBhaskar Upadhaya scfg: syscon@1fc0000 { 2598897f325SBhaskar Upadhaya compatible = "fsl,ls1028a-scfg", "syscon"; 2608897f325SBhaskar Upadhaya reg = <0x0 0x1fc0000 0x0 0x10000>; 2618897f325SBhaskar Upadhaya big-endian; 2628897f325SBhaskar Upadhaya }; 2638897f325SBhaskar Upadhaya 2648897f325SBhaskar Upadhaya clockgen: clock-controller@1300000 { 2658897f325SBhaskar Upadhaya compatible = "fsl,ls1028a-clockgen"; 2668897f325SBhaskar Upadhaya reg = <0x0 0x1300000 0x0 0xa0000>; 2678897f325SBhaskar Upadhaya #clock-cells = <2>; 2688897f325SBhaskar Upadhaya clocks = <&sysclk>; 2698897f325SBhaskar Upadhaya }; 2708897f325SBhaskar Upadhaya 2718897f325SBhaskar Upadhaya i2c0: i2c@2000000 { 2728897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2738897f325SBhaskar Upadhaya #address-cells = <1>; 2748897f325SBhaskar Upadhaya #size-cells = <0>; 2758897f325SBhaskar Upadhaya reg = <0x0 0x2000000 0x0 0x10000>; 2768897f325SBhaskar Upadhaya interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 27799314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 27899314eb1SMichael Walle QORIQ_CLK_PLL_DIV(4)>; 2798897f325SBhaskar Upadhaya status = "disabled"; 2808897f325SBhaskar Upadhaya }; 2818897f325SBhaskar Upadhaya 2828897f325SBhaskar Upadhaya i2c1: i2c@2010000 { 2838897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2848897f325SBhaskar Upadhaya #address-cells = <1>; 2858897f325SBhaskar Upadhaya #size-cells = <0>; 2868897f325SBhaskar Upadhaya reg = <0x0 0x2010000 0x0 0x10000>; 2878897f325SBhaskar Upadhaya interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 28899314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 28999314eb1SMichael Walle QORIQ_CLK_PLL_DIV(4)>; 2908897f325SBhaskar Upadhaya status = "disabled"; 2918897f325SBhaskar Upadhaya }; 2928897f325SBhaskar Upadhaya 2938897f325SBhaskar Upadhaya i2c2: i2c@2020000 { 2948897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2958897f325SBhaskar Upadhaya #address-cells = <1>; 2968897f325SBhaskar Upadhaya #size-cells = <0>; 2978897f325SBhaskar Upadhaya reg = <0x0 0x2020000 0x0 0x10000>; 2988897f325SBhaskar Upadhaya interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 29999314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 30099314eb1SMichael Walle QORIQ_CLK_PLL_DIV(4)>; 3018897f325SBhaskar Upadhaya status = "disabled"; 3028897f325SBhaskar Upadhaya }; 3038897f325SBhaskar Upadhaya 3048897f325SBhaskar Upadhaya i2c3: i2c@2030000 { 3058897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 3068897f325SBhaskar Upadhaya #address-cells = <1>; 3078897f325SBhaskar Upadhaya #size-cells = <0>; 3088897f325SBhaskar Upadhaya reg = <0x0 0x2030000 0x0 0x10000>; 3098897f325SBhaskar Upadhaya interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 31099314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 31199314eb1SMichael Walle QORIQ_CLK_PLL_DIV(4)>; 3128897f325SBhaskar Upadhaya status = "disabled"; 3138897f325SBhaskar Upadhaya }; 3148897f325SBhaskar Upadhaya 3158897f325SBhaskar Upadhaya i2c4: i2c@2040000 { 3168897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 3178897f325SBhaskar Upadhaya #address-cells = <1>; 3188897f325SBhaskar Upadhaya #size-cells = <0>; 3198897f325SBhaskar Upadhaya reg = <0x0 0x2040000 0x0 0x10000>; 3208897f325SBhaskar Upadhaya interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 32199314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 32299314eb1SMichael Walle QORIQ_CLK_PLL_DIV(4)>; 3238897f325SBhaskar Upadhaya status = "disabled"; 3248897f325SBhaskar Upadhaya }; 3258897f325SBhaskar Upadhaya 3268897f325SBhaskar Upadhaya i2c5: i2c@2050000 { 3278897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 3288897f325SBhaskar Upadhaya #address-cells = <1>; 3298897f325SBhaskar Upadhaya #size-cells = <0>; 3308897f325SBhaskar Upadhaya reg = <0x0 0x2050000 0x0 0x10000>; 3318897f325SBhaskar Upadhaya interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 33299314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 33399314eb1SMichael Walle QORIQ_CLK_PLL_DIV(4)>; 3348897f325SBhaskar Upadhaya status = "disabled"; 3358897f325SBhaskar Upadhaya }; 3368897f325SBhaskar Upadhaya 3378897f325SBhaskar Upadhaya i2c6: i2c@2060000 { 3388897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 3398897f325SBhaskar Upadhaya #address-cells = <1>; 3408897f325SBhaskar Upadhaya #size-cells = <0>; 3418897f325SBhaskar Upadhaya reg = <0x0 0x2060000 0x0 0x10000>; 3428897f325SBhaskar Upadhaya interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 34399314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 34499314eb1SMichael Walle QORIQ_CLK_PLL_DIV(4)>; 3458897f325SBhaskar Upadhaya status = "disabled"; 3468897f325SBhaskar Upadhaya }; 3478897f325SBhaskar Upadhaya 3488897f325SBhaskar Upadhaya i2c7: i2c@2070000 { 3498897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 3508897f325SBhaskar Upadhaya #address-cells = <1>; 3518897f325SBhaskar Upadhaya #size-cells = <0>; 3528897f325SBhaskar Upadhaya reg = <0x0 0x2070000 0x0 0x10000>; 3538897f325SBhaskar Upadhaya interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 35499314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 35599314eb1SMichael Walle QORIQ_CLK_PLL_DIV(4)>; 3568897f325SBhaskar Upadhaya status = "disabled"; 3578897f325SBhaskar Upadhaya }; 3588897f325SBhaskar Upadhaya 359c77fae5bSAshish Kumar fspi: spi@20c0000 { 360c77fae5bSAshish Kumar compatible = "nxp,lx2160a-fspi"; 361c77fae5bSAshish Kumar #address-cells = <1>; 362c77fae5bSAshish Kumar #size-cells = <0>; 363c77fae5bSAshish Kumar reg = <0x0 0x20c0000 0x0 0x10000>, 364c77fae5bSAshish Kumar <0x0 0x20000000 0x0 0x10000000>; 365c77fae5bSAshish Kumar reg-names = "fspi_base", "fspi_mmap"; 366c77fae5bSAshish Kumar interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 36769c910d3SMichael Walle clocks = <&fspi_clk>, <&fspi_clk>; 368c77fae5bSAshish Kumar clock-names = "fspi_en", "fspi"; 369c77fae5bSAshish Kumar status = "disabled"; 370c77fae5bSAshish Kumar }; 371c77fae5bSAshish Kumar 372c2d35adaSMichael Walle dspi0: spi@2100000 { 373c2d35adaSMichael Walle compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 374c2d35adaSMichael Walle #address-cells = <1>; 375c2d35adaSMichael Walle #size-cells = <0>; 376c2d35adaSMichael Walle reg = <0x0 0x2100000 0x0 0x10000>; 377c2d35adaSMichael Walle interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 378c2d35adaSMichael Walle clock-names = "dspi"; 37999314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 38099314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 381dd12fa69SVladimir Oltean dmas = <&edma0 0 62>, <&edma0 0 60>; 382dd12fa69SVladimir Oltean dma-names = "tx", "rx"; 383c2d35adaSMichael Walle spi-num-chipselects = <4>; 384c2d35adaSMichael Walle little-endian; 385c2d35adaSMichael Walle status = "disabled"; 386c2d35adaSMichael Walle }; 387c2d35adaSMichael Walle 388c2d35adaSMichael Walle dspi1: spi@2110000 { 389c2d35adaSMichael Walle compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 390c2d35adaSMichael Walle #address-cells = <1>; 391c2d35adaSMichael Walle #size-cells = <0>; 392c2d35adaSMichael Walle reg = <0x0 0x2110000 0x0 0x10000>; 393c2d35adaSMichael Walle interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 394c2d35adaSMichael Walle clock-names = "dspi"; 39599314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 39699314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 397dd12fa69SVladimir Oltean dmas = <&edma0 0 58>, <&edma0 0 56>; 398dd12fa69SVladimir Oltean dma-names = "tx", "rx"; 399c2d35adaSMichael Walle spi-num-chipselects = <4>; 400c2d35adaSMichael Walle little-endian; 401c2d35adaSMichael Walle status = "disabled"; 402c2d35adaSMichael Walle }; 403c2d35adaSMichael Walle 404c2d35adaSMichael Walle dspi2: spi@2120000 { 405c2d35adaSMichael Walle compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 406c2d35adaSMichael Walle #address-cells = <1>; 407c2d35adaSMichael Walle #size-cells = <0>; 408c2d35adaSMichael Walle reg = <0x0 0x2120000 0x0 0x10000>; 409c2d35adaSMichael Walle interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 410c2d35adaSMichael Walle clock-names = "dspi"; 41199314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 41299314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 413dd12fa69SVladimir Oltean dmas = <&edma0 0 54>, <&edma0 0 2>; 414dd12fa69SVladimir Oltean dma-names = "tx", "rx"; 415c2d35adaSMichael Walle spi-num-chipselects = <3>; 416c2d35adaSMichael Walle little-endian; 417c2d35adaSMichael Walle status = "disabled"; 418c2d35adaSMichael Walle }; 419c2d35adaSMichael Walle 420491d3a3fSAshish Kumar esdhc: mmc@2140000 { 421491d3a3fSAshish Kumar compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 422491d3a3fSAshish Kumar reg = <0x0 0x2140000 0x0 0x10000>; 423491d3a3fSAshish Kumar interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 424491d3a3fSAshish Kumar clock-frequency = <0>; /* fixed up by bootloader */ 42599314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; 426491d3a3fSAshish Kumar voltage-ranges = <1800 1800 3300 3300>; 427491d3a3fSAshish Kumar sdhci,auto-cmd12; 428491d3a3fSAshish Kumar little-endian; 429491d3a3fSAshish Kumar bus-width = <4>; 430491d3a3fSAshish Kumar status = "disabled"; 431491d3a3fSAshish Kumar }; 432491d3a3fSAshish Kumar 433491d3a3fSAshish Kumar esdhc1: mmc@2150000 { 434491d3a3fSAshish Kumar compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 435491d3a3fSAshish Kumar reg = <0x0 0x2150000 0x0 0x10000>; 436491d3a3fSAshish Kumar interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 437491d3a3fSAshish Kumar clock-frequency = <0>; /* fixed up by bootloader */ 43899314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; 4398b94aa31SMichael Walle voltage-ranges = <1800 1800>; 440491d3a3fSAshish Kumar sdhci,auto-cmd12; 4418b94aa31SMichael Walle non-removable; 442491d3a3fSAshish Kumar little-endian; 443491d3a3fSAshish Kumar bus-width = <4>; 444491d3a3fSAshish Kumar status = "disabled"; 445491d3a3fSAshish Kumar }; 446491d3a3fSAshish Kumar 44704fa4f03SMichael Walle can0: can@2180000 { 448c9e5ef8cSKuldeep Singh compatible = "fsl,lx2160ar1-flexcan"; 44904fa4f03SMichael Walle reg = <0x0 0x2180000 0x0 0x10000>; 45004fa4f03SMichael Walle interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 451c9e5ef8cSKuldeep Singh clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 452c9e5ef8cSKuldeep Singh QORIQ_CLK_PLL_DIV(2)>, 453c9e5ef8cSKuldeep Singh <&clockgen QORIQ_CLK_PLATFORM_PLL 45499314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 45504fa4f03SMichael Walle clock-names = "ipg", "per"; 45604fa4f03SMichael Walle status = "disabled"; 45704fa4f03SMichael Walle }; 45804fa4f03SMichael Walle 45904fa4f03SMichael Walle can1: can@2190000 { 460c9e5ef8cSKuldeep Singh compatible = "fsl,lx2160ar1-flexcan"; 46104fa4f03SMichael Walle reg = <0x0 0x2190000 0x0 0x10000>; 46204fa4f03SMichael Walle interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 463c9e5ef8cSKuldeep Singh clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 464c9e5ef8cSKuldeep Singh QORIQ_CLK_PLL_DIV(2)>, 465c9e5ef8cSKuldeep Singh <&clockgen QORIQ_CLK_PLATFORM_PLL 46699314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 46704fa4f03SMichael Walle clock-names = "ipg", "per"; 46804fa4f03SMichael Walle status = "disabled"; 46904fa4f03SMichael Walle }; 47004fa4f03SMichael Walle 4718897f325SBhaskar Upadhaya duart0: serial@21c0500 { 4728897f325SBhaskar Upadhaya compatible = "fsl,ns16550", "ns16550a"; 4738897f325SBhaskar Upadhaya reg = <0x00 0x21c0500 0x0 0x100>; 4748897f325SBhaskar Upadhaya interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 47599314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 47699314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 4778897f325SBhaskar Upadhaya status = "disabled"; 4788897f325SBhaskar Upadhaya }; 4798897f325SBhaskar Upadhaya 4808897f325SBhaskar Upadhaya duart1: serial@21c0600 { 4818897f325SBhaskar Upadhaya compatible = "fsl,ns16550", "ns16550a"; 4828897f325SBhaskar Upadhaya reg = <0x00 0x21c0600 0x0 0x100>; 4838897f325SBhaskar Upadhaya interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 48499314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 48599314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 4868897f325SBhaskar Upadhaya status = "disabled"; 4878897f325SBhaskar Upadhaya }; 4888897f325SBhaskar Upadhaya 4892607d724SMichael Walle 4902607d724SMichael Walle lpuart0: serial@2260000 { 4912607d724SMichael Walle compatible = "fsl,ls1028a-lpuart"; 4922607d724SMichael Walle reg = <0x0 0x2260000 0x0 0x1000>; 4932607d724SMichael Walle interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 49499314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 49599314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 4962607d724SMichael Walle clock-names = "ipg"; 4972607d724SMichael Walle dma-names = "rx","tx"; 4982607d724SMichael Walle dmas = <&edma0 1 32>, 4992607d724SMichael Walle <&edma0 1 33>; 5002607d724SMichael Walle status = "disabled"; 5012607d724SMichael Walle }; 5022607d724SMichael Walle 5032607d724SMichael Walle lpuart1: serial@2270000 { 5042607d724SMichael Walle compatible = "fsl,ls1028a-lpuart"; 5052607d724SMichael Walle reg = <0x0 0x2270000 0x0 0x1000>; 5062607d724SMichael Walle interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 50799314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 50899314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 5092607d724SMichael Walle clock-names = "ipg"; 5102607d724SMichael Walle dma-names = "rx","tx"; 5112607d724SMichael Walle dmas = <&edma0 1 30>, 5122607d724SMichael Walle <&edma0 1 31>; 5132607d724SMichael Walle status = "disabled"; 5142607d724SMichael Walle }; 5152607d724SMichael Walle 5162607d724SMichael Walle lpuart2: serial@2280000 { 5172607d724SMichael Walle compatible = "fsl,ls1028a-lpuart"; 5182607d724SMichael Walle reg = <0x0 0x2280000 0x0 0x1000>; 5192607d724SMichael Walle interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 52099314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 52199314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 5222607d724SMichael Walle clock-names = "ipg"; 5232607d724SMichael Walle dma-names = "rx","tx"; 5242607d724SMichael Walle dmas = <&edma0 1 28>, 5252607d724SMichael Walle <&edma0 1 29>; 5262607d724SMichael Walle status = "disabled"; 5272607d724SMichael Walle }; 5282607d724SMichael Walle 5292607d724SMichael Walle lpuart3: serial@2290000 { 5302607d724SMichael Walle compatible = "fsl,ls1028a-lpuart"; 5312607d724SMichael Walle reg = <0x0 0x2290000 0x0 0x1000>; 5322607d724SMichael Walle interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 53399314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 53499314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 5352607d724SMichael Walle clock-names = "ipg"; 5362607d724SMichael Walle dma-names = "rx","tx"; 5372607d724SMichael Walle dmas = <&edma0 1 26>, 5382607d724SMichael Walle <&edma0 1 27>; 5392607d724SMichael Walle status = "disabled"; 5402607d724SMichael Walle }; 5412607d724SMichael Walle 5422607d724SMichael Walle lpuart4: serial@22a0000 { 5432607d724SMichael Walle compatible = "fsl,ls1028a-lpuart"; 5442607d724SMichael Walle reg = <0x0 0x22a0000 0x0 0x1000>; 5452607d724SMichael Walle interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 54699314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 54799314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 5482607d724SMichael Walle clock-names = "ipg"; 5492607d724SMichael Walle dma-names = "rx","tx"; 5502607d724SMichael Walle dmas = <&edma0 1 24>, 5512607d724SMichael Walle <&edma0 1 25>; 5522607d724SMichael Walle status = "disabled"; 5532607d724SMichael Walle }; 5542607d724SMichael Walle 5552607d724SMichael Walle lpuart5: serial@22b0000 { 5562607d724SMichael Walle compatible = "fsl,ls1028a-lpuart"; 5572607d724SMichael Walle reg = <0x0 0x22b0000 0x0 0x1000>; 5582607d724SMichael Walle interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 55999314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 56099314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 5612607d724SMichael Walle clock-names = "ipg"; 5622607d724SMichael Walle dma-names = "rx","tx"; 5632607d724SMichael Walle dmas = <&edma0 1 22>, 5642607d724SMichael Walle <&edma0 1 23>; 5652607d724SMichael Walle status = "disabled"; 5662607d724SMichael Walle }; 5672607d724SMichael Walle 568f54f7be5SAlison Wang edma0: dma-controller@22c0000 { 569f54f7be5SAlison Wang #dma-cells = <2>; 570e0d7856eSMichael Walle compatible = "fsl,ls1028a-edma", "fsl,vf610-edma"; 571f54f7be5SAlison Wang reg = <0x0 0x22c0000 0x0 0x10000>, 572f54f7be5SAlison Wang <0x0 0x22d0000 0x0 0x10000>, 573f54f7be5SAlison Wang <0x0 0x22e0000 0x0 0x10000>; 574f54f7be5SAlison Wang interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 575f54f7be5SAlison Wang <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 576f54f7be5SAlison Wang interrupt-names = "edma-tx", "edma-err"; 577f54f7be5SAlison Wang dma-channels = <32>; 578f54f7be5SAlison Wang clock-names = "dmamux0", "dmamux1"; 57999314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 58099314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>, 58199314eb1SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 58299314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 583f54f7be5SAlison Wang }; 584f54f7be5SAlison Wang 5858897f325SBhaskar Upadhaya gpio1: gpio@2300000 { 586f64697bdSSong Hui compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 5878897f325SBhaskar Upadhaya reg = <0x0 0x2300000 0x0 0x10000>; 5888897f325SBhaskar Upadhaya interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 5898897f325SBhaskar Upadhaya gpio-controller; 5908897f325SBhaskar Upadhaya #gpio-cells = <2>; 5918897f325SBhaskar Upadhaya interrupt-controller; 5928897f325SBhaskar Upadhaya #interrupt-cells = <2>; 593f64697bdSSong Hui little-endian; 5948897f325SBhaskar Upadhaya }; 5958897f325SBhaskar Upadhaya 5968897f325SBhaskar Upadhaya gpio2: gpio@2310000 { 597f64697bdSSong Hui compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 5988897f325SBhaskar Upadhaya reg = <0x0 0x2310000 0x0 0x10000>; 5998897f325SBhaskar Upadhaya interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 6008897f325SBhaskar Upadhaya gpio-controller; 6018897f325SBhaskar Upadhaya #gpio-cells = <2>; 6028897f325SBhaskar Upadhaya interrupt-controller; 6038897f325SBhaskar Upadhaya #interrupt-cells = <2>; 604f64697bdSSong Hui little-endian; 6058897f325SBhaskar Upadhaya }; 6068897f325SBhaskar Upadhaya 6078897f325SBhaskar Upadhaya gpio3: gpio@2320000 { 608f64697bdSSong Hui compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 6098897f325SBhaskar Upadhaya reg = <0x0 0x2320000 0x0 0x10000>; 6108897f325SBhaskar Upadhaya interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 6118897f325SBhaskar Upadhaya gpio-controller; 6128897f325SBhaskar Upadhaya #gpio-cells = <2>; 6138897f325SBhaskar Upadhaya interrupt-controller; 6148897f325SBhaskar Upadhaya #interrupt-cells = <2>; 615f64697bdSSong Hui little-endian; 6168897f325SBhaskar Upadhaya }; 6178897f325SBhaskar Upadhaya 618c92f56faSRan Wang usb0: usb@3100000 { 619c92f56faSRan Wang compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 620c92f56faSRan Wang reg = <0x0 0x3100000 0x0 0x10000>; 621c92f56faSRan Wang interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 622c92f56faSRan Wang snps,dis_rxdet_inp3_quirk; 623c92f56faSRan Wang snps,quirk-frame-length-adjustment = <0x20>; 624c92f56faSRan Wang snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 62570293beaSMichael Walle status = "disabled"; 626c92f56faSRan Wang }; 627c92f56faSRan Wang 628c92f56faSRan Wang usb1: usb@3110000 { 629c92f56faSRan Wang compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 630c92f56faSRan Wang reg = <0x0 0x3110000 0x0 0x10000>; 631c92f56faSRan Wang interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 632c92f56faSRan Wang snps,dis_rxdet_inp3_quirk; 633c92f56faSRan Wang snps,quirk-frame-length-adjustment = <0x20>; 634c92f56faSRan Wang snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 63570293beaSMichael Walle status = "disabled"; 6368897f325SBhaskar Upadhaya }; 6378897f325SBhaskar Upadhaya 6388897f325SBhaskar Upadhaya sata: sata@3200000 { 6398897f325SBhaskar Upadhaya compatible = "fsl,ls1028a-ahci"; 6408897f325SBhaskar Upadhaya reg = <0x0 0x3200000 0x0 0x10000>, 6413f3d7958SPeng Ma <0x7 0x100520 0x0 0x4>; 6428897f325SBhaskar Upadhaya reg-names = "ahci", "sata-ecc"; 6438897f325SBhaskar Upadhaya interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 64499314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 64599314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 6468897f325SBhaskar Upadhaya status = "disabled"; 6478897f325SBhaskar Upadhaya }; 6488897f325SBhaskar Upadhaya 649f7d48ffcSWasim Khan pcie1: pcie@3400000 { 650f6ff3f6dSXiaowei Bao compatible = "fsl,ls1028a-pcie"; 651ce87d936SZhen Lei reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ 652ce87d936SZhen Lei <0x80 0x00000000 0x0 0x00002000>; /* configuration space */ 653f6ff3f6dSXiaowei Bao reg-names = "regs", "config"; 654f6ff3f6dSXiaowei Bao interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 655f6ff3f6dSXiaowei Bao <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 656f6ff3f6dSXiaowei Bao interrupt-names = "pme", "aer"; 657f6ff3f6dSXiaowei Bao #address-cells = <3>; 658f6ff3f6dSXiaowei Bao #size-cells = <2>; 659f6ff3f6dSXiaowei Bao device_type = "pci"; 660f6ff3f6dSXiaowei Bao dma-coherent; 661f6ff3f6dSXiaowei Bao num-viewport = <8>; 662f6ff3f6dSXiaowei Bao bus-range = <0x0 0xff>; 663f6ff3f6dSXiaowei Bao ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */ 664f6ff3f6dSXiaowei Bao 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 665f6ff3f6dSXiaowei Bao msi-parent = <&its>; 666f6ff3f6dSXiaowei Bao #interrupt-cells = <1>; 667f6ff3f6dSXiaowei Bao interrupt-map-mask = <0 0 0 7>; 668f6ff3f6dSXiaowei Bao interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 669f6ff3f6dSXiaowei Bao <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 670f6ff3f6dSXiaowei Bao <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 671f6ff3f6dSXiaowei Bao <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 672f6ff3f6dSXiaowei Bao iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 673f6ff3f6dSXiaowei Bao status = "disabled"; 674f6ff3f6dSXiaowei Bao }; 675f6ff3f6dSXiaowei Bao 676e84e22c0SXiaowei Bao pcie_ep1: pcie-ep@3400000 { 677e84e22c0SXiaowei Bao compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep"; 678e84e22c0SXiaowei Bao reg = <0x00 0x03400000 0x0 0x00100000 679e84e22c0SXiaowei Bao 0x80 0x00000000 0x8 0x00000000>; 680e84e22c0SXiaowei Bao reg-names = "regs", "addr_space"; 681e84e22c0SXiaowei Bao interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ 682e84e22c0SXiaowei Bao interrupt-names = "pme"; 683e84e22c0SXiaowei Bao num-ib-windows = <6>; 684e84e22c0SXiaowei Bao num-ob-windows = <8>; 685e84e22c0SXiaowei Bao status = "disabled"; 686e84e22c0SXiaowei Bao }; 687e84e22c0SXiaowei Bao 688f7d48ffcSWasim Khan pcie2: pcie@3500000 { 689f6ff3f6dSXiaowei Bao compatible = "fsl,ls1028a-pcie"; 690ce87d936SZhen Lei reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ 691ce87d936SZhen Lei <0x88 0x00000000 0x0 0x00002000>; /* configuration space */ 692f6ff3f6dSXiaowei Bao reg-names = "regs", "config"; 693f6ff3f6dSXiaowei Bao interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 694f6ff3f6dSXiaowei Bao <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 695f6ff3f6dSXiaowei Bao interrupt-names = "pme", "aer"; 696f6ff3f6dSXiaowei Bao #address-cells = <3>; 697f6ff3f6dSXiaowei Bao #size-cells = <2>; 698f6ff3f6dSXiaowei Bao device_type = "pci"; 699f6ff3f6dSXiaowei Bao dma-coherent; 700f6ff3f6dSXiaowei Bao num-viewport = <8>; 701f6ff3f6dSXiaowei Bao bus-range = <0x0 0xff>; 702f6ff3f6dSXiaowei Bao ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 /* downstream I/O */ 703f6ff3f6dSXiaowei Bao 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 704f6ff3f6dSXiaowei Bao msi-parent = <&its>; 705f6ff3f6dSXiaowei Bao #interrupt-cells = <1>; 706f6ff3f6dSXiaowei Bao interrupt-map-mask = <0 0 0 7>; 707f6ff3f6dSXiaowei Bao interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 708f6ff3f6dSXiaowei Bao <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 709f6ff3f6dSXiaowei Bao <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 710f6ff3f6dSXiaowei Bao <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 711f6ff3f6dSXiaowei Bao iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 712f6ff3f6dSXiaowei Bao status = "disabled"; 713f6ff3f6dSXiaowei Bao }; 714f6ff3f6dSXiaowei Bao 715e84e22c0SXiaowei Bao pcie_ep2: pcie-ep@3500000 { 716e84e22c0SXiaowei Bao compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep"; 717e84e22c0SXiaowei Bao reg = <0x00 0x03500000 0x0 0x00100000 718e84e22c0SXiaowei Bao 0x88 0x00000000 0x8 0x00000000>; 719e84e22c0SXiaowei Bao reg-names = "regs", "addr_space"; 720e84e22c0SXiaowei Bao interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ 721e84e22c0SXiaowei Bao interrupt-names = "pme"; 722e84e22c0SXiaowei Bao num-ib-windows = <6>; 723e84e22c0SXiaowei Bao num-ob-windows = <8>; 724e84e22c0SXiaowei Bao status = "disabled"; 725e84e22c0SXiaowei Bao }; 726e84e22c0SXiaowei Bao 7278897f325SBhaskar Upadhaya smmu: iommu@5000000 { 7288897f325SBhaskar Upadhaya compatible = "arm,mmu-500"; 7298897f325SBhaskar Upadhaya reg = <0 0x5000000 0 0x800000>; 7308897f325SBhaskar Upadhaya #global-interrupts = <8>; 7318897f325SBhaskar Upadhaya #iommu-cells = <1>; 7328720913fSVladimir Oltean dma-coherent; 7338897f325SBhaskar Upadhaya stream-match-mask = <0x7c00>; 7348897f325SBhaskar Upadhaya /* global secure fault */ 7358897f325SBhaskar Upadhaya interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 7368897f325SBhaskar Upadhaya /* combined secure interrupt */ 7378897f325SBhaskar Upadhaya <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 7388897f325SBhaskar Upadhaya /* global non-secure fault */ 7398897f325SBhaskar Upadhaya <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 7408897f325SBhaskar Upadhaya /* combined non-secure interrupt */ 7418897f325SBhaskar Upadhaya <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 7428897f325SBhaskar Upadhaya /* performance counter interrupts 0-7 */ 7438897f325SBhaskar Upadhaya <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 7448897f325SBhaskar Upadhaya <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 7458897f325SBhaskar Upadhaya /* per context interrupt, 64 interrupts */ 7468897f325SBhaskar Upadhaya <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 7478897f325SBhaskar Upadhaya <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 7488897f325SBhaskar Upadhaya <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 7498897f325SBhaskar Upadhaya <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 7508897f325SBhaskar Upadhaya <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 7518897f325SBhaskar Upadhaya <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 7528897f325SBhaskar Upadhaya <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 7538897f325SBhaskar Upadhaya <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 7548897f325SBhaskar Upadhaya <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 7558897f325SBhaskar Upadhaya <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 7568897f325SBhaskar Upadhaya <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 7578897f325SBhaskar Upadhaya <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 7588897f325SBhaskar Upadhaya <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 7598897f325SBhaskar Upadhaya <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 7608897f325SBhaskar Upadhaya <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 7618897f325SBhaskar Upadhaya <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 7628897f325SBhaskar Upadhaya <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 7638897f325SBhaskar Upadhaya <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 7648897f325SBhaskar Upadhaya <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 7658897f325SBhaskar Upadhaya <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 7668897f325SBhaskar Upadhaya <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 7678897f325SBhaskar Upadhaya <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 7688897f325SBhaskar Upadhaya <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 7698897f325SBhaskar Upadhaya <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 7708897f325SBhaskar Upadhaya <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 7718897f325SBhaskar Upadhaya <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 7728897f325SBhaskar Upadhaya <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 7738897f325SBhaskar Upadhaya <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 7748897f325SBhaskar Upadhaya <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 7758897f325SBhaskar Upadhaya <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 7768897f325SBhaskar Upadhaya <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 7778897f325SBhaskar Upadhaya <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 7788897f325SBhaskar Upadhaya }; 779927d7f85SClaudiu Manoil 7801d0becabSHoria Geantă crypto: crypto@8000000 { 7811d0becabSHoria Geantă compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 7821d0becabSHoria Geantă fsl,sec-era = <10>; 7831d0becabSHoria Geantă #address-cells = <1>; 7841d0becabSHoria Geantă #size-cells = <1>; 7851d0becabSHoria Geantă ranges = <0x0 0x00 0x8000000 0x100000>; 7861d0becabSHoria Geantă reg = <0x00 0x8000000 0x0 0x100000>; 7871d0becabSHoria Geantă interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 7881d0becabSHoria Geantă dma-coherent; 7891d0becabSHoria Geantă 7901d0becabSHoria Geantă sec_jr0: jr@10000 { 7911d0becabSHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 7921d0becabSHoria Geantă "fsl,sec-v4.0-job-ring"; 7931d0becabSHoria Geantă reg = <0x10000 0x10000>; 7941d0becabSHoria Geantă interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 7951d0becabSHoria Geantă }; 7961d0becabSHoria Geantă 7971d0becabSHoria Geantă sec_jr1: jr@20000 { 7981d0becabSHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 7991d0becabSHoria Geantă "fsl,sec-v4.0-job-ring"; 8001d0becabSHoria Geantă reg = <0x20000 0x10000>; 8011d0becabSHoria Geantă interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 8021d0becabSHoria Geantă }; 8031d0becabSHoria Geantă 8041d0becabSHoria Geantă sec_jr2: jr@30000 { 8051d0becabSHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 8061d0becabSHoria Geantă "fsl,sec-v4.0-job-ring"; 8071d0becabSHoria Geantă reg = <0x30000 0x10000>; 8081d0becabSHoria Geantă interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 8091d0becabSHoria Geantă }; 8101d0becabSHoria Geantă 8111d0becabSHoria Geantă sec_jr3: jr@40000 { 8121d0becabSHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 8131d0becabSHoria Geantă "fsl,sec-v4.0-job-ring"; 8141d0becabSHoria Geantă reg = <0x40000 0x10000>; 8151d0becabSHoria Geantă interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 8161d0becabSHoria Geantă }; 8171d0becabSHoria Geantă }; 8181d0becabSHoria Geantă 8197802f88dSPeng Ma qdma: dma-controller@8380000 { 8207802f88dSPeng Ma compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma"; 8217802f88dSPeng Ma reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ 8227802f88dSPeng Ma <0x0 0x8390000 0x0 0x10000>, /* Status regs */ 8237802f88dSPeng Ma <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ 8247802f88dSPeng Ma interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 8257802f88dSPeng Ma <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 8267802f88dSPeng Ma <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 8277802f88dSPeng Ma <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 8287802f88dSPeng Ma <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 8297802f88dSPeng Ma interrupt-names = "qdma-error", "qdma-queue0", 8307802f88dSPeng Ma "qdma-queue1", "qdma-queue2", "qdma-queue3"; 8317802f88dSPeng Ma dma-channels = <8>; 8327802f88dSPeng Ma block-number = <1>; 8337802f88dSPeng Ma block-offset = <0x10000>; 8347802f88dSPeng Ma fsl,dma-queues = <2>; 8357802f88dSPeng Ma status-sizes = <64>; 8367802f88dSPeng Ma queue-sizes = <64 64>; 8377802f88dSPeng Ma }; 8387802f88dSPeng Ma 83957aa1bc7SChuanhua Han cluster1_core0_watchdog: watchdog@c000000 { 84057aa1bc7SChuanhua Han compatible = "arm,sp805", "arm,primecell"; 84157aa1bc7SChuanhua Han reg = <0x0 0xc000000 0x0 0x1000>; 84299314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 84399314eb1SMichael Walle QORIQ_CLK_PLL_DIV(16)>, 84499314eb1SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 84599314eb1SMichael Walle QORIQ_CLK_PLL_DIV(16)>; 846f2dc2359SAndre Przywara clock-names = "wdog_clk", "apb_pclk"; 84757aa1bc7SChuanhua Han }; 84857aa1bc7SChuanhua Han 84957aa1bc7SChuanhua Han cluster1_core1_watchdog: watchdog@c010000 { 85057aa1bc7SChuanhua Han compatible = "arm,sp805", "arm,primecell"; 85157aa1bc7SChuanhua Han reg = <0x0 0xc010000 0x0 0x1000>; 85299314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 85399314eb1SMichael Walle QORIQ_CLK_PLL_DIV(16)>, 85499314eb1SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 85599314eb1SMichael Walle QORIQ_CLK_PLL_DIV(16)>; 856f2dc2359SAndre Przywara clock-names = "wdog_clk", "apb_pclk"; 85757aa1bc7SChuanhua Han }; 85857aa1bc7SChuanhua Han 8597de87eaeSMichael Walle malidp0: display@f080000 { 8607de87eaeSMichael Walle compatible = "arm,mali-dp500"; 8617de87eaeSMichael Walle reg = <0x0 0xf080000 0x0 0x10000>; 8627de87eaeSMichael Walle interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, 8637de87eaeSMichael Walle <0 223 IRQ_TYPE_LEVEL_HIGH>; 8647de87eaeSMichael Walle interrupt-names = "DE", "SE"; 8657de87eaeSMichael Walle clocks = <&dpclk>, 8667de87eaeSMichael Walle <&clockgen QORIQ_CLK_HWACCEL 2>, 8677de87eaeSMichael Walle <&clockgen QORIQ_CLK_HWACCEL 2>, 8687de87eaeSMichael Walle <&clockgen QORIQ_CLK_HWACCEL 2>; 8697de87eaeSMichael Walle clock-names = "pxlclk", "mclk", "aclk", "pclk"; 8707de87eaeSMichael Walle arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; 8717de87eaeSMichael Walle arm,malidp-arqos-value = <0xd000d000>; 8727de87eaeSMichael Walle 8737de87eaeSMichael Walle port { 8747de87eaeSMichael Walle dpi0_out: endpoint { 8757de87eaeSMichael Walle 8767de87eaeSMichael Walle }; 8777de87eaeSMichael Walle }; 8787de87eaeSMichael Walle }; 8797de87eaeSMichael Walle 88055ca18c0SMichael Walle gpu: gpu@f0c0000 { 88155ca18c0SMichael Walle compatible = "vivante,gc"; 88255ca18c0SMichael Walle reg = <0x0 0xf0c0000 0x0 0x10000>; 88355ca18c0SMichael Walle interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 88455ca18c0SMichael Walle clocks = <&clockgen QORIQ_CLK_HWACCEL 2>, 88555ca18c0SMichael Walle <&clockgen QORIQ_CLK_HWACCEL 2>, 88655ca18c0SMichael Walle <&clockgen QORIQ_CLK_HWACCEL 2>; 88755ca18c0SMichael Walle clock-names = "core", "shader", "bus"; 88855ca18c0SMichael Walle #cooling-cells = <2>; 88955ca18c0SMichael Walle }; 89055ca18c0SMichael Walle 891f54f7be5SAlison Wang sai1: audio-controller@f100000 { 892f54f7be5SAlison Wang #sound-dai-cells = <0>; 893f54f7be5SAlison Wang compatible = "fsl,vf610-sai"; 894f54f7be5SAlison Wang reg = <0x0 0xf100000 0x0 0x10000>; 895f54f7be5SAlison Wang interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 89699314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 89799314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>, 89899314eb1SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 89999314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>, 90099314eb1SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 90199314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>, 90299314eb1SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 90399314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 904f54f7be5SAlison Wang clock-names = "bus", "mclk1", "mclk2", "mclk3"; 905f54f7be5SAlison Wang dma-names = "tx", "rx"; 906f54f7be5SAlison Wang dmas = <&edma0 1 4>, 907f54f7be5SAlison Wang <&edma0 1 3>; 9089c015e13SMichael Walle fsl,sai-asynchronous; 909f54f7be5SAlison Wang status = "disabled"; 910f54f7be5SAlison Wang }; 911f54f7be5SAlison Wang 912f54f7be5SAlison Wang sai2: audio-controller@f110000 { 913f54f7be5SAlison Wang #sound-dai-cells = <0>; 914f54f7be5SAlison Wang compatible = "fsl,vf610-sai"; 915f54f7be5SAlison Wang reg = <0x0 0xf110000 0x0 0x10000>; 916f54f7be5SAlison Wang interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 91799314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 91899314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>, 91999314eb1SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 92099314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>, 92199314eb1SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 92299314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>, 92399314eb1SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 92499314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 925f54f7be5SAlison Wang clock-names = "bus", "mclk1", "mclk2", "mclk3"; 926f54f7be5SAlison Wang dma-names = "tx", "rx"; 927f54f7be5SAlison Wang dmas = <&edma0 1 6>, 928f54f7be5SAlison Wang <&edma0 1 5>; 9299c015e13SMichael Walle fsl,sai-asynchronous; 930f54f7be5SAlison Wang status = "disabled"; 931f54f7be5SAlison Wang }; 932f54f7be5SAlison Wang 933434f9cc1SMichael Walle sai3: audio-controller@f120000 { 934434f9cc1SMichael Walle #sound-dai-cells = <0>; 935434f9cc1SMichael Walle compatible = "fsl,vf610-sai"; 936434f9cc1SMichael Walle reg = <0x0 0xf120000 0x0 0x10000>; 937434f9cc1SMichael Walle interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 93899314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 93999314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>, 94099314eb1SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 94199314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>, 94299314eb1SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 94399314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>, 94499314eb1SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 94599314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 946434f9cc1SMichael Walle clock-names = "bus", "mclk1", "mclk2", "mclk3"; 947434f9cc1SMichael Walle dma-names = "tx", "rx"; 948434f9cc1SMichael Walle dmas = <&edma0 1 8>, 949434f9cc1SMichael Walle <&edma0 1 7>; 9509c015e13SMichael Walle fsl,sai-asynchronous; 951f54f7be5SAlison Wang status = "disabled"; 952f54f7be5SAlison Wang }; 953f54f7be5SAlison Wang 954f54f7be5SAlison Wang sai4: audio-controller@f130000 { 955f54f7be5SAlison Wang #sound-dai-cells = <0>; 956f54f7be5SAlison Wang compatible = "fsl,vf610-sai"; 957f54f7be5SAlison Wang reg = <0x0 0xf130000 0x0 0x10000>; 958f54f7be5SAlison Wang interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 95999314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 96099314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>, 96199314eb1SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 96299314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>, 96399314eb1SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 96499314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>, 96599314eb1SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 96699314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 967f54f7be5SAlison Wang clock-names = "bus", "mclk1", "mclk2", "mclk3"; 968f54f7be5SAlison Wang dma-names = "tx", "rx"; 969f54f7be5SAlison Wang dmas = <&edma0 1 10>, 970f54f7be5SAlison Wang <&edma0 1 9>; 9719c015e13SMichael Walle fsl,sai-asynchronous; 972f54f7be5SAlison Wang status = "disabled"; 973f54f7be5SAlison Wang }; 974f54f7be5SAlison Wang 975434f9cc1SMichael Walle sai5: audio-controller@f140000 { 976434f9cc1SMichael Walle #sound-dai-cells = <0>; 977434f9cc1SMichael Walle compatible = "fsl,vf610-sai"; 978434f9cc1SMichael Walle reg = <0x0 0xf140000 0x0 0x10000>; 979434f9cc1SMichael Walle interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 98099314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 98199314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>, 98299314eb1SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 98399314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>, 98499314eb1SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 98599314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>, 98699314eb1SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 98799314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 988434f9cc1SMichael Walle clock-names = "bus", "mclk1", "mclk2", "mclk3"; 989434f9cc1SMichael Walle dma-names = "tx", "rx"; 990434f9cc1SMichael Walle dmas = <&edma0 1 12>, 991434f9cc1SMichael Walle <&edma0 1 11>; 9929c015e13SMichael Walle fsl,sai-asynchronous; 993434f9cc1SMichael Walle status = "disabled"; 994434f9cc1SMichael Walle }; 995434f9cc1SMichael Walle 996434f9cc1SMichael Walle sai6: audio-controller@f150000 { 997434f9cc1SMichael Walle #sound-dai-cells = <0>; 998434f9cc1SMichael Walle compatible = "fsl,vf610-sai"; 999434f9cc1SMichael Walle reg = <0x0 0xf150000 0x0 0x10000>; 1000434f9cc1SMichael Walle interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 100199314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 100299314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>, 100399314eb1SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 100499314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>, 100599314eb1SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 100699314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>, 100799314eb1SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 100899314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 1009434f9cc1SMichael Walle clock-names = "bus", "mclk1", "mclk2", "mclk3"; 1010434f9cc1SMichael Walle dma-names = "tx", "rx"; 1011434f9cc1SMichael Walle dmas = <&edma0 1 14>, 1012434f9cc1SMichael Walle <&edma0 1 13>; 10139c015e13SMichael Walle fsl,sai-asynchronous; 10148897f325SBhaskar Upadhaya status = "disabled"; 10158897f325SBhaskar Upadhaya }; 10168897f325SBhaskar Upadhaya 1017b4751afbSMichael Walle dpclk: clock-controller@f1f0000 { 1018b4751afbSMichael Walle compatible = "fsl,ls1028a-plldig"; 1019b4751afbSMichael Walle reg = <0x0 0xf1f0000 0x0 0x10000>; 1020b4751afbSMichael Walle #clock-cells = <0>; 1021b4751afbSMichael Walle clocks = <&osc_27m>; 1022b4751afbSMichael Walle }; 1023b4751afbSMichael Walle 10240b680963SFabio Estevam tmu: tmu@1f80000 { 1025571cebfeSYuantian Tang compatible = "fsl,qoriq-tmu"; 1026571cebfeSYuantian Tang reg = <0x0 0x1f80000 0x0 0x10000>; 1027571cebfeSYuantian Tang interrupts = <0 23 0x4>; 1028571cebfeSYuantian Tang fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; 1029571cebfeSYuantian Tang fsl,tmu-calibration = <0x00000000 0x00000024 1030571cebfeSYuantian Tang 0x00000001 0x0000002b 1031571cebfeSYuantian Tang 0x00000002 0x00000031 1032571cebfeSYuantian Tang 0x00000003 0x00000038 1033571cebfeSYuantian Tang 0x00000004 0x0000003f 1034571cebfeSYuantian Tang 0x00000005 0x00000045 1035571cebfeSYuantian Tang 0x00000006 0x0000004c 1036571cebfeSYuantian Tang 0x00000007 0x00000053 1037571cebfeSYuantian Tang 0x00000008 0x00000059 1038571cebfeSYuantian Tang 0x00000009 0x00000060 1039571cebfeSYuantian Tang 0x0000000a 0x00000066 1040571cebfeSYuantian Tang 0x0000000b 0x0000006d 1041571cebfeSYuantian Tang 1042571cebfeSYuantian Tang 0x00010000 0x0000001c 1043571cebfeSYuantian Tang 0x00010001 0x00000024 1044571cebfeSYuantian Tang 0x00010002 0x0000002c 1045571cebfeSYuantian Tang 0x00010003 0x00000035 1046571cebfeSYuantian Tang 0x00010004 0x0000003d 1047571cebfeSYuantian Tang 0x00010005 0x00000045 1048571cebfeSYuantian Tang 0x00010006 0x0000004d 1049961f8209SMichael Walle 0x00010007 0x00000055 1050571cebfeSYuantian Tang 0x00010008 0x0000005e 1051571cebfeSYuantian Tang 0x00010009 0x00000066 1052571cebfeSYuantian Tang 0x0001000a 0x0000006e 1053571cebfeSYuantian Tang 1054571cebfeSYuantian Tang 0x00020000 0x00000018 1055571cebfeSYuantian Tang 0x00020001 0x00000022 1056571cebfeSYuantian Tang 0x00020002 0x0000002d 1057571cebfeSYuantian Tang 0x00020003 0x00000038 1058571cebfeSYuantian Tang 0x00020004 0x00000043 1059571cebfeSYuantian Tang 0x00020005 0x0000004d 1060571cebfeSYuantian Tang 0x00020006 0x00000058 1061571cebfeSYuantian Tang 0x00020007 0x00000063 1062571cebfeSYuantian Tang 0x00020008 0x0000006e 1063571cebfeSYuantian Tang 1064571cebfeSYuantian Tang 0x00030000 0x00000010 1065571cebfeSYuantian Tang 0x00030001 0x0000001c 1066571cebfeSYuantian Tang 0x00030002 0x00000029 1067571cebfeSYuantian Tang 0x00030003 0x00000036 1068571cebfeSYuantian Tang 0x00030004 0x00000042 1069571cebfeSYuantian Tang 0x00030005 0x0000004f 1070571cebfeSYuantian Tang 0x00030006 0x0000005b 1071571cebfeSYuantian Tang 0x00030007 0x00000068>; 1072571cebfeSYuantian Tang little-endian; 1073571cebfeSYuantian Tang #thermal-sensor-cells = <1>; 1074571cebfeSYuantian Tang }; 1075571cebfeSYuantian Tang 10768897f325SBhaskar Upadhaya pcie@1f0000000 { /* Integrated Endpoint Root Complex */ 10778897f325SBhaskar Upadhaya compatible = "pci-host-ecam-generic"; 10788897f325SBhaskar Upadhaya reg = <0x01 0xf0000000 0x0 0x100000>; 10798897f325SBhaskar Upadhaya #address-cells = <3>; 10808897f325SBhaskar Upadhaya #size-cells = <2>; 10818897f325SBhaskar Upadhaya msi-parent = <&its>; 10828897f325SBhaskar Upadhaya device_type = "pci"; 10838897f325SBhaskar Upadhaya bus-range = <0x0 0x0>; 10848897f325SBhaskar Upadhaya dma-coherent; 10858897f325SBhaskar Upadhaya msi-map = <0 &its 0x17 0xe>; 10868897f325SBhaskar Upadhaya iommu-map = <0 &smmu 0x17 0xe>; 10878897f325SBhaskar Upadhaya /* PF0-6 BAR0 - non-prefetchable memory */ 10886bee93d9SKornel Duleba ranges = <0x82000000 0x1 0xf8000000 0x1 0xf8000000 0x0 0x160000 10898897f325SBhaskar Upadhaya /* PF0-6 BAR2 - prefetchable memory */ 10906bee93d9SKornel Duleba 0xc2000000 0x1 0xf8160000 0x1 0xf8160000 0x0 0x070000 10918897f325SBhaskar Upadhaya /* PF0: VF0-1 BAR0 - non-prefetchable memory */ 10926bee93d9SKornel Duleba 0x82000000 0x1 0xf81d0000 0x1 0xf81d0000 0x0 0x020000 10938897f325SBhaskar Upadhaya /* PF0: VF0-1 BAR2 - prefetchable memory */ 10946bee93d9SKornel Duleba 0xc2000000 0x1 0xf81f0000 0x1 0xf81f0000 0x0 0x020000 10958897f325SBhaskar Upadhaya /* PF1: VF0-1 BAR0 - non-prefetchable memory */ 10966bee93d9SKornel Duleba 0x82000000 0x1 0xf8210000 0x1 0xf8210000 0x0 0x020000 10978897f325SBhaskar Upadhaya /* PF1: VF0-1 BAR2 - prefetchable memory */ 10986bee93d9SKornel Duleba 0xc2000000 0x1 0xf8230000 0x1 0xf8230000 0x0 0x020000 1099b1520d8bSClaudiu Manoil /* BAR4 (PF5) - non-prefetchable memory */ 11006bee93d9SKornel Duleba 0x82000000 0x1 0xfc000000 0x1 0xfc000000 0x0 0x400000>; 11018897f325SBhaskar Upadhaya 11028897f325SBhaskar Upadhaya enetc_port0: ethernet@0,0 { 11038897f325SBhaskar Upadhaya compatible = "fsl,enetc"; 11048897f325SBhaskar Upadhaya reg = <0x000000 0 0 0 0>; 11051a4bfe0fSVladimir Oltean status = "disabled"; 11068897f325SBhaskar Upadhaya }; 11071a4bfe0fSVladimir Oltean 11088897f325SBhaskar Upadhaya enetc_port1: ethernet@0,1 { 11098897f325SBhaskar Upadhaya compatible = "fsl,enetc"; 11108897f325SBhaskar Upadhaya reg = <0x000100 0 0 0 0>; 11111a4bfe0fSVladimir Oltean status = "disabled"; 11128897f325SBhaskar Upadhaya }; 11131a4bfe0fSVladimir Oltean 1114b1520d8bSClaudiu Manoil enetc_port2: ethernet@0,2 { 1115b1520d8bSClaudiu Manoil compatible = "fsl,enetc"; 1116b1520d8bSClaudiu Manoil reg = <0x000200 0 0 0 0>; 1117b1520d8bSClaudiu Manoil phy-mode = "internal"; 1118b1520d8bSClaudiu Manoil status = "disabled"; 1119b1520d8bSClaudiu Manoil 1120b1520d8bSClaudiu Manoil fixed-link { 11212c832fe4SVladimir Oltean speed = <2500>; 1122b1520d8bSClaudiu Manoil full-duplex; 11238fcea7beSVladimir Oltean pause; 1124b1520d8bSClaudiu Manoil }; 1125b1520d8bSClaudiu Manoil }; 1126b1520d8bSClaudiu Manoil 11278488d8e9SClaudiu Manoil enetc_mdio_pf3: mdio@0,3 { 11288488d8e9SClaudiu Manoil compatible = "fsl,enetc-mdio"; 11298488d8e9SClaudiu Manoil reg = <0x000300 0 0 0 0>; 11308488d8e9SClaudiu Manoil #address-cells = <1>; 11318488d8e9SClaudiu Manoil #size-cells = <0>; 11328488d8e9SClaudiu Manoil }; 11331a4bfe0fSVladimir Oltean 113449401003SY.b. Lu ethernet@0,4 { 113549401003SY.b. Lu compatible = "fsl,enetc-ptp"; 113649401003SY.b. Lu reg = <0x000400 0 0 0 0>; 113799314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_HWACCEL 3>; 113849401003SY.b. Lu little-endian; 1139ab84bad5SYangbo Lu fsl,extts-fifo; 114049401003SY.b. Lu }; 1141b1520d8bSClaudiu Manoil 1142630952e1SMichael Walle mscc_felix: ethernet-switch@0,5 { 1143b1520d8bSClaudiu Manoil reg = <0x000500 0 0 0 0>; 1144b1520d8bSClaudiu Manoil /* IEP INT_B */ 1145b1520d8bSClaudiu Manoil interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1146630952e1SMichael Walle status = "disabled"; 1147b1520d8bSClaudiu Manoil 1148e426d63eSAlex Marginean mscc_felix_ports: ports { 1149b1520d8bSClaudiu Manoil #address-cells = <1>; 1150b1520d8bSClaudiu Manoil #size-cells = <0>; 1151b1520d8bSClaudiu Manoil 1152b1520d8bSClaudiu Manoil /* External ports */ 1153b1520d8bSClaudiu Manoil mscc_felix_port0: port@0 { 1154b1520d8bSClaudiu Manoil reg = <0>; 1155b1520d8bSClaudiu Manoil status = "disabled"; 1156b1520d8bSClaudiu Manoil }; 1157b1520d8bSClaudiu Manoil 1158b1520d8bSClaudiu Manoil mscc_felix_port1: port@1 { 1159b1520d8bSClaudiu Manoil reg = <1>; 1160b1520d8bSClaudiu Manoil status = "disabled"; 1161b1520d8bSClaudiu Manoil }; 1162b1520d8bSClaudiu Manoil 1163b1520d8bSClaudiu Manoil mscc_felix_port2: port@2 { 1164b1520d8bSClaudiu Manoil reg = <2>; 1165b1520d8bSClaudiu Manoil status = "disabled"; 1166b1520d8bSClaudiu Manoil }; 1167b1520d8bSClaudiu Manoil 1168b1520d8bSClaudiu Manoil mscc_felix_port3: port@3 { 1169b1520d8bSClaudiu Manoil reg = <3>; 1170b1520d8bSClaudiu Manoil status = "disabled"; 1171b1520d8bSClaudiu Manoil }; 1172b1520d8bSClaudiu Manoil 1173b1520d8bSClaudiu Manoil /* Internal ports */ 1174b1520d8bSClaudiu Manoil mscc_felix_port4: port@4 { 1175b1520d8bSClaudiu Manoil reg = <4>; 1176b1520d8bSClaudiu Manoil phy-mode = "internal"; 1177b340ee02SVladimir Oltean ethernet = <&enetc_port2>; 1178b1520d8bSClaudiu Manoil status = "disabled"; 1179b1520d8bSClaudiu Manoil 1180b1520d8bSClaudiu Manoil fixed-link { 1181b1520d8bSClaudiu Manoil speed = <2500>; 1182b1520d8bSClaudiu Manoil full-duplex; 11838fcea7beSVladimir Oltean pause; 1184b1520d8bSClaudiu Manoil }; 1185b1520d8bSClaudiu Manoil }; 1186b1520d8bSClaudiu Manoil 1187b1520d8bSClaudiu Manoil mscc_felix_port5: port@5 { 1188b1520d8bSClaudiu Manoil reg = <5>; 1189b1520d8bSClaudiu Manoil phy-mode = "internal"; 1190d72e3b4eSVladimir Oltean ethernet = <&enetc_port3>; 1191b1520d8bSClaudiu Manoil status = "disabled"; 1192b1520d8bSClaudiu Manoil 1193b1520d8bSClaudiu Manoil fixed-link { 1194b1520d8bSClaudiu Manoil speed = <1000>; 1195b1520d8bSClaudiu Manoil full-duplex; 11968fcea7beSVladimir Oltean pause; 1197b1520d8bSClaudiu Manoil }; 1198b1520d8bSClaudiu Manoil }; 1199b1520d8bSClaudiu Manoil }; 1200b1520d8bSClaudiu Manoil }; 1201b1520d8bSClaudiu Manoil 1202b1520d8bSClaudiu Manoil enetc_port3: ethernet@0,6 { 1203b1520d8bSClaudiu Manoil compatible = "fsl,enetc"; 1204b1520d8bSClaudiu Manoil reg = <0x000600 0 0 0 0>; 1205b1520d8bSClaudiu Manoil phy-mode = "internal"; 1206b1520d8bSClaudiu Manoil status = "disabled"; 1207b1520d8bSClaudiu Manoil 1208b1520d8bSClaudiu Manoil fixed-link { 1209b1520d8bSClaudiu Manoil speed = <1000>; 1210b1520d8bSClaudiu Manoil full-duplex; 12118fcea7beSVladimir Oltean pause; 1212b1520d8bSClaudiu Manoil }; 12138897f325SBhaskar Upadhaya }; 1214dfee46f1SMichael Walle 1215dfee46f1SMichael Walle rcec@1f,0 { 1216dfee46f1SMichael Walle reg = <0x00f800 0 0 0 0>; 1217dfee46f1SMichael Walle /* IEP INT_A */ 1218dfee46f1SMichael Walle interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 1219dfee46f1SMichael Walle }; 12208897f325SBhaskar Upadhaya }; 1221791c88caSBiwen Li 1222b764dc6cSVladimir Oltean /* Integrated Endpoint Register Block */ 1223b764dc6cSVladimir Oltean ierb@1f0800000 { 1224b764dc6cSVladimir Oltean compatible = "fsl,ls1028a-enetc-ierb"; 1225b764dc6cSVladimir Oltean reg = <0x01 0xf0800000 0x0 0x10000>; 1226b764dc6cSVladimir Oltean }; 1227b764dc6cSVladimir Oltean 122871799672SBiwen Li pwm0: pwm@2800000 { 122971799672SBiwen Li compatible = "fsl,vf610-ftm-pwm"; 123071799672SBiwen Li #pwm-cells = <3>; 123171799672SBiwen Li reg = <0x0 0x2800000 0x0 0x10000>; 123271799672SBiwen Li clock-names = "ftm_sys", "ftm_ext", 123371799672SBiwen Li "ftm_fix", "ftm_cnt_clk_en"; 123471799672SBiwen Li clocks = <&clockgen 4 1>, <&clockgen 4 1>, 123571799672SBiwen Li <&rtc_clk>, <&clockgen 4 1>; 123671799672SBiwen Li status = "disabled"; 123771799672SBiwen Li }; 123871799672SBiwen Li 123971799672SBiwen Li pwm1: pwm@2810000 { 124071799672SBiwen Li compatible = "fsl,vf610-ftm-pwm"; 124171799672SBiwen Li #pwm-cells = <3>; 124271799672SBiwen Li reg = <0x0 0x2810000 0x0 0x10000>; 124371799672SBiwen Li clock-names = "ftm_sys", "ftm_ext", 124471799672SBiwen Li "ftm_fix", "ftm_cnt_clk_en"; 124571799672SBiwen Li clocks = <&clockgen 4 1>, <&clockgen 4 1>, 124671799672SBiwen Li <&rtc_clk>, <&clockgen 4 1>; 124771799672SBiwen Li status = "disabled"; 124871799672SBiwen Li }; 124971799672SBiwen Li 125071799672SBiwen Li pwm2: pwm@2820000 { 125171799672SBiwen Li compatible = "fsl,vf610-ftm-pwm"; 125271799672SBiwen Li #pwm-cells = <3>; 125371799672SBiwen Li reg = <0x0 0x2820000 0x0 0x10000>; 125471799672SBiwen Li clock-names = "ftm_sys", "ftm_ext", 125571799672SBiwen Li "ftm_fix", "ftm_cnt_clk_en"; 125671799672SBiwen Li clocks = <&clockgen 4 1>, <&clockgen 4 1>, 125771799672SBiwen Li <&rtc_clk>, <&clockgen 4 1>; 125871799672SBiwen Li status = "disabled"; 125971799672SBiwen Li }; 126071799672SBiwen Li 126171799672SBiwen Li pwm3: pwm@2830000 { 126271799672SBiwen Li compatible = "fsl,vf610-ftm-pwm"; 126371799672SBiwen Li #pwm-cells = <3>; 126471799672SBiwen Li reg = <0x0 0x2830000 0x0 0x10000>; 126571799672SBiwen Li clock-names = "ftm_sys", "ftm_ext", 126671799672SBiwen Li "ftm_fix", "ftm_cnt_clk_en"; 126771799672SBiwen Li clocks = <&clockgen 4 1>, <&clockgen 4 1>, 126871799672SBiwen Li <&rtc_clk>, <&clockgen 4 1>; 126971799672SBiwen Li status = "disabled"; 127071799672SBiwen Li }; 127171799672SBiwen Li 127271799672SBiwen Li pwm4: pwm@2840000 { 127371799672SBiwen Li compatible = "fsl,vf610-ftm-pwm"; 127471799672SBiwen Li #pwm-cells = <3>; 127571799672SBiwen Li reg = <0x0 0x2840000 0x0 0x10000>; 127671799672SBiwen Li clock-names = "ftm_sys", "ftm_ext", 127771799672SBiwen Li "ftm_fix", "ftm_cnt_clk_en"; 127871799672SBiwen Li clocks = <&clockgen 4 1>, <&clockgen 4 1>, 127971799672SBiwen Li <&rtc_clk>, <&clockgen 4 1>; 128071799672SBiwen Li status = "disabled"; 128171799672SBiwen Li }; 128271799672SBiwen Li 128371799672SBiwen Li pwm5: pwm@2850000 { 128471799672SBiwen Li compatible = "fsl,vf610-ftm-pwm"; 128571799672SBiwen Li #pwm-cells = <3>; 128671799672SBiwen Li reg = <0x0 0x2850000 0x0 0x10000>; 128771799672SBiwen Li clock-names = "ftm_sys", "ftm_ext", 128871799672SBiwen Li "ftm_fix", "ftm_cnt_clk_en"; 128971799672SBiwen Li clocks = <&clockgen 4 1>, <&clockgen 4 1>, 129071799672SBiwen Li <&rtc_clk>, <&clockgen 4 1>; 129171799672SBiwen Li status = "disabled"; 129271799672SBiwen Li }; 129371799672SBiwen Li 129471799672SBiwen Li pwm6: pwm@2860000 { 129571799672SBiwen Li compatible = "fsl,vf610-ftm-pwm"; 129671799672SBiwen Li #pwm-cells = <3>; 129771799672SBiwen Li reg = <0x0 0x2860000 0x0 0x10000>; 129871799672SBiwen Li clock-names = "ftm_sys", "ftm_ext", 129971799672SBiwen Li "ftm_fix", "ftm_cnt_clk_en"; 130071799672SBiwen Li clocks = <&clockgen 4 1>, <&clockgen 4 1>, 130171799672SBiwen Li <&rtc_clk>, <&clockgen 4 1>; 130271799672SBiwen Li status = "disabled"; 130371799672SBiwen Li }; 130471799672SBiwen Li 130571799672SBiwen Li pwm7: pwm@2870000 { 130671799672SBiwen Li compatible = "fsl,vf610-ftm-pwm"; 130771799672SBiwen Li #pwm-cells = <3>; 130871799672SBiwen Li reg = <0x0 0x2870000 0x0 0x10000>; 130971799672SBiwen Li clock-names = "ftm_sys", "ftm_ext", 131071799672SBiwen Li "ftm_fix", "ftm_cnt_clk_en"; 131171799672SBiwen Li clocks = <&clockgen 4 1>, <&clockgen 4 1>, 131271799672SBiwen Li <&rtc_clk>, <&clockgen 4 1>; 131371799672SBiwen Li status = "disabled"; 131471799672SBiwen Li }; 131571799672SBiwen Li 1316791c88caSBiwen Li rcpm: power-controller@1e34040 { 1317791c88caSBiwen Li compatible = "fsl,ls1028a-rcpm", "fsl,qoriq-rcpm-2.1+"; 1318791c88caSBiwen Li reg = <0x0 0x1e34040 0x0 0x1c>; 1319791c88caSBiwen Li #fsl,rcpm-wakeup-cells = <7>; 1320d9245428SBiwen Li little-endian; 1321791c88caSBiwen Li }; 1322791c88caSBiwen Li 1323791c88caSBiwen Li ftm_alarm0: timer@2800000 { 1324791c88caSBiwen Li compatible = "fsl,ls1028a-ftm-alarm"; 1325791c88caSBiwen Li reg = <0x0 0x2800000 0x0 0x10000>; 1326791c88caSBiwen Li fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; 1327791c88caSBiwen Li interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1328dd3d936aSBiwen Li status = "disabled"; 1329dd3d936aSBiwen Li }; 1330dd3d936aSBiwen Li 1331dd3d936aSBiwen Li ftm_alarm1: timer@2810000 { 1332dd3d936aSBiwen Li compatible = "fsl,ls1028a-ftm-alarm"; 1333dd3d936aSBiwen Li reg = <0x0 0x2810000 0x0 0x10000>; 1334dd3d936aSBiwen Li fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; 1335dd3d936aSBiwen Li interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1336dd3d936aSBiwen Li status = "disabled"; 1337791c88caSBiwen Li }; 13388897f325SBhaskar Upadhaya }; 13397f538f19SWen He 13408897f325SBhaskar Upadhaya}; 1341