Home
last modified time | relevance | path

Searched +full:dll +full:- +full:config (Results 1 – 25 of 103) sorted by relevance

12345

/openbmc/linux/drivers/mmc/host/
H A Dsdhci-msm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
5 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
23 #include "sdhci-cqhci.h"
24 #include "sdhci-pltfm.h"
123 #define INVALID_TUNING_PHASE -1
137 /* Max load for eMMC Vdd-io supply */
141 msm_host->var_ops->msm_readl_relaxed(host, offset)
144 msm_host->var_ops->msm_writel_relaxed(val, host, offset)
300 return msm_host->offset; in sdhci_priv_msm_offset()
[all …]
H A Dsdhci-esdhc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
26 /* pltfm-specific */
89 /* DLL Config 0 Register */
95 /* DLL Config 1 Register */
99 /* DLL Status 0 Register */
H A Dsdhci-xenon-phy.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Date: 2016-8-24
17 #include "sdhci-pltfm.h"
18 #include "sdhci-xenon.h"
128 /* Offset of DLL Control register */
132 /* DLL Update Enable bit */
209 params = devm_kzalloc(mmc_dev(host->mmc), sizeof(*params), GFP_KERNEL); in xenon_alloc_emmc_phy()
211 return -ENOMEM; in xenon_alloc_emmc_phy()
213 priv->phy_params = params; in xenon_alloc_emmc_phy()
214 if (priv->phy_type == EMMC_5_0_PHY) in xenon_alloc_emmc_phy()
[all …]
H A Dsdhci-st.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Based on sdhci-cns3xxx.c
18 #include "sdhci-pltfm.h"
88 #define ST_TOP_MMC_DLY_FIX_OFF(x) (x - 0x8)
90 /* TOP config registers to manage static and dynamic delay */
102 /* register to provide the phase-shift value for DLL */
119 * DLL procedure has finished before switching to ultra-speed modes.
139 * flashSS sub-system which needs to be configured to be compliant to eMMC 4.5
145 struct mmc_host *mhost = host->mmc; in st_mmcss_cconfig()
148 if (!of_device_is_compatible(np, "st,sdhci-stih407")) in st_mmcss_cconfig()
[all …]
/openbmc/u-boot/arch/arm/mach-exynos/
H A Ddmc_init_exynos4.c23 * MA 02111-1307 USA
26 #include <config.h>
55 &dmc->phycontrol1); in phy_control_reset()
57 &dmc->phycontrol1); in phy_control_reset()
60 &dmc->phycontrol0); in phy_control_reset()
62 &dmc->phycontrol0); in phy_control_reset()
76 &dmc->directcmd); in dmc_config_mrs()
83 * DLL Parameter Setting: in dmc_init()
87 writel(mem.control1, &dmc->phycontrol1); in dmc_init()
94 writel(mem.zqcontrol, &dmc->phyzqcontrol); in dmc_init()
[all …]
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-multimedia/jack/jack/
H A D0002-Fix-all-DeprecationWarning-invalid-escape-sequence.patch2 From: =?UTF-8?q?Micka=C3=ABl=20Schoentgen?= <contact@tiger-222.fr>
5 MIME-Version: 1.0
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
9 Signed-off-by: Mickaël Schoentgen <contact@tiger-222.fr>
10 ---
11 Upstream-Status: Backport [from waflib not jack: https://gitlab.com/ita1024/waf/-/commit/412a9b819e…
13 waflib/Build.py | 2 +-
14 waflib/ConfigSet.py | 2 +-
15 waflib/Context.py | 2 +-
[all …]
/openbmc/u-boot/drivers/power/
H A DKconfig17 config SUNXI_NO_PMIC
19 ---help---
22 config AXP152_POWER
27 ---help---
31 config AXP209_POWER
36 ---help---
40 config AXP221_POWER
45 ---help---
49 config AXP809_POWER
54 ---help---
[all …]
/openbmc/qemu/hw/misc/
H A Dmps2-scc.c29 #include "hw/misc/mps2-scc.h"
31 #include "hw/qdev-properties.h"
53 REG32(DLL, 0x100)
60 return extract32(s->id, 4, 8); in scc_partno()
116 if (function != 1 || device >= s->num_oscclk) { in scc_cfg_write()
118 "MPS2 SCC config write: bad function %d device %d\n", in scc_cfg_write()
123 s->oscclk[device] = value; in scc_cfg_write()
134 if (function != 1 || device >= s->num_oscclk) { in scc_cfg_read()
136 "MPS2 SCC config read: bad function %d device %d\n", in scc_cfg_read()
141 *value = s->oscclk[device]; in scc_cfg_read()
[all …]
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-graphics/vk-gl-cts/files/
H A D0001-use-library-sonames-for-linking.patch3 Date: Thu, 23 Sep 2021 19:36:43 -0400
11 Upstream-Status: Denied [https://github.com/KhronosGroup/VK-GL-CTS/pull/288]
12 Signed-off-by: Trevor Woerner <twoerner@gmail.com>
13 ---
14 framework/egl/egluGLContextFactory.cpp | 4 ++--
15 framework/egl/wrapper/eglwLibrary.cpp | 2 +-
16 framework/platform/android/tcuAndroidPlatform.cpp | 2 +-
17 framework/platform/lnx/X11/tcuLnxX11EglDisplayFactory.cpp | 2 +-
18 .../platform/lnx/wayland/tcuLnxWaylandEglDisplayFactory.cpp | 2 +-
19 framework/platform/surfaceless/tcuSurfacelessPlatform.cpp | 6 +++---
[all …]
/openbmc/linux/arch/arm/mach-omap2/
H A Dsleep34xx.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Karthik Dasu <karthik-dp@ti.com>
9 * Richard Woodruff <r-woodruff2@ti.com>
57 * with non-Thumb-2-capable firmware.
86 .arch armv7-a
89 stmfd sp!, {r4 - r11, lr} @ save registers on stack
103 ldmfd sp!, {r4 - r11, pc}
115 * omap34xx_cpu_suspend() - This bit of code saves the CPU context if needed
121 * - only the minimum set of functions gets copied to internal SRAM at boot
122 * and after wake-up from OFF mode, cf. omap_push_sram_idle. The function
[all …]
/openbmc/u-boot/arch/arm/cpu/arm1136/mx35/
H A Dmx35_sdram.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <asm/arch/imx-regs.h>
34 while (wait--) in dram_wait()
49 cfg_reg = &esdc->esdcfg0; in mx3_setup_sdram_bank()
50 ctl_reg = &esdc->esdctl0; in mx3_setup_sdram_bank()
53 cfg_reg = &esdc->esdcfg1; in mx3_setup_sdram_bank()
54 ctl_reg = &esdc->esdctl1; in mx3_setup_sdram_bank()
63 ctlval = (row - 11) << 24 | (col - 8) << 20 | (dsize << 16); in mx3_setup_sdram_bank()
68 writel(val, &esdc->esdmisc); in mx3_setup_sdram_bank()
70 writel(val, &esdc->esdmisc); in mx3_setup_sdram_bank()
[all …]
/openbmc/openbmc/poky/meta/recipes-devtools/python/
H A Dpython3-rpds-py-crates.inc1 # Autogenerated with 'bitbake -c update_crates python3-rpds-py'
8 crate://crates.io/cfg-if/1.0.0 \
14 crate://crates.io/portable-atomic/1.6.0 \
15 crate://crates.io/proc-macro2/1.0.86 \
17 crate://crates.io/pyo3-build-config/0.22.6 \
18 crate://crates.io/pyo3-ffi/0.22.6 \
19 crate://crates.io/pyo3-macros/0.22.6 \
20 crate://crates.io/pyo3-macros-backend/0.22.6 \
21 crate://crates.io/python3-dll-a/0.2.10 \
25 crate://crates.io/target-lexicon/0.12.14 \
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dsdhci-msm.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/sdhci-msm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SDHCI controller (sdhci-msm)
10 - Bhupesh Sharma <bhupesh.sharma@linaro.org>
19 - enum:
20 - qcom,sdhci-msm-v4
22 - items:
23 - enum:
[all …]
/openbmc/u-boot/drivers/ddr/microchip/
H A Dddr2.c1 // SPDX-License-Identifier: GPL-2.0+
26 RECALIB_CNT(0x10), &ddr2_phy->dll_recalib); in ddr2_phy_init()
35 writel(pad_ctl, &ddr2_phy->pad_ctrl); in ddr2_phy_init()
39 SCL_ODTCSWW, &ddr2_phy->scl_config_1); in ddr2_phy_init()
42 writel(SCL_CSEN | SCL_WCAS_LAT(WL), &ddr2_phy->scl_config_2); in ddr2_phy_init()
45 writel(SCL_CAPCLKDLY(3) | SCL_DDRCLKDLY(4), &ddr2_phy->scl_latency); in ddr2_phy_init()
56 writel(SCL_START | SCL_EN, &ddr2_phy->scl_start); in ddr2_phy_calib_start()
59 return wait_for_bit_le32(&ddr2_phy->scl_start, SCL_LUBPASS, in ddr2_phy_calib_start()
73 writel(i * MIN_LIM_WIDTH, &ctrl->tsel); in ddr_set_arbiter()
74 writel(param->min_limit, &ctrl->minlim); in ddr_set_arbiter()
[all …]
H A Dddr2_regs.h1 /* SPDX-License-Identifier: GPL-2.0+ */
40 /* Arbiter Config */
45 /* Refresh Config */
50 /* Power Config */
62 /* Delay Config */
68 /* Xfer Config */
123 /* PHY DLL RECALIBRATE */
/openbmc/u-boot/scripts/kconfig/lxdialog/
H A Dcheck-lxdialog.sh2 # SPDX-License-Identifier: GPL-2.0
8 pkg-config --libs ncursesw 2>/dev/null && exit
9 pkg-config --libs ncurses 2>/dev/null && exit
10 for ext in so a dll.a dylib ; do
12 $cc -print-file-name=lib${lib}.${ext} | grep -q /
13 if [ $? -eq 0 ]; then
14 echo "-l${lib}"
25 if pkg-config --cflags ncursesw 2>/dev/null; then
26 echo '-DCURSES_LOC="<ncurses.h>" -DNCURSES_WIDECHAR=1'
27 elif pkg-config --cflags ncurses 2>/dev/null; then
[all …]
/openbmc/openbmc/poky/meta/recipes-core/busybox/busybox/
H A Dbusybox-cross-menuconfig.patch2 Date: Sun, 3 Mar 2013 12:31:40 -0600
3 Subject: [PATCH] menuconfig,check-lxdiaglog.sh: Allow specification of ncurses location
5 Upstream-Status: Submitted
14 ---
25 check-lxdialog.sh for environments such as the Yocto Project. Adding
29 Signed-off-by: Jason Wessel <jason.wessel@windriver.com>
31 cc: linux-kbuild@vger.kernel.org
32 ---
33 scripts/kconfig/lxdialog/Makefile | 2 +-
34 scripts/kconfig/lxdialog/check-lxdialog.sh | 8 ++++++++
[all …]
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-dbs/psqlodbc/files/
H A Dpsqlodbc-fix-for-ptest-support.patch12 Upstream-Status: Inappropriate [OE ptest specific]
14 Signed-off-by: Jackie Huang <jackie.huang@windriver.com>
16 ---
17 test/Makefile.in | 2 +-
18 test/odbcini-gen.sh | 8 ++++----
19 test/runsuite.c | 20 ++++++++++----------
20 3 files changed, 15 insertions(+), 15 deletions(-)
22 --- a/test/Makefile.in
24 @@ -19,7 +19,7 @@ CPPFLAGS = @CPPFLAGS@ -I.. # config.h
28 -LIBODBC = @LIBODBC@
[all …]
/openbmc/u-boot/drivers/ram/rockchip/
H A Dsdram_rk3188.c1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
12 #include <dt-structs.h>
103 rk_clrsetreg(&cru->cru_softrst_con[5], in ddr_reset()
116 rk_clrsetreg(&cru->cru_softrst_con[5], in ddr_phy_ctl_reset()
128 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); in phy_pctrl_reset()
130 clrbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); in phy_pctrl_reset()
133 setbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); in phy_pctrl_reset()
135 setbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); in phy_pctrl_reset()
151 clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); in phy_dll_bypass_set()
153 setbits_le32(&publ->dllgcr, SBIAS_BYPASS); in phy_dll_bypass_set()
[all …]
H A Dsdram_rk3288.c1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
12 #include <dt-structs.h>
102 rk_clrsetreg(&cru->cru_softrst_con[10], in ddr_reset()
115 rk_clrsetreg(&cru->cru_softrst_con[10], in ddr_phy_ctl_reset()
127 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); in phy_pctrl_reset()
129 clrbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); in phy_pctrl_reset()
132 setbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); in phy_pctrl_reset()
134 setbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); in phy_pctrl_reset()
150 clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); in phy_dll_bypass_set()
152 setbits_le32(&publ->dllgcr, SBIAS_BYPASS); in phy_dll_bypass_set()
[all …]
/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_dfs.c1 // SPDX-License-Identifier: GPL-2.0
72 /* Poll - Wait for Refresh operation completion */ in wait_refresh_op_complete()
82 * Args: target_freq - target frequency
84 * Returns: freq_par - the ratio parameter
95 /* Find the ratio between PLL frequency and ddr-clk */ in ddr3_get_freq_parameter()
108 * Args: freq - target frequency
110 * Returns: MV_OK - success, MV_FAIL - fail
119 DEBUG_DFS_C("DDR3 - DFS - High To Low - Starting DFS procedure to Frequency - ", in ddr3_dfs_high_2_low()
122 /* target frequency - 100MHz */ in ddr3_dfs_high_2_low()
131 /* Configure - DRAM DLL final state after DFS is complete - Enable */ in ddr3_dfs_high_2_low()
[all …]
/openbmc/u-boot/drivers/ddr/fsl/
H A Dctrl_regs.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2008-2016 Freescale Semiconductor, Inc.
4 * Copyright 2017-2018 NXP Semiconductor
29 * Rtt(nominal) - DDR2:
34 * Rtt(nominal) - DDR3:
49 * if (popts->dimmslot[i].num_valid_cs
50 * && (popts->cs_local_opts[2*i].odt_rd_cfg
51 * || popts->cs_local_opts[2*i].odt_wr_cfg)) {
155 unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */ in set_csn_config()
174 if (!popts->memctl_interleaving) in set_csn_config()
[all …]
/openbmc/u-boot/drivers/serial/
H A Dns16550.c66 writeb(value, addr + (1 << shift) - 1); in serial_out_shift()
83 return readb(addr + (1 << shift) - 1); in serial_in_shift()
97 struct ns16550_platdata *plat = port->plat; in ns16550_writeb()
100 offset *= 1 << plat->reg_shift; in ns16550_writeb()
101 addr = (unsigned char *)plat->base + offset; in ns16550_writeb()
105 * these options at run-time, so use the existing CONFIG options. in ns16550_writeb()
107 serial_out_shift(addr + plat->reg_offset, plat->reg_shift, value); in ns16550_writeb()
112 struct ns16550_platdata *plat = port->plat; in ns16550_readb()
115 offset *= 1 << plat->reg_shift; in ns16550_readb()
116 addr = (unsigned char *)plat->base + offset; in ns16550_readb()
[all …]
/openbmc/u-boot/include/configs/
H A Dsbc8349.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * WindRiver SBC8349 U-Boot configuration file.
7 * Based on the MPC8349EMDS config.
24 /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
64 * 32-bit data path mode.
66 * Please note that using this mode for devices with the real density of 64-bit
70 * 128MB); normally this define should be used for devices with real 32-bit
98 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
103 /* set burst length to 8 for 32-bit data path */
104 /* DLL,normal,seq,4/2.5, 8 burst len */
[all …]
H A DMPC8349EMDS.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2006-2010
69 * 32-bit data path mode.
71 * Please note that using this mode for devices with the real density of 64-bit
75 * 128MB); normally this define should be used for devices with real 32-bit
88 * DDRCDR - DDR Control Driver Register
121 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
126 /* set burst length to 8 for 32-bit data path */
127 /* DLL,normal,seq,4/2.5, 8 burst len */
130 /* the default burst length is 4 - for 64-bit data path */
[all …]

12345